chipscope manual

8/10/2019 ChipScope Manual

1/22

Depuracin mediante ChipScope Pro


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ChipScope Pro 2

Objetivos

Ver como se utiliza la herramienta ChipScope Pro para realizar

la depuracin del sistema en el dispositivo

Ver los distintos cores que se utilizan con la herramienta

ChipScope Pro


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ChipScope Pro 3

Contenido

Introduccin

Depuracin utilizando ChipScope Pro Insertar un core ChipScope Pro

Resumen

Prctica 6: ChipScope Pro


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ChipScope Pro 4

No hay visibilidad interna

Como accedo al bus de sistema? IP Cores

No se puede acceder a la parteinterna de los cores

Utilizar JTAG Sobrecarga al sistema al establecerla interface con el bloque JTAG

IO Pads

IOP

ads

IOP

ads

IO Pads

Logic BIST Memory BIST Access

Memory

Array

CPUCore

IP

Core

Custom Boundary Scan TAP Controller

Embedded System BusEmbedded System Bus

Custom

Logic

CustomCore

Es problemtico acceder a las seales internas del sistemaDepuracin tradicional


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ChipScope Pro 5

External Logic

AnalyzerPins

Virtex-II Pro

XC2VP20

FF1152

Probe

points

Requieresmucho I/O dedicado a depuracin Llevar las seales a pines de I/O genera problemas de ruteo

Solucin poco flexible Es muy dificultoso agregar pines de depuracin adicionales sin

reimplementar todo el sistema

La visibilidad a las seales internas es muy limitada

Depuracin tradicionalPines dedicados conectados a un analizador lgico


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ChipScope Pro 6

Contenido

Introduccin

Depuracin util izando ChipScope Pro Insertar un core ChipScope Pro

Resumen



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ChipScope Pro 7

Depuracin con Chipscope

IO Pads

IOPa

ds

IOP

ads

IO Pads

Boundary Scan TAP Controller

Embedded System BusEmbedded System Bus

Memory

Array

PPC405Core

IP

Core

CustomCore

ICON

ILA

ILA

ILA

IBA CustomLogic

ILA

Hay visibilidad completa del interiorde la FPGA Se utiliza la herramienta ChipScope Pro

Integrated Logic Analyzer

Se puede acceder a los buses delsistema

Se utiliza la herramienta ChipScope ProIntegrated Bus Analyzer

La depuracin es flexible Se puede acceder a cada seal y/o

remover el acceso en cualquier

momento sin reimplementar el sistema

Usar ChipScope Pro permite el acceso a todas las seales internas


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ChipScope Pro 8

Aurora

OPB SDRAM

User Logic

PLB

Bus

OPB

BusBridge

OPB GPIO

Arbiter

Utilizar los cores de acuerdo a la

necesidad

Integrated Bus Analysis

Core (IBA) PLB and OPB specific

Bus analysis cores

Protocol detection

Debug and verify control,address, and data buses

Agilent Trace Core 2 (ATC2)

Agilent created core enablingOn-chip debug of Xilinx FPGAs using

Agilent FPGA Dynamic Probing

Virtual Input Output

Core (VIO)

Virtual Inputs and Outputs Stimulate logic with pulse

trains

Integrated Logic Analysis

Core (ILA) Access internal nodes and signals

Debug and verify signal behavior

Define detailed trigger conditions

Los cores ChipScope Pro se colocan directamente sobre la lgica

Se puede acceder a cualquier seal y depurar a la velocidad del reloj de sistema


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JTAG

ChipScope Pro

Xilinx FPGA

ILA Block

RAM

Probe

points

No se necesitan pines de I/O para depuracin Se accede a travs del puerto JTAG

Depuracin con ChipScope ProIntegrated Logic Analyzer


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ChipScope Pro 10

ChipScope Pro

JTAG

IBA Block

RAM

System

Busses

No se necesitan pines de I/O para depuracin Se accede a travs del puerto JTAG

On-Chip System Bus Analyzer Puede analizar buses estandar [Processor Local Bus (PLB), On-Chip

Peripheral Bus (OPB)]

Incluye la depuracin de transacciones y detecciones de violaciones alprotocolo del bus

Xilinx FPGA

Depuracin con ChipScope ProIntegrated Bus Analyzer


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ChipScope Pro 11

Contenido

Introduccin

Depuracin utilizando ChipScope Pro Insertar un core ChipScope Pro

Resumen



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ChipScope Pro 12

Agregado de cores de depuracin

FPGA Design

HDL or Netlis t

FPGA DesignFPGA Design

HDL or Netlis tHDL or Netlis t

Design

Synthesis

DesignDesign

SynthesisSynthesis

ImplementationImplementationImplementation

FPGA

Configuration

FPGAFPGA

ConfigurationConfiguration

Debug

Verification

DebugDebug

VerificationVerification

Real-time

Control

RealReal--timetime

ControlControl

JTAG

Xilinx CORE Generator System

ChipScope Pro Analyzer

FPGA Design

Netlist

FPGA DesignFPGA Design

NetlistNetlist

Netlis t MergeNetlis t MergeNetlis t Merge

ImplementationImplementationImplementation

FPGA

Configuration

FPGAFPGA

ConfigurationConfiguration

Pass Fail

Margin Analysis

Pass FailPass Fail

Margin AnalysisMargin Analysis

Real-time

Control

RealReal--timetime

ControlControl

JTAG

ChipScope Pro Core Inserter

ChipScope Pro Analyzer

Xilinx CORE Generator

Genera y agrega coresal comienzo delproceso de diseo

New Source from ProjectNavigator

Agrega un core en

cualquier momento ChipScope Pro Core Inserter

Agrega cores dedepuracin en sistemassintetizados

ChipScope Pro Analyzer Permite ver las seales

internas del sistema


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Browse to directory,give project name,

and click Save

Select core

ChipScope Pro 13


Create New Project

Select family, part


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ChipScope Pro 14


Enable storage

qualifications

Expanded Bit

Values and Funct ions

Based on Match Type

Define the number

of Trigger Ports

and maximum number

of sequence levels


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ChipScope Pro 15


Archivo Readme con

un resumen de losarchivos generados y

su funcin


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ChipScope Pro 16

Automatical ly Launch

the ChipScope Pro

Analyzer

Inserter Called

Automat ically

During Translate

Stage

ChipScope Pro Core Inserter

ChipScope Pro Core

Inserter Add ILA and ATC2 Cores to

an Existing Design Netlist

ChipScope Pro and ISE

Integration ChipScope File (.CDC) Added

to Project as a Source,

Associated With the Top Level

Design Source

User Double-Clicks .CDC to

Set Parameters and

Connections

Versions of ISE and

ChipScope Pro Must Match

Set ChipScope Pro Core

Parameters and

Connections Via This Source

Insert ChipScope Pro Cores in an existing design


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ChipScope Pro 17

Chipscope Pro Core Inserter

ChipScope Pro Core Inserter can now see entire

design NGCBUILD is used

to merge top-level

netlist with all underlying

cores and sub-netlists Encrypted files appear

as black-boxes with

ENCRYPTED tag

Cores appear as

levels of hierarchy

in Hierarchy Browser

Easily connect Chipscope Pro cores in the design


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ChipScope Pro 18

PC Based Interface Makes FPGA Debug

Easy

Access ChipScope cores via JTAG or user defined Trace port

Configure FPGA, define trigger conditions, and view data viaChipScope Pro analyzer running on a PC

ChipScope Pro Analyzer functions as a logicChipScope Pro Analyzer functions as a logic

analyzer, bus analyzer, and control consoleanalyzer, bus analyzer, and control console


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ChipScope Pro 19

Remote Debug and Verification

ChipScope Pro Analyzer server connected

to Xilinx development board enabled for

remote debug and verification

Debug remote systems fromyour office via ChipScope Pro

Analyzer c lient

ChipScope Pro Analyzer server connected

to fielded system enabled for remote debug

and verification

1. Start server on remote

system

2. Set up server host

connection on client system

3. Open cable connection fromclient system

4. Configure device from client

system

5. Start debug and verification

using ChipScope Pro cores


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ChipScope Pro 20

Outline Introduction

Debugging Using ChipScope Pro Inserting ChipScope Core

Summary

Lab 6: ChipScope Pro Lab


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ChipScope Pro 21

Summary

ChipScope Pro core provides improved visibility and access

Point access from within design

Minimal impact to design

Move to hardware faster

Accelerate evaluation, debug, and verification

Finish faster at the system rate

Increased productivity

Integrated into FPGA design flow

Rapid iteration

Share resources


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ChipScope Pro 22

Outline Introduction

Debugging Using ChipScope Pro Inserting ChipScope Core

Summary

Lab 6: ChipScope Pro Lab

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