® chipscope ila tm xilinx and agilent technologies
TRANSCRIPT
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ChipScope ILATM
Xilinx and Agilent Technologies
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Short Design Cycles are Critical
Time-to-market pressures increase in all market segments
Verification and debug are typically the largest time variable
Designer productivity is critical for reducing design cycle time
Tools to speed verification and debug are required
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Traditional Debug Methods Don’t Work for Today’s Designs
Multi-million gate designs require more testing time
Increasing system speeds reduce probing accuracy
DLLs in FPGAs, Processors, RAMs and ASICs can not be single stepped
BGAs have no external leads for traditional tools
Multi-layer board sizes are shrinking allowing less space for test features
Board probing is becoming impossible for 16+ bit busses
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Typical Board Debug Setup
Scope Probe
Download Cable
Logic Analyzer 40-Pin Pod
before Chipscope ILA
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Preferred Debug Setupwith Chipscope ILA
USB port
Serial Port
-or-
JTAG Connections(w/ optional Slave Serial)
Simple!
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Xilinx’ ChipScope ILA Solution
Logic analysis core integrated in the FPGA— Software interface to monitor and analyze results— Access to all internal design nodes— Many flexible trigger options— Operates at the full system speed synchronous to
the design clock up to 155 MHz— Does not require single stepping the design — Virtex, Virtex-E and Spartan II compatible
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Xilinx Partners with Agilent Technologies
Industry leaders join forces to provide integrated verification solutions
ChipScope ILA developed for Agilent compatibility
Allows further system-level analysis with leading tools
Agilent Technologies16702B Logic Analyzer
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ChipScope ILA System
Control
USERFUNCTION
ILA
USERFUNCTION
USERFUNCTION
ILA
ILA
Chipscope ILA
PC running ChipScope
MultiLINX Cable orParallel Cable III
JTAGConnection
Target Board
Target FPGAwith ILA cores
JTAG
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ChipScope ILA FeaturesCategory ChipScope ILAMax number of ILA capture cores per device Up to 15Max number of data samples per core 4096Max data sample width 256
Max trigger width 64
Optional trigger separate from data YesChange data or trigger nets without recompiling YesTrigger range comparison YesTrigger at any sample position YesMultiple triggers per sample buffer YesPulse width duration measurement YesTrigger event count measurement YesMulti-level trigger macros Yes
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ChipScope ILA Components
Two Cores— ICON control core for communication via the JTAG
port— ILA capture core for trigger and trace capture
ChipScope Software— Used for configuration, setup, and trace display
Download Cable— MultiLINX : communicates via USB / RS232— Parallel Cable III : communicates via parallel port
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ICON Core Fundamentals
Provides communication and control to ILA and future Xilinx ChipScope cores
One ICON per device supports up to 15 ILAs
Uses BSCAN_VIRTEX special block
USER1 scan chain used for ILA modifications— Write to ILA trigger control registers— Read Trigger Status— Data read and status
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ILA Core Fundamentals
Trigger settings are in-system changeable without affecting the user logic
Uses Virtex specific features to reduce area and to improve speed and functionality
User-selectable trigger functionality Parameterizable data and trigger width
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ChipScope CLBResource Utilization
Single basic ILA with ICON core
Trigger/DataWidth Flops LUTs Slices Percentage
of XCV10002 125 143 72 0.58 %4 128 151 76 0.62 %8 134 167 84 0.68 %
16 146 199 100 0.81 %
32 173 265 133 1.08 %64 222 395 198 1.61 %
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ChipScope Block RAMResource Utilization
Single basic ILA with ICON core
Trigger/DataWidth
256samples
512samples
1024samples
2048samples
4096samples
2 1 unit 1 unit 1 unit 1 unit 2 units4 1 unit 1 unit 1 unit 2 units 4 units
8 1 unit 1 unit 2 units 4 units 8 units
16 1 unit 2 units 4 units 8 units 16 units
32 2 units 4 units 8 units 16 units 32 units
64 4 units 8 units 16 units 32 units 64 units
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ChipScope ILA Software
Provides an easy-to-use graphical interface for— FPGA configuration download— ILA capture setup and trigger modifications— Waveform display for captured traces— Can write the waveforms to VCD format for other waveform
viewers
Communicates to the download cable’s software API
Output format compatible with Agilent Technologies’ 16700 series analyzer
PC-Windows based; Upcoming Solaris support 3Q00
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ChipScope Screen Shot
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Board Requirements
IEEE 1149.1 Boundary Scan chain— Headers for TDI, TCK, TMS, TDO— Works in multi-chip Boundary Scan chains— Works with Boundary Scan chains containing non-
Virtex devices
Headers for GND and VCC of 2.5-5.0V for download cable
For slave-serial programming (MultiLINX only)— Headers for PROGRAM, DONE, INIT, DIN, CCLK
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How to Get Started
Order through Xilinx Silicon Xpresso Café or normal distribution channels— Single-user one-year license for $495 — Single-user one-year license including MultiLINX
cable for $995— Download ChipScope ILA software— Generate ICON and ILA cores through the web— Access documentation through ChipScope
ILA product page on www.xilinx.com
Real-time on-chip debugging is here today!