chapters 4 & 5: lc-3 computer architecture machine instructions assembly language programming in...
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Chapters 4 & 5:
LC-3 Computer
•Architecture
• Machine Instructions
• Assembly language
• Programming in Machine and Assembly Language
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Overview
The LC-3 Computer
16 bit machine, word addressable, 64K or 65,536 locations
Computer Machine Instructions – Computer “native” instructions
- The basic instructions that all programs use on that computer
(The “atomic” unit of work done by a computer)
The Instruction Cycle
- The steps in the execution of a machine language instruction
(Fetch, Decode, Evaluate Address(es), Fetch operand(s), Execute,
and Store results)
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LC-3 Data Path:
CombinationalLogic
State Machine
Storage
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Data Path of the LC-3
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LC-3 Memory Layout
x0000 – x2FFF System: Operating System programs, tables,
and data - Generally off limits to programmer
(Programs run in Supervisor mode)
x3000 – xFDFF User: User Program and Data Area
Area shared by users like you
(Nominally run in non-supervisor mode)
xFE00 – xFFFF Device: I/O Register Addresses
Pseudo memory used for input/output
R0-R7 Registers (16 bit)
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LC-3 Memory Map
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Computer Machine Instruction Formats
What is IN an instruction?• Operation code – what to do
• Input Operand(s) – where to get input operands (memory, registers)
• Output Operand(s) – Where to put results (memory, registers)
What are the major instruction types?• Data Movement (load, store, etc.)
• Operate (add, sub, mult,OR, AND, etc.)
• Control (branch, jump to subroutine, etc.)
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The Instruction Cycle
Steps (or phases):• Fetch Next Instruction from Memory
(PC) (points to) next instruction
PC (PC) + 1
• Decode Fetched Instruction
• Evaluate Address (es) (find where the data is)
• Fetch Operand (s) (get data)
• Execute Operation
• Store Result (if specified)
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The LC-3 Instruction Addressing Modes
• Register (Operand is in one of the 8 registers)
• PC-relative (Operand is “offset” from the (PC) )
• Base + Offset (Base relative) (Operand is “offset” from the contents of a register)
• Immediate (Operand is in the instruction)
• Indirect (The “Operand” actually points to the real address
– rather than being the operand)
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The LC-3 Instruction Addressing Modes
• Register (Operand is in one of the 8 registers)
• Immediate (Operand is in the instruction)
• PC-relative (Operand is “offset” from the (PC) )
• Indirect (The “Operand” actually points to the real address – rather than being the operand)
• Base + Offset (Base relative) (Operand is “offset” from the contents of a register)
Note: no Direct Addressing defined in the LC-3
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LC-3 Instructions (Fig 5.3 – Appendix a)
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Operate Instructions
• Only three operations:
ADD, AND, NOT
• Source and Destination operands are:
Registers
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ADD/AND (Register)
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NOT (Register)
Note: Src and Dstcould be the same register.
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ADD/AND (Immediate)
Note: Immediate field issign-extended.
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Data Movement Instructions
•Load -- read data from memory to register– LD: PC-relative mode [0010 DR PCoffset9]– LDI: indirect mode [1010 DR PCoffset9]– LDR: base+offset mode [0110 DR BaseR offset6]
•Store -- write data from register to memory– ST: PC-relative mode [0011 DR PCoffset9]– STI: indirect mode [1011 DR PCoffset9]– STR: base+offset mode [0111 DR BaseR offset6]
•Load effective address – address saved in register– LEA: immediate mode [1110 DR PCoffset9]
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LD (PC-Relative)
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ST (PC-Relative)
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LDI (Indirect)
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STI (Indirect)
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LDR (Base+Offset)
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STR (Base+Offset)
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LEA (Immediate)
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Branch Instruction
BR [0000 nzp PCoffset9]
• Branch specifies one or more condition codes• If the set bit is specified, the branch is taken:
– PC is set to the address specified in the instruction
– Target address is made by adding SEXT(IR[8:0]) to the PC
• If the branch is not taken: - the next sequential instruction (PC) is executed.
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BR
/////////////
///// +
SEXT
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Jump Instruction
JMP BaseR [1100 000 BaseR 000000]
• Jump is an unconditional branch -- always taken.
• Base– Address is contents of the register– Allows any target address.
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TRAP
• Calls a service routine, identified by 8-bit “trap vector.”
• When routine is done, PC is set to the instruction following TRAP.
vector routine
x23 input a character from the keyboard
x21 output a character to the monitor
x25 halt the program
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TRAPS
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Using Branch Instructions
• Compute sum of 12 integers.Numbers start at location x3100. Program starts at location x3000.
R1 x3100R3 0R2 12
R2=0?
R4 M[R1]R3 R3+R4R1 R1+1R2 R2-1
NO
YES
R3: Accumulator for the sum of integers
R1: Array index pointer (Begin with location 3100)
R4: Temporary register to store next integer
R2: Loop counter (Count down from 12)
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Sample Program
Address Instruction Comments
x3000 1 1 1 0 0 0 1 0 1 1 1 1 1 1 1 1 R1 x3100 (PC+0xFF)
x3001 0 1 0 1 0 1 1 0 1 1 1 0 0 0 0 0 R3 0
x3002 0 1 0 1 0 1 0 0 1 0 1 0 0 0 0 0 R2 0
x3003 0 0 0 1 0 1 0 0 1 0 1 0 1 1 0 0 R2 12
x3004 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 1 If Z, goto x300A (PC+5)
x3005 0 1 1 0 1 0 0 0 0 1 0 0 0 0 0 0 Load next value to R4
x3006 0 0 0 1 0 1 1 0 1 1 0 0 0 0 0 1 Add to R3
x3007 0 0 0 1 0 0 1 0 0 1 1 0 0 0 0 1 Increment R1 (pointer)
X3008 0 0 0 1 0 1 0 0 1 0 1 1 1 1 1 1 Decrement R2 (counter)
x3009 0 0 0 0 1 1 1 1 1 1 1 1 1 0 1 0 Goto x3004 (PC-6)
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Example 1: Multiply
• This program multiplies two unsigned integers in R4 and R5.
x3200 0101010010100000x3201 0001010010000100x3202 0001101101111111x3203 0000011111111101x3204 1111000000100101
clear R2
add R4 to R2
decrement R5
R5 = 0?
HALT
No
Yes
R2 <- 0R2 <- R2 + R4 R5 <- R5 – 1BRzp x3201HALT