chapters 1 and 3 arm processor architecture -...
TRANSCRIPT
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Chapters1and3ARMProcessorArchitecture
EmbeddedSystemswithARMCortext-MUpdated:Monday,February5,2018
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ALittleaboutARM– Thecompany
• Originally AcornRISCMachine(ARM)• Later AdvancedRISCMachine• ThenitbecameARMLtdownedbyARMHoldings(parentcompany)• In2016SoftBank boughtARMfor$31billion• ARM:
• Developsthearchitectureandlicensesittoothercompanies• Othercompaniesdesigntheirownproductsthatimplementoneofthosearchitectures — including systems-
on-chips (SoC)and systems-on-modules (SoM)thatincorporatememory,interfaces,radios,etc.• Italsodesigns coresthatimplementthis instructionset andlicensesthesedesignstoanumberofcompanies
thatincorporatethosecoredesignsintotheirownproducts.• ARMProcessors
• RISCbasedprocessors• In2010alone,6.1billionARM-basedprocessor,representing95%ofsmartphones,35% ofdigitaltelevisions
andset-topboxesand10% ofmobilecomputers• over100billionARMprocessorsproducedasof2017• Themostwidelyused instructionsetarchitecture intermsofquantityproduced
https://en.wikipedia.org/wiki/ARM_architecture
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https://en.wikipedia.org/wiki/ARM_architecture
M
R
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ARMFamilyandArchitecture
CPU
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ARMFAMILYTREE
CORTEX-
CORTEX-
CORTEX-
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ARMCortexProcessors
6
• ARMCortex-A family:• Applicationsprocessors• SupportOSandhigh-performanceapplications
• SuchasSmartphones,SmartTV
• ARMCortex-R family:• Real-timeprocessorswithhighperformanceandhighreliability
• Supportreal-timeprocessingandmission-criticalcontrol
• ARMCortex-M family:• Microcontroller• Cost-sensitive,supportSoC
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CORTEX-• Cortex-Misagreattrade-offbetweenperformance,cost,efficiency;usedforIoT,variousapplications.
• Hason-chipperipherals• CoreislicensedbyARM
HarvardArchitecture
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CORTEX-M:CORE+Peripherals
• Core• Memory
• FLASH:Non-Volatile/InstructionmemorySRAM/DRAM:Volatile/datamemory
• Processor• ALU• ProcessorControlUnit(CPU)• Registers
• SpecialPurposeRegisters• GeneralPurposeRegisters
• Buses• DataBus• InstructionBus• Busbridgetoconnectdiff.buses• AdvancedHigh-performanceBus(AHB)• AdvancedPeripheralBus(APB)
• GPIO
• Peripherals• ADC• LCDController• SPI• I2C• Etc.
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9
CoreArchitecture
Instructionsanddataarestoredinthesamememory.
Von-Neumann HarvardDataandinstructionsarestoredintoseparatememories.
• Faster• Moreenergyefficient• Differentbussizes
• Simpleandinexpensive• Accesstodataorinstruction,oneatatime
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10
CoreArchitecture
Instructionsanddataarestoredinthesamememory.
Von-Neumann HarvardDataandinstructionsarestoredintoseparatememories.
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ARMSimplifiedBlockDiagramSystemonChip(SoC)
http://www.microdigitaled.com/ARM/ASM_ARM/PowerPoints/ARM_ASM_ppts.htm
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ARMCortex-M4Organization(STM32L4)
12
System-on-a-chip
Instructions
System Bus
Inte
rrup
t Con
trol
ler
(NVI
C)
Memory Protection Unit (MPU)
Instruction Bus
Data Bus
Interrupts`
Mem
ory
Inte
rfac
e
Cortex-M4 Processor Core
SW/JTAG
Inst
ruct
ion
Fetc
h U
nit
Inst
ruct
ion
Dec
oder
ALU
Proc
esso
r Con
trol
U
nit
Trac
e &
Deb
ug
Inte
rfac
e
Flash Memory
AHB to APB Bridge 1
AHB to APB Bridge 2
APB1
ABP2
LCDTIM2TIM3TIM4TIM6TIM7USART2USART3USART4USART5LPUART1
SPI2SPI3I2C1/SMBUSI2C2/SMBUSI2C3/SMBUSUSB 2.0 FSbxCANSWPMI1LPTIM1LPTIM2OpAmp
GPIO Port AGPIO Port BGPIO Port CGPIO Port DGPIO Port EGPIO Port FGPIO Port GGPIO Port H
EXTIWKUPTIM1/PWMTIM8/PWMTIM15TIM16TIM17USART1
SPI1SAI1SAI2DFSDMCOMP1COMP2Firewall
AHB
Bus
Mat
rix
Direction Memory Access (DMA)
Controllers
DataSRAM
Advanced Peripheral Bus
(APB)
Advanced High-performance Bus
(AHB)
FPU
(opt
iona
l)
Sing
le In
stru
ctio
n M
ultip
le D
ata
(DSP
)
NotethattheKitweareusingHasanSTM32F401
HarvardBasedArchitecture
GeneralPurposeIO
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Memory• Memoryisarrangedasaseriesof“locations”
• Eachlocationhasaunique“address”• Eachlocationholdsabyte(byte-addressable)• e.g.thememorylocationataddress0x080001B0containsthebytevalue0x70,i.e.,112
• Thenumberoflocationsinmemoryislimited• e.g.4GBofRAM• 1 Gigabyte(GB)=230 bytes• 232 locationsè 4,294,967,296locations!
• Valuesstoredateachlocationcanrepresenteitherprogramdataorprograminstructions
• e.g.thevalue0x70mightbethecodeusedtotelltheprocessortoaddtwovaluestogether
13
70 BC1801A0
0x00000000
0xFFFFFFFF
0x080001B00x080001AF0x080001AE0x080001AD0x080001AC
Memory
AddressData8 bits 32 bits
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MemoryMapping• Answerthefollowingquestions:
• WhatisthesizeoftheEEPROM?• WhatisthesizeoftheFlash?• WhichMemoryportionisnon-volatile?• WhatdoesSRAMgenerallyusedforinanARMcoreprocessor?
• Whereis0x743address?• Whereis0x1000ABaddress?
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ARMRegisterandALU16ProcessorRegisters13forgeneralpurpose3forspecificpurpose
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ProcessorRegisters
R0R1R2R3R4R5R6R7R8R9
R10R11R12
R13 (SP)R14 (LR)R15 (PC)
32 bits
CONTROLFAULTMASK
PRIMASKBASEPRI
R13 (MSP) R13 (PSP)
xPSR
Low Registers
High Registers
32 bits
SpecialPurposeRegister
GeneralPurposeRegister
16
} Fastestwaytoreadandwrite} Registersarewithintheprocessorchip} Aregisterstores32-bitvalue} CortexM(STM32L)has
} R0-R12:13 general-purposeregisters} R13:Stackpointer(ShadowofMSPorPSP)} R14:Linkregister(LR)} R15:Programcounter(PC)} Specialregisters(xPSR,BASEPRI,PRIMASK,etc.)-
morelater
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ProgramExecution• ProgramCounter(PC)isaregisterthatholdsthememoryaddressofthenextinstructiontobefetchedfromthememory.
4770 2000188B22012100
0x080001B40x080001B20x080001B00x080001AE0x080001AC
PC
MemoryAddress
17
PC=0x080001B0Instruction= 188B or 2000188B or 8B180020
MemoryContentàNextInstruction
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Three-statepipeline:Fetch,Decode,Execution• Pipeliningallowshardwareresourcestobefullyutilized• One32-bitinstructionortwo16-bitinstructionscanbefetched.
18
Pipelineof32-bitinstructions
1.FetchinstructionatPCaddress
2.Decodethe
instruction
3.Executethe
instruction
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LoadingCodeandDataintoMemory
19
SRAM
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ARMRegisterandALU
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Machinecodesarestoredinmemory
r15r14r13r12r11r10r9r8r7r6r5r4r3r2r1r0
ALU47702000188B22012100
pclrsp
0x00000000
0xFFFFFFFF
0x080001B40x080001B20x080001B00x080001AE0x080001AC
Registers Memory
AddressData
CPU21
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FetchInstruction:pc=0x08001ACDecodeInstruction:2100=MOVSr1,#0x00
0x080001ACr15r14r13r12r11r10r9r8r7r6r5r4r3r2r1r0
ALU47702000188B22012100
pclrsp
0x00000000
0xFFFFFFFF
Registers Memory
AddressData
CPU
0x080001B40x080001B20x080001B00x080001AE0x080001AC
22
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ExecuteInstruction:MOVSr1,#0x00
0x080001AC
0x00000000
r15r14r13r12r11r10r9r8r7r6r5r4r3r2r1r0
ALU47702000188B22012100
pclrsp
0x00000000
0xFFFFFFFF
Registers Memory
AddressData
CPU
0x080001B40x080001B20x080001B00x080001AE0x080001AC
23
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FetchNextInstruction:pc=pc+2Decode&Execute:2201=MOVSr2,#0x01
0x080001AE
0x00000001
0x00000000
r15r14r13r12r11r10r9r8r7r6r5r4r3r2r1r0
ALU47702000188B22012100
pclrsp
0x00000000
0xFFFFFFFF
Registers Memory
AddressData
CPU
0x080001B40x080001B20x080001B00x080001AE0x080001AC
24
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FetchNextInstruction:pc=pc+2Decode&Execute:188B=ADDSr3,r1,r2
0x080001B0
0x00000001
0x00000001
0x00000000
r15r14r13r12r11r10r9r8r7r6r5r4r3r2r1r0
ALU47702000188B22012100
pclrsp
0x00000000
0xFFFFFFFF
Registers Memory
AddressData
CPU
0x080001B40x080001B20x080001B00x080001AE0x080001AC
25
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FetchNextInstruction:pc=pc+2Decode&Execute:2000=MOVSr0,#0x00
0x080001B2
0x00000001
0x00000000
0x00000000
r15r14r13r12r11r10r9r8r7r6r5r4r3r2r1r0
ALU47702000188B22012100
pclrsp
0x00000000
0xFFFFFFFF
Registers Memory
AddressData
CPU
0x080001B40x080001B20x080001B00x080001AE0x080001AC
26
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ARMApplications….
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iPhone5Teardown
28http://www.ifixit.com
TheA6processoristhefirstAppleSystem-on-Chip(SoC)touseacustomdesign,basedofftheARMv7 instructionset.
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iPhone6Teardown
29http://www.ifixit.com
TheA8processoristhefirst64-bitARMbasedSoC. ItsupportsARMA64,A32,andT32instructionset.
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iPhone7Teardown
30
A10processor:• 64-bitsystemonchip(SoC)• ARMv8-Acore
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AppleWatch
31
• AppleS1Processor• 32-bitARMv7-Acompatible• #ofCores:1• CMOSTechnology:28nm• L1cache 32KBdata• L2cache 256KB• GPU PowerVR SGX543
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KindleHDFire
32http://www.ifixit.com
TexasInstrumentsOMAP4460dual-coreprocessor
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FitbitFlexTeardown
33
STMicroelectronics32L151C6UltraLowPowerARMCortexM3 Microcontroller
NordicSemiconductornRF8001 BluetoothLowEnergyConnectivityIC
www.ifixit.com
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SamsungGalaxyGear
• STMicroelectronicsSTM32F401BARM-CortexM4MCUwith128KBFlash
source:ifixit.com
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PebbleSmartwatch
• STMicroelectronicsSTM32F205REARMCortex-M3MCU,withamaximumspeedof120MHz
source:ifixit.com
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OculusVR
• Facebook’s$2BillionAcquisitionOfOculusin2014• STMicroelectronicsSTM32F072VBARMCortex-M0 32-bitRISCCoreMicrocontroller
source:ifixit.com
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HTCVive
37
STMicroelectronics32F072R8ARMCortex-M0Microcontroller
source:ifixit.com
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NestLearningThermostat
• STMicroelectronicsSTM32L151VBultra-low-power32MHzARMCortex-M3MCU
source:ifixit.com
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SamsungGearFitFitnessTracker
• STMicroelectronicsSTM32F439ZI180MHz,32bitARMCortex-M4CPU
source:ifixit.com
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ALittleAboutSTM32
• STM32 isafamilyof32-bit microcontroller integratedcircuits by STMicroelectronics
• TheSTM32chipsaregroupedintorelatedseriesthatarebasedaroundthesame 32-bit ARM processorcore,suchasthe Cortex-M7F, Cortex-M4F, Cortex-M3, Cortex-M0+,or Cortex-M0.
• Internally,eachmicrocontrollerconsistsoftheprocessorcore, staticRAM memory, flash memory,debugginginterface,andvariousperipherals.
https://en.wikipedia.org/wiki/STM32
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STM32NucleoFamily
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OtherARMChips