Chapter 7 -- Modular Sequential Logic

Serial-in, Serial-out Shift Register

S e r ia l in S e r ia l o u t

C e ll n x n

M S

S h iftc o n tr o l

p u lse

S h ift

(b )

(a )

C K

C e ll i x i

M S

C e ll i -1 x i-1

M S

C e ll 1 x 1

M S

S

R

Q

Q

C K

S

R

Q

Q

C K

S

R

Q

Q

S e r ia l o u tS e r ia l in

Generic Shift RegisterP a r a lle l in (Y )

P a r a lle l o u t (X )

S e r ia l o u tS e r ia l in

P r e se t c o n tr o l

S h ift p u lse

C le a r c o n tr o l

(a )

n -B it sh iftr e g is te r

P a r a lle l in (Y )

S e r ia l o u t

P r e se t c o n tr o l

S h ift p u lse

C le a r c o n tr o l

(b )

n -B it sh iftr e g is te r

P a r a lle l o u t (X )

S e r ia l in

S h ift p u lse

C le a r c o n tr o l

(c )

n -B it sh iftr e g is te r

SN74164 Serial-in, Serial-out Shift Register

C lo c k

R

(8 )

(1 )

(2 )Q A

S

(a )

C K

Q A

C le a r

S e r ia lin p u ts

(3 ) (4 ) (5 ) (6 ) (1 0 ) (11 ) (1 3 )O u tp u t

Q A

O u tp u tQ B

O u tp u tQ C

O u tp u tQ D

O u tp u tQ E

O u tp u tQ F

O u tp u tQ G

O u tp u tQ H

(S e r ia l o u tp u t)

AB

(9 )

C le a rR Q B

S

C K

Q B

C le a rR Q C

S

C K

Q C

C le a rR Q D

S

C K

Q D

C le a rR Q E

S

C K

Q E

C le a rR Q F

S

C K

Q F

C le a rR Q G

S

C K

Q G

C le a rR Q H

S

C K

Q H

C le a r

(1 2 )

C le a rAB

S e r ia lin p u ts

O u tp u ts

C lo c kQ A

Q B

Q C

Q D

Q E

Q F

Q G

C le a rC le a r(b )

SN74164 Function Table and Package

(c )

A

Q C

V C C

Q H

Q G

Q F

Q E

B

Q A

Q B

Q D

G N D

(d )

1

2

3

4

5

6

7

1 4

1 3

1 2

11

1 0

9

8

A B

In p u ts O u tp u ts

LHHHH

´L

´´

HL´

´´

H´L

LQ B 0

Q A n

Q A n

Q A n

LQ A 0

HLL

LQ H 0

Q G n

Q G n

Q G n

Q A 0 , Q B 0 , Q H 0 = le v e ls o f Q A , Q B , Q H , r e sp e c tiv e ly ,b e fo r e th e in d ic a te d s te a d y -sta te in p u t c o n d itio n s a r e e s ta b lish e d .Q A n , Q G n = le v e ls o f Q A , Q G , r e sp e c tiv e ly , b e fo r e th e m o str e c e n t tr a n s itio n o f th e c lo c k (1 -b it sh ift)

C lo c k

C le a r

C lo c kC le a r Q A Q B Q HÉ

SN74165 8-bit Serial-In, Serial-out Shift register

In p u ts In te r n a lo u tp u ts

O u tp u tP a r a lle l

C lo c k S e r ia lC lo c kin h ib it

LHHHH

´LLLH

´L ´

´´

HL´

a ...h´´´´

A ...H

aQ A 0

HL

Q A 0

bQ B 0

Q A n

Q A nQ B 0

hQ H 0

Q G n

Q G n

Q H 0

Q HQ BQ A

S h ift/lo a d

(a )

A

P a r a lle l in p u ts

S h ift/L o a d

C lo c k in h ib itC lo c k

(1 0 )S e r ia l

(1 1 )

S

(1 )

(2 )

R

C K

D

B(1 2 )

S

R

C K

D

C(1 3 )

S

R

C K

D

D(1 4 )

S

R

C K

D

E(3 )

S

R

C K

D

F(4 )

S

R

C K

D

G(5 )

S

R

C K

D

H(6 )

S

R

C K

D

(1 5 )

Q H

Q H

(9 )

(7 )

A

S h ift/L o a d

C lo c k in h ib itC lo c k

(1 0 )S e r ia l

(1 1 )

S

(1 )

(2 )

R

C K

D

(1 5 )

(b )

(c )

SN74165 Timing Diagram

C lo ck

C lo ck in h ib it

S e ria l in p u t

S h ift/lo ad

D a ta

H

L

H

L

H

L

H

H

H

L

L o adIn h ib it

(d )

O u tp u t Q H

O u tp u t Q H

A

B

C

D

E

F

G

H

S eria l sh ift

H H

L L L

H H

L LH H

L L L

H

Parallel Accumulator

F A

C L R

D

C K

Q

...

...

...

F A

C L R

D

C K

Q

H A

C L R

D

C K

Q

(b )

x n x 2 x 1

z1z2zn

C lea rA ccu m u la te

zn+ 1

Synchronous Binary Counter

C L R

J

C K

Q

Q

C K

KC L R

J

C K

Q

KQC L R

J

C K

Q

KQC L R

J

C K

Q

KQ

...

...

...

O v erflo w

X n X 1X 2X 3

C lea r

C o u n t

In h ib it(a )

(b )

00000

00001

00110

01010

11001

11000

11000

1

01010

X n X 1X 2X 3

R ecy c le s

SN74163 Synchronous Binary Counter

S y n ch ro n o u s c lea rS y n ch ro n o u s lo ad

C o u n tH o ldH o ld

L o ad

D a ta A

D a ta B

D a ta C

D a ta D

(a )

(b )

(9 )

(3 )

(4 )

(2 )

(5 )

(6 )

(1 )

(7 )

C lo ck

E N P

E N T

In p u ts

M o d e

(1 0 )

Q AJ

K

LHHHH

´LHHH

´´

HL

´´

HL

Q

C K

(1 4 )

Q BJ

K

Q

C K

(1 3 )

Q CJ

K

Q

C K

(1 2 )

R C O

J

K

Q

C K

(1 5 )

Q D(11 )

C lea r

L o ad E N PE N TC lea r

SN74163 Timing Diagram

(c )

C lea r

L o ad

O u tp u ts

A

B

C

D

C lo ck

E N P

E N T

R C O

Q A

Q B

Q C

Q D

S y n cc lea r

S y n clo ad

D a tain p u ts

1 2 1 3 1 4 1 5 0 1 2

C o u n t In h ib it

Asynchronous Down Counter

C L R

J

C K

Q

Q

C K

K

C L R

J

C K

Q

KQ

C L R

J

C K

Q

KQ

...

...

...

X n X 1X 2

C le a r

(a )

(b )

1

0

0

0

0

0

1

0

0

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

...

...

. ..

. ..

. ..

. ..

X n X 1X 2X 3. ..

C lo c k

C o u n t

0

1

1

1

1

1

0

1

1

1

1

0

0

1

1

0

0

1

0

1

0

1

0

1

...

...

. ..

. ..

. ..

. ..

X n X 1X 2X 3. ..

U p c o u n t m o d e D o w n c o u n t m o d e

Synchronous Up/Down Counter

C L R

J

C K

Q

Q

C K

K

...

X n

U po v erflo w

D o w no v erflo w

C L R

J

C K

Q

Q

C K

K

X 2

...

...

...

...

...

C L R

J

C K

Q

Q

C K

K

X 1

U p /d o w n

C lo ck

C lea r

1

SN74160 Synchronous Decade Counter

M 1

C lea r

D

V C C

Q A

Q B

Q C

Q D

L o ad

E N T

A

B

E N P

G N D

(a )

1

2

3

4

5

6

7

8

1 6

1 5

1 4

1 3

1 2

11

1 0

9

(1 )

(9 )

(1 0 )

(7 )

(2 )

(3 )

(4 )

(5 )

(6 )

(b )

(1 4 )

(1 3 )

(1 2 )

(11 )

(1 )

(2 )

(4 )

(8 )

(1 5 )C lo ck

C

R C O

C lea r

D

A

B

E N P

L o ad

C

C lo ck

E N T

Q A

Q B

Q C

Q D

R C O3 C T = 9M 2

C T = 0

G 4

G 5 /2 ,3 ,4 +

G 3

C T R D IV 1 0'1 6 0

1 ,5 D

SN74160 Logic DiagramL o ad

D a ta A

D a ta B

D a ta C

D a ta D

(c )

(9 )

(3 )

(4 )

(2 )

(5 )

(6 )

(1 )

(7 )

C lo ck

E N P

E N T(1 0 )

Q AJ

K

Q

C K

(1 4 )

Q BJ

K

Q

C K

(1 3 )

Q CJ

K

Q

C K

(1 2 )

R C O

J

K

Q

C K

(1 5 )

Q D(11 )

C lea r

C L R

C L R

C L R

C L R Q

SN74160 Timing Diagram

(d )

C lea r

L o ad

O u tp u ts

A

B

C

DC lo ck

E N P

E N T

R C O

Q A

Q B

Q C

Q D

A sy n cc lea r

S y n clo ad

D a tain p u ts

7 8 9 0 1 2 3

C o u n t In h ib it

Asynchronous BCD Counter

J

C K

Q

Q

X 3

C K

KR

J

C K

Q

KQ

J

C K

Q

KQ

X 0X 2

C le a r

C lo c k

C o u n t

(a )

J

C K

Q

KQ

X 1

S

R

S

R

S

R

S

1

0

9

1 0

8

0

8

0

46

76

4

5

4

2

3

0

2

(b )

Digital Timer Block DiagramM in u te s S e c o n d s

C le a r

1 P u lse /h o u r 1 P u lse /m in u te

1 P u lse /se c o n d

P o w e r lin e

S ta r t/S to p

¸ 6 ¸ 1 0 ¸ 6 ¸ 1 0

¸ 5 ¸ 1 2

P u lseg e n e r a to r

Figure 7.22

SN7492A Asynchronous CounterC lo c k B

V C C

C lo c k A

Q A

Q B

G N D

Q D

Q C

N C

R O (1 )

R O (2 )

(a )

1

2

3

4

5

6

7

1 4

1 3

1 2

11

1 0

9

8

N C

N C

N C

C T = 0

&(6 )

(7 )

(b )

11

(9 )

D IV 3

(1 2 )

R O (1 )

R O (2 )

C lo c k A

Q B

Q C

Q A

C T R'9 2

D IV 2(1 4 )

0

1 Z 4

+

C T

Q AJ

K

Q

C K

(1 2 )

Q BJ

K

Q

C K

(11 )

Q CJ

K

Q

C K

(9 )

J

K

Q

C K

Q D(8 )

(6 )

(7 )

C lo c k A

C lo c k B

(1 4 )

(1 )

(a )

R 0 (1 )

R 0 (2 )

(8 )Q D

D IV 24 +

C lo c k B(1 )

+

Q

SN7492A Timing Diagram

(d )

C lo c k B

R 0 (1 ) = R 0 (2 )

Q B

Q C

J B = Q C

K B

J C = Q B

K C

0 1 0 0

0 0 1 0

1 1 0 1

1 1 1 1

0 1 0 0

1 1 1 1

SN7492A State Diagrams1

0

1 3

8

1 20

1 2

1 0

89 8

0

5

4

2

32

(e )

4

1 1

1 0

1

1 3

8

1 20

1 2

8

9 80

6

5

2

4

0

(f)

41 0

1 4

Modulo-N Asynchronous Counter

J

C K

Q

Q

X n - 1

C K

KR

J

C K

Q

KQ

X 0

C le a rc o n tr o l

C o u n tp u lse

C o u n tc o n tr o l

J

C K

Q

KQ

X 1

S

R

S

R

S

S ta te d e te c tio nlo g ic

SN74293 Asynchronous Binary Counter

Q AJ

K

Q A

C K

(9 )

Q BJ

K

Q B

C K

(5 )

Q CJ

K

Q C

C K

(4 )

J

K

Q D

C K

Q D(8 )

(1 2 )

(1 3 )

In p u t A

In p u t B

(1 0 )

(11 )

(a ) (b )

08

R 0 (1 )

R 0 (2 )

1 2

3

1 5

1 4

1 3

4

5

1 2

11

1 0

9 8

6

7

1 2

1 4

0

2

0

4

6

4

0

8

1 2

8

1 0

Modulo-13 Counter Design -- Example 7.1

1

1 1

1 3

8

0

1 0

8

68

0

7

5

2

4

0

(b )

6

9

1 0

0

4

4

1 2

32

(a )

7 4 2 9 3

7 4 3 2 /4

7 4 1 1 /3

Q A

Q B

Q C

Q D

In p u t A

In p u t B

R 0 (1 )

R 0 (2 )

C lo c k

C le a r