chapter 6 – msp430 micro-architecture
DESCRIPTION
Chapter 6 – MSP430 Micro-Architecture. Concepts to Learn…. Computer Architecture MSP430 Micro-Architecture Instruction Cycle Review Fetch Cycle Addressing Modes Operand Fetch Cycles Execute Cycle Store Cycle Instruction Clock Cycles Digital I/O. Levels of Transformation. Problems. - PowerPoint PPT PresentationTRANSCRIPT
Chapter 6 – MSP430Micro-Architecture
BYU CS/ECEn 124 Chapter 6 - MSP430 Micro-Architecture 2
Concepts to Learn…
Computer Architecture MSP430 Micro-Architecture Instruction Cycle Review Fetch Cycle Addressing Modes Operand Fetch Cycles Execute Cycle Store Cycle Instruction Clock Cycles Digital I/O
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Levels of Transformation
Problems
Algorithms
Language (Program)
Machine (ISA) Architecture
Microarchitecture
Circuits
Devices
Programmable
Computer Specific
Manufacturer Specific
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Computer Architecture
Like a building architect, whose place at the engineering/arts and goals/means interfaces is seen in this diagram, a computer architect
reconciles many conflicting or competing demands.
Architect Interface
Interface
Goals
Means
Arts Engineering
Client’s taste: mood, style, . . .
Client’s requirements: function, cost, . . .
The world of arts: aesthetics, trends, . . .
Construction technology: material, codes, . . .
Computer Architecture
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MSP430 Modular ArchitectureMSP430 Micro-Architecture
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Memory OrganizationMSP430 Micro-Architecture
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Micro-Architecture SimulatorMemory Address Register
Arithmetic Logic Unit
Program CounterAddress Bus
Data BusCondition Codes Memory
Port 1 Output
Instruction Register
Source Operand
Destination Operand
MSP430 Micro-Architecture
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Quiz…
Disassemble the following MSP430 instructions:Address Data0x8010: 40310x8012: 06000x8014: 40B20x8016: 5A1E0x8018: 01200x801a: 430E0x801c: 535E0x801e: F07E0x8020: 000F0x8022: 12300x8024: 000E0x8026: 83910x8028: 00000x802a: 23FD0x802c: 413F0x802e: 3FF6
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Quiz…
Disassemble the following MSP430 instructions:Address Data0x8010: 40310x8012: 06000x8014: 40B20x8016: 5A1E0x8018: 01200x801a: 430E0x801c: 535E0x801e: F07E0x8020: 000F0x8022: 12300x8024: 000E0x8026: 83910x8028: 00000x802a: 23FD0x802c: 413F0x802e: 3FF6
mov.w #0x0600,r1
mov.w #0x5a1e,&0x0120
mov.w #0,r14add.b #1,r14and.b #0x0f,r14
push #0x000e
sub.w #0,0(r1)
jne 0x8026mov.w @r1+,r15jmp 0x801c
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The Instruction Cycle
INSTRUCTION FETCH Obtain the next instruction from memory
DECODE Examine the instruction, and determine how to execute it
SOURCE OPERAND FETCH Load source operand
DESTINATION OPERAND FETCH Load destination operand
EXECUTE Carry out the execution of the instruction
STORE RESULT Store the result in the designated destination
Not all instructions require all six phases
Instruction Cycle
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Fetching an Instruction
PC
Fetch Cycle
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Addressing ModesAddressing Modes
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Source Addressing Modes
The MSP430 has four basic modes for the source address: Rs - Register x(Rs) - Indexed Register @Rs - Register Indirect @Rs+ - Indirect Auto-increment
In combination with registers R0-R3, three additional source addressing modes are available: label - PC Relative, x(PC) &label – Absolute, x(SR) #n – Immediate, @PC+
Addressing Modes
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MSP430 Source Constants
To improve code efficiency, the MSP430 "hardwires" six register/addressing mode combinations to commonly used source values: #0 - R3 in register mode #1 - R3 in indexed mode #4 - R2 in indirect mode #2 - R3 in indirect mode #8 - R2 in indirect auto-increment mode #-1 - R3 in indirect auto-increment mode
Eliminates the need to use a memory location for the immediate value - commonly reduces code size by 30%.
Addressing Modes
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Destination Addressing Modes
There are two basic modes for the destination address: Rd - Register x(Rd) - Indexed Register
In combination with registers R0/R2, two additional destination addressing modes are available: label - PC Relative, x(PC) &label – Absolute, x(SR)
Addressing Modes
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Register Addressing ModeOperand Fetch Cycles
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Source: Register Mode – Rs
Rs
Operand Fetch Cycles
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Destination: Register Mode – Rd
Rs
Operand Fetch Cycles
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Register-Indexed Addressing ModeOperand Fetch Cycles
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Source: Indexed Mode – x(Rs)
Rs
PC
PC
Operand Fetch Cycles
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Symbolic Addressing ModeOperand Fetch Cycles
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Source: Symbolic Mode – Address
PC
PC
PC
Operand Fetch Cycles
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Absolute Addressing ModeOperand Fetch Cycles
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Source: Absolute Mode – &Address
SR (0)
PC
PC
Operand Fetch Cycles
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Register Indirect Addressing ModeOperand Fetch Cycles
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Source: Indirect Mode – @Rs
Rs
Operand Fetch Cycles
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Register Indirect Auto-incrementOperand Fetch Cycles
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Source: Indirect Auto Mode – @Rs+
Rs
Rs
Operand Fetch Cycles
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Immediate Addressing ModeOperand Fetch Cycles
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Source: Immediate Mode – #n
PC
Operand Fetch Cycles
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Execute Phase: PUSH.W
SP
SP
Execute Cycle
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Execute Phase: Jump
Execute Cycle
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Store Phase: Rd
Store Cycle
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Store Phase: Other…
Store Cycle
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Instruction Timing
Instruction cycles = Power consumption Most instruction cycles limited by access
to memory (von Neumann bottleneck) In general
1 cycle to fetch instruction +1 cycle for @Rn, @Rn+, or immediate +2 cycles for indexed, absolute, or symbolic +1 to write destination back to memory 2 cycles for any jump No difference between byte and word
Instruction Clock Cycles
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Digital I/O
Digital I/O grouped in 8 bit memory locations called ports Each I/O port can be:
programmed independently for each bit combined for input, output, and interrupt functionality
Edge-selectable input interrupt capability for all 8 bits of ports P1 and P2
Read/write access using regular MSP430 byte instructions Individually programmable pull-up/pull-down resistors The available digital I/O pins for the hardware
development tools: eZ430-F2013: 10 pins - P1 (8 bits) and P2 (2 bits); eZ430-F2274: 32 pins – P1, P2, P3, and P4
Digital I/O
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8-bit Digital I/O Registers
Direction Register (PxDIR): Bit = 1: the individual port pin is set as an output Bit = 0: the individual port pin is set as an input
Input Register (PxIN): When pins are configured as GPIO, each bit of these read-only
registers reflects the input signal at the corresponding I/O pin Bit = 1: The input is high Bit = 0: The input is low
Output Register (PxOUT): Each bit of these registers reflects the value written to the
corresponding output pin. Bit = 1: The output is high; Bit = 0: The output is low. Note: the PxOUT is a read-write register which means
previously written values can be read, modified, and written back
Digital I/O
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Select Digital I/O Registers
Function Select Registers: (PxSEL) and (PxSEL2):
PxSEL PxSEL2 Pin Function
0 0 Selects general purpose I/O function
0 1 Selects the primary peripheral module function
1 0 Reserved (See device-specific data sheet)
1 1 Selects the secondary peripheral module function
Digital I/O
Port P2.0 Example:
P2SEL.0 ADC10AE0.0 Pin Function
0 0 General-purpose digital I/O pin
1 0 ACLK output
X 1 ADC10, analog input A0 / OA0, analog input I0
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Interrupt Digital I/O Registers
Interrupt Enable (PxIE): Read-write register to enable interrupts on individual pins on ports P1/P2 Bit = 1: The interrupt is enabled Bit = 0: The interrupt is disabled Each PxIE bit enables the interrupt request associated with the
corresponding PxIFG interrupt flag
Interrupt Edge Select Registers (PxIES): Selects the transition on which an interrupt occurs Bit = 1: Interrupt flag is set on a high-to-low transition Bit = 0: Interrupt flag is set on a low-to-high transition
Interrupt Flag Registers (PxIFG) Set automatically when the programmed signal transition (edge) occurs PxIFG flag can be set and must be reset by software Bit = 0: No interrupt is pending Bit = 1: An interrupt is pending
Digital I/O
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Pull-up/down Register
Pull-up/down Resistor Enable Registers (PxREN): Each bit of this register enables or disables the pull-up/pull-down
resistor of the corresponding I/O pin Bit = 1: Pull-up/pull-down resistor enabled Bit = 0: Pull-up/pull-down resistor disabled. When pull-up/pull-down resistor is enabled, Output Register
(PxOUT) selects: Bit = 1: The pin is pulled up Bit = 0: The pin is pulled down.
Digital I/O
+3.3v
P2.0
P2.1
P2.3
P2.4
P2.2
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Port P1 RegistersDigital I/O
Register NameShort Form Address
Register Type Initial State
Input P1IN 020h Read only −
Output P1OUT 021h Read/write Unchanged
Direction P1DIR 022h Read/write Reset with PUC
Interrupt Flag P1IFG 023h Read/write Reset with PUC
Interrupt Edge Select P1IES 024h Read/write Unchanged
Interrupt Enable P1IE 025h Read/write Reset with PUC
Port Select P1SEL 026h Read/write Reset with PUC
Port Select 2 P1SEL2 041h Read/write Reset with PUC
Resistor Enable P1REN 027h Read/write Reset with PUC
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