chapter 4 circuit-leveldesign -...

Chapter 4

Circuit-level Design

4.1 Introduction

This chapter focuses on the circuit level design of the basic bnilding blocks in the

siglIl;Hldta (EL,) modulator. It explores the design considerations in selecting

the key blocks like operational transconductance amplifiers (UTA), bias networks.

common-mode feedback circuit. switches, capacitors, comparators and two-phase

clock generation circuitry. The modulator has been designed and simulated in a

TSMC O.18um Cl\IOS process at 1.8V supply voltage using SPICE.

4.2 Sampled-Data vs. Continuous-Time

Sigma-delta modulators can be implemented either as a sampled-data system

or in t.hc cour inuous-t imc domain. Thc main diffcrcnce is that s.unplcd-rluta

sigma-delta systems employ switched-capacitor integrators while continuous-time

systems usc active RC integrators in the modulators as in Figure 4.1. There are

a number of advantages and disadvantages associated with each option which arc

discussed here.

The need for on-chip resistors (51), (1) (87) with very high linearity makes

continuous-time integrators less attractive when compared to switched capacitor

integrators which use capacitor ratios which arc well-controlled. It also helps to

minimize the thermal noise associated with these resistors which occupies a large

66

4.2 Sampled-Data vs. Continuous-Time

area and makes almost impractical to realize on-chip. The frequency response of

switched-capacitor integrators can be more accurately predicted because the time

constant is a function of capacitor ratios (C.,/C i ) and of the sampling frequency.

The time constant of continuous-time integrators, on the other hand is a product

of tho resistor and t.hc capacitor, and suffers severely froin pr()('(~ss variat.ious.

C

Cs

3---,j~F2Vin I I I I

~f r(a)

t

)-L--<:VOUI

Vin R

+

(b)

Voul

Figure 4.1: (a) Switched-capacitor integrator (b) Continuous-time integrator

Auot.hor C\dvallla~e of switched capacitur L;D systems is that they are less

sensitive to clock jitter since most of the charge transfer takes place during the

first half clock period rather than being spread uniformly over t.hc entire clock

period as in continuous-time integrators. As long as the op-amp settles t.o the

required accuracy. it doe; not matt.er whether the op-amp slews or linearly settles.

Continuous- time integrators must be linear at. all times.

Continuous-time integrators also have their advantages. Since the amplifier

set.tling requirenieuts are generally more relaxed than in switched-capacitor cir

cuits. a very high ovcrsampling ratio is uchievablc. The oversampling ratio in

switched-capacitor int.egrators is limit.ed by t.he achievable bandwidth of t.he op

amps. This uiakc» «outiuuous-t.imc ED modulators very appealing for high-speed

applications. 13ecallse of t.hc above incnt.iouc-d uupl.uncutat.iou dillicultios. the

continuous-time approach were not. adopt.ed in this work.

67

4.3 Switched-Capacitor Integrator

Vout

+

Ci

OTAVcmi

F

+'"F2

---1Ci

Fl

~

F2d2/L l F2dl

Vdac- Vdact

~-----'---1

1Yin

1


The integrator is implemented in a fully dilkrellti,d ronJigmatioll as show» ill

Figure 4.2 and employs a two-phase non-overlapping clock as shown in Figure 4.3.

The input is sampled during phase 1 (F 1 and F 1d ) . During phase 2, the charge

is transferred from the sampling capacitor (C.,) to the integrating capacitor (Ci ) .

At the same time, depending on the output value. the appropriate DAC reference

level is applied by closing either switches labelled F 2dl or F2d2 , thus performing

the subtraction operation and the results are being accumulated in the integrat.ion

capacitors.

The integrator employs the bot.tour-plate sampling technique to numnuzo

signal-dependent charge-injection and clock-feed through. This is achieved through

delayed clocks: F 1d , F2d 1 and F2d2 . \Vhen switches labeled F 1 me first. turned off,

the charge injection from those switches remains, to a first order, independent

of the input sigu.il, B(;CHllSC OlW of plates is now Hoatillg, turning off swinhos

labelled F ld shortly after does not introduce charge-injection errors. Further the

switches F1d , F 2d1 and F2d2 are implement.ed as C:YIOS transmission gates in or-

68


Table 4.1: Switches and capacitors in the integrator

Switch/ Size

capacitor

FI N: 10/0.18 urn

P: 10/0.18 urn

F2 N: 10/0.18 urn

P: lO/0.18 mil

FId N: lO/0.18 mn

P: 40/0.18 urn

F2d1 . N: 10/0.18 mil

P: 40/0.18 mil

C, 2 pF

o, 4 pF

der to ensure a small variation ill 011- rosist.auco across the full input siguul range.

This also serves to reduce signal-dependent charge injection from the switches to

C, and C, t.o a negligible level. Table 4.1 shows the switches and capacitors sizes

used in the integrators.

/ /

-~/Figure 4.3: Two-phase non-overlap dock

4.3.1 Operational Trans-conductance Amplifier (OTA)

The basic building block in a switched-capacitor int.egrator is OTA. Figure 4.4

shows the schcmat.ic: of a fully differcntial folded-uLScode OTA used in the in

t.egrators. OIl" of tho uiajor driving forces hdIind t.li« usc of fully difforcntial

opamps is to help reject noise from the substrate as well as from pass-transistor

69


vdd

IFigur« /IA: Fullv-di.lorcnti.rl fold,'d-mscod,' OTJ\

switrho-. turning oil ill switchcd-cava,citol' applicatious. Sinro llJ(\ DC 1 gaIll re

quirement is not so demanding, this is a good selection because of its high opera

tion speed/power consumption ratio. The output common-moele voltage was also

stabilized using a dynamic switched-capacitor common-mode feedback (C:\IFB)

circuit (64) whose linearity is good enough for this application and does not re

quire extra power consumption. Thc schematic also includes the biasing stage

formed by transistors :\h to !vI4.

Trunsistors M, and :\h forms 1,11<' ]l-1.vl)(1 input difh'J'('lIti,d lHur taking into

account the noise constraints, ;VI:; acts as a current source, !vI ll and ;\112 act as

active load for the input stage. anel their gate voltages are controlled by the

common-mode feedback circuit: ]\19 and !VI l O are cascodo transistors which have

opposite type as the input transistors. 11'1 4 • '.1,,, J\h. !vis are current mirrors acting

as active load. The main advantages of using folded-cascade are high ell' gain even

with a single-stage OTA, ease of biasing with a supply voltage as low as 1.8V

when compared with normal tclcscope-cascoded OTAs. simple structure where

frequency compensation is realized by the load capacitance. Also the common

mode control is easier and more accurate. since there is only one stage. Table 4.2

shows the transistor sizes of folded-cascade OTA.

70


r -

Transistor Size (urn)

Ml, M2 720/0.48

M3 432/0.48

1'vJ4, M5, 1'vJ7, M8 216/0.48

1'vJ9. 1'vJ 10 144/0.48

1'vJ1l, M12 72/0.48

Table 4.2' Transistor sizes of folded cascade OTA

4.3.2 Common-mode Feedback

Common-mode feedback is required in Iully-dilfcrontial .unplifior-. to dofiu« t.ho

voltages at the high-impedance output nodes. The amplifier employs dynamic or

switched-capacitor common-mode feedback as shown in Figure 4.5. Capacltors

labelled C, generate the average of t.he output voltages. which is used to create

control voltages for the opamp current sources. The de volt.ag,e across C, is de

terrnined by capacitors C,. which are switched between bias voltages and desired

counuou-un«k- voltage. Thr- bin,s voltag('s an' d(;sigllCd t.o \)(' ('qual to t 1H: differ

ence between the desired common-mode volt.age and the desired control volt.age

used for the opamp current. sources.

The capacitors being switched, C,. might. be between one-quarter and one

tenth the sizes of the non-switched capacitors. C,. Using larger capacitance val

ues overloads the opamp more than is necessary during the phase ()2' and their

size is not. critical to circuit performance. Reducing the capacit.ors t.oo much

causes ('()IIlUlOll-11H)(lc ollsot voltages dur to charge iujor.t.ion of t.ho swii.chos. Nor

mally, all of the switches would be realized by minimum-size n-rhanncl transistors

(O.22um/O.18um) only. except. for t.he switches connect.ed t.o t.he outputs, which

might. be realized by transmission gat.es t.o accommodat.e a wider signal swing. In

applications where the opamp is being used to realize switclied-capacitor circuits.

switched-capacitor CJvIFB circuits arc generally preferred over their continuous

time counterparts since t.hey allow a larger output signal swing. Table 4.3 shows

the capacitor sizes used in the swil.cheri-capacitor common-mode feedback

71


Vout+ Vout-

cmfb

Figure 4.5: A switched-capacitor common-mode feedback

Table 4.3: Capacit.or sizes in t.he switched-capacitor C:\JFB

Capacitor Size

C8 20f

C, 100f

4.3.3 Bias

Figure 4.6 shows the biasing scheme for the OTA which incorporates a wide

swing cascode current. mirror without. restrict.ing t.he signal swings much. The

n-chunncl wide-swing cascade current mirror consists of transistors QI-Q4: along

with t.he diode-connected biasing transistor Qs. The pair Q3. Q4 act.s similarly t.o

a diode-connect.ed transistor at. tho input side of the mirror. The out.put current

comes from Q,. The gate voltages of cascode transistors Ql and Q" an: derived

by the diode-connected transistor Qs. The current for this biasing transistor is

act.uully derived from the bias loop via Ql0 and Qu.

Similarly, t.he p-channel wide-swing cascade current mirror is realized by Q6

Qa. Transistors Qs and Q9 operate as a diode-connected transistor at the input

side of t.he mirror. The current-mirror output. current is t.he drain current. of

Q6' The cascade transistors Q6 and Qo have gate voltages derived from diode

connected Q14, which has a bias current derived from the bias loop via Q12 and

72


08

.-__--oBP1

BP2

017

-=--++-,--__-+-__-+1--=013

05 -yI" :" BN'

L- ~ OBN1

01

Figure 4.6: Wide owing constant transconductance bias circuit.

Table 4 4' Transistor sizes in the bias circuitryC • . " A

Transistor Size Transistor Size Trasistor Size

(um ) (urn) (urn)

Q1, Q2 1D/D.48, 3D/0.36 Q8, Q9 30/0.36, 30/D.48 Q15 10/0.36

Q3, Q4 1O/D36. 10/0.48 Q6, Q7 30/0.48, 30/0.36 Q16 10/0.36

Q5 1.5/0.48 Q14 5/0.48 Q17 10/0.36

Q12, Q13 1O/D.36. 10/0.48 Q10, Q11 3D/D.48, 30/0.36 Q18 20/2

Ql:1. Table 4.4 shows the transistor sizes used in the bias circuitry.

The bias loop does have the problem that at. start-up it is possible for the

current to be zero in all transistors, and the circuit will remain in this stable

state forever. To ensure this condition does not happen, it is necessary to include

start-up circuitry that aneds only the bias-loop in t.ho case that all currnnt.s in

the loop are zero. Here the start-up circuitry consists of transistors Q15, Q16, Q17

and Q18. In the event that all currents in the bias loop are zero, Q17 will be: ofI'.

Since Q18 operates as a high-impedance load that is always on, the gates of Q15

and Q16 will be pulled high. These transistors then will inject currents into the

73

,t.a Switched-Capaclt or Int .egrut or

bias loop which will sta rt up the circuit. Once th e loop sta rts III'. Q17 will come

on. sinking all of the curren t from Q llol . pull ing the gates of Q uo; an d Q 16 low. and

the reby tu rning tln -m off so t hey 110 longer affect the bias loop.

4 .3 .4 Slmulat ion Results of OTA

Table -1 .5 gives the performance summary of OT:\.. Figu re -1 .7 shows the freq uency

respo nse of OTA. Simulat ion res ul ts show that OTA has more than 60 dB gain.

unity gain-bandwidt h (VG D) of -I-l2 :\[Hz and a phase margin of 62 degree. Figure

-l.9 show the transient re-pon-e which shows that the maximum ou tpu t swin g

of a TA is 2\' {different ial]. Figure -l .1O shows the Slew Ra te (S R ) of OT.-\.

whose value is 300\'/ u:,; at loacl capacitance CL=2pF. OTA draws a maximum

current of 2.1 mA dissipating 3.'S m\\' in O.lIS um C:\IOS technology. .-\ second

configura tion i..also considered which is shown in Figu re -I .S [Cascodo OTA circuit

with high output resist ance }. T his OTA design is more stable with increasedload

capacit " TH·e.

.. ~,-------...-... ........_........, .- L

.," ~-------------------+-

· OM ••••_ •••••_ _ _ _ _ _ •••••_ ••

· ,...------------•"•

! • I· ,•.. .- .. -'--." '-. _..- ..- _.-.-.. .._-"'--" -..

_ I .. ).... .......Figure -1 .7: Frequr-ncv res pon-a- of 01'..\.

4 .3 Switched- Capaci to r Integ rato r

""''''•Jf-~ '

~,

Ie.""'''.......

Figure ..1.8: Cascode OT.-\ circuit with high output resistance,

OTA Differential Output Swing

~ - 500ml

- 1.0 f,0.0

>

1.1:1

500m~

0.0

. 1

5.0 u. 1

10ulime ( s )

I

15uI

20u

Figure -1 .9: Tran sient response of OT:\.

rc

4 .3 Switched-Capacito r Integrator

I

/

2.00

1.70

~

> 1.40~

1.10 •

800m492n

--L.498n

time ( s

I

504n)

J

510n

4.3.5

figure ·t 10: Slew rat e of QTA,

P rocess Variation Analysis

Severe uncertaiutv is involved ill nano-scale C).IOS fabri cation which causes vari

at ion in de vice param eters (7). (36), (58), (55). T his leads to variation in dif

Icrent proces s parameters such as chanlid length. ga te-oxide t hickuos s. t hrcshold

vol ta ge. metal win' thickness etc. T I1PSC variation arc ca tr-gorizcd into intr-r-dir

variati on and intra-die [sys tcmatic or random). Xlorcover . tilt' iucreasi ug st a

t ist ical variat ion ill t he pro cess parameter!'; has emerged as a prohleiu ill deep

sub-micron circuit design and cal l cause significant difference ill perform ance of

the fabri ca ted chip compa red to designed , Hence. variability llllal,vsis and mod

eling of t he factors r'outrihuting to the total performance. considering the effects

of random vari ation i ll the process parameters . is important for des igning analog

C),lOS circu its as well. Since c pa mp is the key build ing block in t his design. ill

thi s section. opamp variability is discussed . First. gai n variat ion corresponding

to different loading effect is considered. Figure -l.Ll shows parametric a nalys is

of the ga in a nd ph ase var iat ion corresponding to loml capaci tauo- lfF to lOfF.

As the load capacitance i.... increased the gain slightlv decreased. clue to var ious

second orde r effects.

76

4.5 Circuit Noise

values of sampling and integration capacitors are 2pF. IpF, 0.5pF, 0.2pF and

4pF, 2pF, IpF, 0.4pF respectively.

In addition to sizing the switches for linearity and charge-injection reasons, the

sampling network also needs to b" d"sign"d tor sufficient bandwidth. In('n,asing

the switch sizes decreases the resistance but increases the parasitic capacitance

of the network. An optimum value of the switch size which yields a minimum

R-C time constant can be determined.

4.5 Circuit Noise

There exist mainly two sources of circuit noise (50), (37) which degrades the

porformuncc of wdl-dcsi~l}('d hi~h-r"solut.ion L:6 modulator. They arc thermal

noise (kT/C) and flicker (1/t') noise in the transistors comprising the modulator.

Thermal noise is the result of the random motion of electrons in a conductor. It. is

proportional to absolute temperature. it has a Gaussian amplitude distribution.

and its power spectral density is white.

The source of flicker noise is believed to be due to imperfections in the crystal

lattice at the interface between the oxide and the silicon lavers. The power spec

tral density of flicker noise is approximately inversely proportional to frequency

and is independent of the device biasing conditions. Its amplitude distribution

tends to vary from device to device and may not be Gaussian. The flicker noise

of a ~IOS transistor is inversely proportional to its gate area. So the l/f noise

in an amplifier can be reduced to a great extent simply by increasing the size of

transistors that contribute significantly to the input-referred flicker noise. There

fore the total power spectral density of the equivalent input-referred noise can

be found by adding the two independent noise sources and is given by equation

4.5 where k is Boltzmanns constant, T is the absolute temperature, '/ is a bias

and technology dependent factor, gm is the transconductance of the device, Kf

is an experimentally determined constant that is bias independent but highly

technology dependent, and long-channel transistor behaviour is assumed.

-;? 1 f{~ = 4kT'Y~ + _ f/';} 9m W LCox !

80

(4.5)

4.6 Sampling and Integrating Capacitors

Vdd

1

ICs

Vout

ModelofMOStransistor used as a

switchr---------.I Rs II III

: I

L~-~----lICs

Vout

Fig (a) A switched-capacitor samplingnetwork

(b) Circuit model for sampling noise

Figure 4.14: A switched-capacitor sampling network

4.6 Sampling and Integrating Capacitors

The sizes of the sampling and integrating capacitors are governed by the noise

requirements. The ideal input.-referred thermal noise of the integrator is given by

equation 4.6

kTPN i = 4-

C(4.6)

-:,Figure 4.14a represents the switched-capacitor sampling network in the inte

grator of Figure 4.2 when F1 is high. The power of the sampled noise can be

estimated using the circuit in Figure 4.14b, where the i\lOS switch is modelled

as a resistor in series with a noise voltage source. When the sampling switch in

Figure 4.2 is opened. the noise voltage is stored on C,. If the sampling period

is much longer than the time constant formed by R, and C.,. the high frequency

components of the noise are aliased into the frequency bane! from 0 to f,. As a

result, the full power of the sampling noise appears in this bane! with an approxi

mately white spectral density. kTIC, is thus the total power of the input-referred

81

4.7 Incomplete Linear Settling and Slew Rate Limitation

sampling noise introduced during F1 in the integrator. Since the sampling noise

is distributed uniformly across the Nyquist band, if the signal is oversampled by a

factor M the thermal noise power appearing in the base band is given by equation

4.7

- kT'1)2 = __

AI ]vIC,(4.7)

When the charge that was sampled during F I is transferred from C, to C,

during F 2 , additional thermal noise is introduced by the switches. The thermal

noise introduced by the switches in the circuit during F 2 is band limited by the

response of the operational amplifier as well as tho time constant formed by the

on-resistance of tho switches and the sampling capacitor

4.7 Incomplete Linear Settling and Slew Rate

Limitation

The finite bandwidth of operational amplifiers translates into incomplete linear

sett.ling, in the time domain when the amplifiers arc; used in switched-capacitor

integrators. This causes an integrat.or gain error as given in equation 4.8.

(4.8)

where

(1 - E) is the gain error.

n T = -In(2-N ) , (Nnmber· of Time Constants)

C.,C = feedback factor.z

(4.9)

(4.10)

(4.11 )

From equation 4.9, it. is clear t.hat higher the required resolution (N) of the

ADC, the smaller t.he tolerable settling error will be. This means a higher bias

current. is needed in amplifiers.

82

(4.12)

4.8 Integrator Leakage and Amplifier Gain Requirements

If we substitute the unity-gain frequency of the OTA we designed, we can

compute the number of time constants using the equation 4.12.

, - 1 >- 2fi.;.;uT - ~ ':/" snT

442MH, ;:, 2 x 64iVI H z x nT' nr :( 3.45

which gives a resolution of around 5 bits using the equation 4.10.

This shows how important it is to improve the unity gain bandwidth and de

gain of the opamp to have small sett.ling error as the clock frequency increases,

and to get. the required accuracy. There exists a relationship between the slew

rate'S' and settling time constant 'T' such that slewing never occurs and the

settling process is entirely linear and is given by equation 4.12

S = (1 + C, + Cp ) x Vc;s - VT

C, T

where Vc;s is tbe gate-to-oo\11'ce voltage, VT io the thresho.d voltage of the

input transistors. awl Vas:VT is referred to as the transisr.or overdrive voltage.

C, is the sampling capacitance, C, is the integrating capacitance and Cp is the

parasitic capacitance in equation 4.12.

If we compute T by substituting the sn (300 VIus) of 0\11' OTA. and assuming

an overdrive voltage of 0.5 and parasitic capacitance of 1 pF. we get

T = (1 + 2P,~,1/') X ~:~ = 2.92ns, which is the sottliug time constant. Hence

it is clear that it io necessary to employ relatively large overdrive voltages to

simultaneously achieve both a high slew rate and a large settling time constant.

4.8 Integrator Leakage and Amplifier Gain Re

quirements

Integrator leak, (100) which is a consequence of finite amplifier de gain, limits the

extent to which low-frequency qn.uitizatiou noise is shil]Jcd in a L:6 modulator,

thereby increasing the base band noise. The transfer function of a leaky int.egrator

is given by equation 4.13,

(4.13)

83

4.9 Quantizers

where (' is referred to as the leakage factor.

In a switched-capacitor integrator of Figure 4.2 , the integrator leakage factor

is given by equation 4.14,

1 C,f = AD + 1 x c; (04)

where An is the amplifiers open loop gain. An amplifier gain of 63 db (1.5 K)

gives t.ho intcgrur.or leakage factor as O.02'1r· in order to ensure sufficient linoaritv

and parasitic insensitivity in the integrator response.

4.9 Quantizers

The quantizers (2:3) in the cascaded modulator comprises of a single comparat.or

(68) and a l-bit D/A convert.er in the first stage and a multi-bit A/D and D/A

in tho second and third stages (:30). The comparator is irupleuicut.cd as a cascade

of a regenerative latch followed by an SR latch. while the I-bit DAC is a simple

switch )1<'1 work c01l1ll,cl..cd to off~chip n,i'<:rcnc(' vo]tagc's. Enors int rodurr«l bv 1Ill'

DAC in the first stage of t.he modulator arc added to t.he input signal and directly

degrade the performance of t.he modulator. Therefore, this DAC is designed to

settle to t.he resolution of the modulator. However. errors associated wit.h the

other components of the quantizcrs are great.ly attenuated in the base band by

noise shaping. Tlms t.he principle design objective for these circuits is low power

consumption.

4.9.1 Comparators

The regenerative latch (cross-coupled inverters) in Figure 4.15 is made up of l\!:J,M4 , M.s. and :VI". When phi) is low, t.he p-channcls, l\Is and l\h of the latch

are isolated from the n-channels, l\!:J and ;\14 . In addition, the outputs of the

decision circuit are pulled high, that is, t.he outputs of the comparator arc low,

Q = Q = O. When phi) signal transitions high, t.he regenerative action of t.he

lat.ch causes an imbalance in the decision circuit, forcing the outputs int.o a state

determined by V+ and V-. Table 4.6 shows t.he transistor sizes in t.he regenerative

latch. Figure 4.17 shows the time domain response of the comparator. A second

84

4.9 Quantizers

Transistors

Transistor sizes in the regenerative latch

I Size (11m ) ~

:';11 , lYh, lYb, lvl.1 09/0.45

:\In, lvllO 2.25/0.45

lvl5 , lvl6 , :'vh, :\I~ 2.25/0.45

:\J11 , lvl12 , M1.3' lvl14 1.2/0.18

Table 4.6:

~

configuration iii abo considered which is shown in Figure 4.16 (Clamped push-pull

output comparator). The layont design of clamped push-pull output comparator

is simpler compared to Figure 4.15.

vdd

s

phlt o--tt-"c.:...-------I M10

R

s--oR~

Figure 4.15: Regenerative comparator.

The need for pre-amplification stage depends on the comparator sensitivity

and speed. The preamp stage amplifies the input signal to improve the com

parator sensit.ivit.y and isolates the input. of t.he comparat.or from swit.ching noise

coming from t.he positive feedback st.age.

Sigma-delta modulators show little sensitivity to t.he errors induced during the

85

4.10 Clocks

All the comparators are identical that are used in the first and second stage of

the quantizers. Without a pre-amplification stage, a comparator may provide a

resolution not much better than 50mV, which is enough to guarantee the INL

requirements, taking into account the value of the least significant bit (LSB).

However, if the LSB decreases, as would happen if the gain of the ADC had to

be increased, the hysteresis inherent in the latched comparators might become

a problem. In that case, more complex topologies with pre-amplification stages

must be used, with a considerable increase in the power consumption. That is

the reason why it is interesting to keep the ADC gain equal to unity. After the

comparator array, sixteen A?'lD gates gerwrat.e a l-of-16 code which is translated

t.o binary by an encoding logic using an encoder. To implement t.he DAC. the

l-of-If code is used to select. through analog switches the voltages generat.ed

in a resistive ladder. also used t.o generate the reference voltages for the ADC.

The resistances in the ladder an' H/2 = 100 ohm: this value is low enough to

ensure that the settling (,ITO!' of t.he voltages in the ADC input capacitors arc not

excessive. All switches are complerueut.arv with a size of lOum/0.18um for both

Nl'vIOS and P:\IOS transistors. The value of the t.wo sampling capacitance was

chosen to be 500 fF.

4.9.3 Digital-to-Analog Converters

The I-bit D/ A converters are implemented as switch networks that. are cont.rolled

by the comparator outputs. The outputs of the SR latches used in the compara

tors an' hllfr"r"d hv inverters that .Iriv.: t.wo swit ('Ii.,s ('<Jllll.,(·t(,d t o tho positive

and llq~ativ(~ n>f(~rcIJ('(~ voltages which arc g{~lH'rat('(l on chip.

4.10 Clocks

In switched-capacitor circuit two non-overlap clock phases are needed. In order to

reduce the influence of charge injection (also called clock ked through), a delayed

version is needed for each clock phase. A complement version is also needed for

each clock phase when a transmission gate is used, Normally 4-8 clock phases are

needed in a L;,I'; modulator. These clock phases are usually generated on-chip.

89

4.11 Simulation Results

In a normal signal generator the delayed version clock phase has a same delay at

both rising edge and falling edge. However in most modulators only the falling

edge needs to be delayed in order to reduce the signal-dependent charge injection.

The rising edge does not have to be delayed. The advantage of non-delayed rising

edge is that t.he settling time can be increased. which reduces tho requirement

on the OTA driving capability. The rising edges of the delayed clocks should be

lined up with the rising edges of the non-delayed versions to increase the amount

of available settling time for t.he OTA, which is given by tho equation 4.16.

T,T.sdtleavuilablc = :2 - fnol - tf' - tf (416)

where T, is sampling period, t n ol ='lonoverlap Time, t, =Rise Time and

t r =Fall Time. A circuit to realize two-phase non-overlapping clocks is shown

in Figure 4.20. The two basic non-overlap phases F j and F 2 arc generated by

latches. The delayed versions of t.!H,se two phases are genemted by inverters

working as delay-line. The complement. versions of t.hese phases are also gmwrat.,ed

by inverters, but these inverters are large awl cause very short. extra delay. The

special two-input "inverter" guarantees that the delay happens only at falling

edges.

4.11 Simulation Results

The cOllfigur;lb!<- I:6 modulator has been designed in TSI\IC 0.18Uln C;\IOS

technology, operating from 1.8V supply voltage using SPICE. The cirruit-Iovcl

iiuplouu-utatiou of tho 2nd orde-r I:6 modulator with feed forward signal path

used in t.he first stage is shown in Figure 4.21.

Circuit simulation of a 2nd order modulator with a single-hit. quantizer (GS:vI)

of feed-forward t.opology was carried out. after verifying the results of each block

separately. The l-bit D/A converters are implemented as switch networks that

arc cont.rolled by the comparator outputs. The input. signal had amplitude of 0.5

V (p-p) and a frequency of 100 KHz. The sampling frequency was oct to be 64

:vIHz with an oversampling ratio of HiO. The modulator design employs feedback

reference voltages equal to t.he supply voltages since lowering tho feedback levels

90

4.11 Simul ation Resul ts

Modulated output

1.90

>

1.40

900m

400m

- 100m0.00 4.00u

time8.00u

( s )12.0

Figure -1 .23: Modulator response wit h the modulator input an d qu auti zer ou tput

PSD d !he SIgma-Delta Modulator in !he GSM mode0,.-- - _ _ '- - __-...,

-20

- 40

- 80

~o - 100~

- 120

- 140

-'60

-'60

,,' ,,'Frequeocy [Hz]

,,'

Figure -1 .2-1: OutPU Tspectrum ill GS ),I mode

93

4 .11 Simulat ion R esults

- '00

""~e,

-'50

- 200

,,'-250'-- ...,-- - - ....,.--- .....,-- - -,,----J

Figure .1 .25: Output spectrum ill \\-CD~ I A mode

-~

Figure 4.26: Output spect rum in \\-LA:'\" mode

In order to implement the second and third stage- for t ill' \\"CD~I:\ /\Y LA.:'\

mode. a 2-2 cascadedf fourt h-order] and a 2-2-2 cascaded [sixt h-order] modulator

4 .11 Si m ulatio n R esults

with 2·bit and -l-bit quantizers has been simulated respect ively. T he ..t·bit ADC

employs a flash arc hitecture with sampling network in front of t he 16 comparators

for the comparison of the fully differential input and the reference voltages. The

output of the comparators ace given to an A:'\D gate which generates the ther

mometer code which is furt her converted iuto a binary code using an encoder.

T he -l-bit feedback D.\C circuits are implemented using capacitors. T ho sam

pling capacitances are combined wit h sixteen small unit capacitances to realize

t he -l-bit DAC.

FigUTPs -1.24. 4.25 and 4.26 shows t he modulat cr out put spect rum obtui nod

from circuit -level simulatiou for GS~I I \\'CD~IA/ \\ ' LA:'\ modes fOTa O.5V. 0. 1/ l /S

~ lHz input signal at a sampling frequency of 6..t /6-l/ 200 ~ lHz respectivclv. T he

simulation res ults indicates that the proposed a rchitect ure diss ipates llm\\' /

20m\\" I 35m\\' at 1.8V supply and achieves a peak S:\ DR of 82/G8 /54 d ll ill

GS~I / \\'CD~IA/ II"LA;": modes respectively.

(·l :.)

~

" c a " ",-."y.

11 ' 'o~

c" fj n ,, 1 ~" " e ""[.J,, .v. c

"=" "

.,

Figure 4.27: Opamp layout

95

4 .11 Simulat io n Results

, .-.--;•

• • •• .,· • • •· · • ••; • • ·•• , • •• • ••• • ;• • • • •• ;• • , •· •• • • • •..•• ., • • •• •• • • ;• ••·

•· •• ·• " •• •' .• • • • •~_ ,, _ ..,..: __ L : : • •• • • • •

•

.,

•

•

..

...

Figure 4 .2~ ; Two hit flash converter layout

'. '~!1( I'--.~ I I I 1/'

[. - I .n ! I ~l1-',

~ I, I ..JI '-I

I III

"

f,

I,

I "; ,I II,

:,.

\ i Ii/v

I I U I \, ,I'· ,

I I

I0,

1c- u I t--I I II

, ,, , ;.. ," .. .. .. .. 00 ' 00 ' '" ., -Figure -I .2U: Two hit flash converter layout sinmla tiou out put

4.12 Layout Design

Table 4 7· Porfonnauco comparison with other nmlti-stunrlarrl I:6 ADCsParameters Dual-mode ..igma~delta ADC Triple I\lode

(11 ) (29) (53) (20) (95) (103) (33) Proposed

Orop! 3 2 2 2/(2-1) 2-1-1 2 1 1 1 2-2 2-2-2

No. of hit" 1 2.5 6 1/2.3 1/1/1 Ij1.5j:J 2.5/2.5 1 2 -4

F,.; (1\.IHz) 104/184.32 26/46 23/46 39/38.4 138/245/320 51.2/100!lOO 23/4G G4jG4/20UBW (l\lHz) D,2/3.84 0.2/2 0.2/1.92 O.1/U12 0.271/3.84/20 0.2/5/20 0.2/1.5/1.92 0.2/2/20

DR (dB) 86/54 79/50 HI/70 H2/70 103/82/06 94/88/,56 70/,51/.50 H2/t;Hjr:i4

C:\IOS Pm"""" c.as llm) n.1:,lllm 0.1811m O.\J 11m 0.35 um 0,18 '"ll D,IS lllll 0.18 11111

Pow"r (m\V) 11.5/13..'" 2.4/2,Y 30(50 2.4/4.3 5S/82/12il ."0.8/-5/1 J ll/ZOj:J.S

4.12 Layout Design

A number of layout strategies have to be adopted while doing analog and mixed

signal layout. A digital layout is made by interconnecting simple blocks with

less regard to individual transistors. In contrast. the layout of analog circuits

mainly involves optimizing transistor layouts with much less concern for inter

connections. Important design criteria influenced by the layout are accmacy and

noise immunity,

'When analog and digital circuitries are integrated onto the same chip. addi

tional problems arise. The noise generated by the digital circuitry may couple into

the analog circuitry and corrupt the overall analog circuit performance. There

fore. the control of the noisy interaction is vital in mixed circuits. This can be

done by careful circuit design, for example, by achieving good PSRR.

Fignres 4.27 and 4.28 shows the layout of OTA and flash ADC obtained using

the tool called \IICROWIND in 0.18um technology respectively. Sinmlation re

sults indicate that the OTA layout occupies an area of 6.3um x 5.1um consuming

1m\V of power under 1.8 V supply as illustrated in Fignre 4.27. The simulation

output of 2-bit flash converter is shown in Figure 4.29. Further, the 2-bit flash

ADC dissipates 2.5 m\V occupying an area of 13.8um x 15.6um.

4.13 Performance Comparison

Table 4.7 shows the already publixlu-d mult.i-st.uuiard I:6 ADC in terms of

both dual-mode ,uHI triple-mode architcrturos. TI,,: t riplo-urock: ~6 which has

been published in (95) uses 0.35mn technology and consumes considerably large

97

4.14 Chapter Summary

amount of power. Though (33) uses O.18um technology, it achieves less dynamic

range compared to our performance.

4.14 Chapter Summary

This elmpter desnihes tho circuit kvcl d('si";ll olt.lu- basic building blocks in a E6

modulator based on the results obtained from the Matlab" simulations. The de

sign considerations involves selecting the key blocks like operational transconduc

tance amplifiers (OTA). bias networks. common-mode feedback circuit, switches,

capacitors, comparators and two-phase elock geueration circuitry. The modulator

has been designed and simulated in a TSMC O.18um CMOS process at 1.8V sup

ply volta,.;e. Circ-uit situulat ion of a seco]HI-ol"(kr E6 modulator for GSM with

feedforward topology was carried out after vcrifyirn; t.he results of each block

separately. Later it was extended to simulate a fourth-order and sixth-order

modulator for WCDMA uud WLA:'oI respectively.

98

chapter 4 circuit-leveldesign -...

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