Controller Design (to determine controller settings for P, PI or PID controllers) Based on Transient Response Criteria

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Desirable Controller Features1. The closed-loop system must be stable.2. The effects of disturbances are minimized, i.e., good

disturbance rejection.3. Quick and smooth responses to the set-point changes are

guaranteed, i.e., good set-point tracking.4. Off-set is eliminated.5. Excessive controller action is avoided.6. The control system is robust, i.e., it is insensitive to

changes in operating conditions and to inaccuracies in process model and/or measurements.

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Simplified Block Diagram

1

2

1 2

1 1

1 1

1 1

let

1 1

m c v p dsp

c v p m c v p m

m c v p m d mm sp

c v p m c v p m

v p m

d m

csp

c c

K G s G s G s G sY s Y s D s

G s G s G s G s G s G s G s G s

K G s G s G s G s G s G sG s Y s Y s D s

G s G s G s G s G s G s G s G s

G s G s G s G s

G s G s G s

G s G s G sB s Y s D s

G s G s G s G s

Simplified Block Diagram

1

2

v p m

d m

G s G s G s G s

G s G s G s

B(s)P(s)

D(s)

spY s

Example

41

2

1

20 11

11

1

sv p m

d m

c cI

G s G s G s G s es

G s G s G s

G s Ks

D ss

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Example 12.1

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Alternatives for Controller Design

1. Direct synthesis (DS) method

2. Internal model control (IMC) method

3. Controller tuning relations

4. Frequency response techniques

5. Computer simulation

6. On-line tuning after the control system is installed.

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Direct Synthesis

1

Let and

/1

1 1 /

Let

assumed process model

desired closed-loop transfer function

/1

1 /

m c v p

sp c v p m

v p m m m

spCc

sp C sp

sp sp d

sp dc

sp d

K G G GY

Y G G G G

G G G G G K

Y YG GYG

Y G G G Y Y

G G

Y Y

Y Y

Y YG

G Y Y

Direct Synthesis Steps

1. Specify desired closed-loop response (transfer function)

2. Assume process model3. Solve for controller transfer function

Direct Synthesis to Achieve Perfect Control

2

1 2 11 2

Case 1: Desired response is 1

This is impossible since 1- 0

Case 2: , i.e., an offset is allowed1

(1 1

sp d

sp d

c

sp cd

cc

cc

Y

Y

Y

Y

KY

Y K

KG

GKK

G G ss s K

Ex.

2 ) 1

This is not practical!

s

Direct Synthesis to Achieve Finite Settling Time

1 (Note that there is no offset!)

1

111 1 1

11

1

1 1Ex 1: (pure integral controller)

sp cd

cc

c

c

cc

Y

Y s

sG s

sG Gs

G K G sK s

Example

11 1 1 1

11

PI controller: ,

cc

c

cI

c

c

K

KG s

ss

G sG s K s

s

KK

Example

1

211

21 1

1 1

Series PID controller:

; ; 0 ; =

c

c Dc

I

c

G s ssK

KK

1 2

1 2

1 2

1 2

1

1 2

12

1 22

11

Parallel PID controller

;

:

;

c

cc

I D

c K

KK

G s ss

1 2

21 2 1 2

1 1

1 1c

c

KG s

s s

s sG s

K s

Direct Synthesis for Time-Delayed Systems

1;

1

Let

1 1 1

1 1

c

s

sc

sp cd

c

s

c sc

sc

G s G s e

Ye

Y s

eG s

G s s e sG s e

Taylor Series Approximation

211 1

2!

1

11

1 1c

c

s

s

c

s s s

e

e

sG s

sG

sG

Example 1

1 11

PI c

1

, ontroller:

1

s s

c

cc

cc

I

K

KK

G s e e

G s

KG s

ss

sK s

Example 2

1

1 2

1 2

1

1 2

1

2

1 2

2

1 2

1

1

2

2

21 1 1

11

;

Parrallel PID controll

;

e

1 1

r

:

c

c Ic

s

D

s

cc

KG s

sG s e e

s sG s

K s

K

KK

s

ss

Pade Approximation

1 / 2

1 / 2

11 / 2

11 / 2

1 / 21

1 / 2 1 1 / 2

1 / 21

1 / 2 1 1 / 2

s

c

c

c

c

s

s

s

s

eG s

sGs

s

e s

s s sG

s s sG

e

s

Example

1 / 2

1 / 2 1 1 / 2

111

1

11 Series PID controller: 1

1

,

1

,

1

/ 2

,2

2

c

cD

D

c

c

I

Ic

s s

cc

c

c

D

G s e e

sG s

s s s

s

s s

sG s

s

KG s

s

s

K

K

sK

KK

c

c

Use the DS design method to calculate PID controller settings for the process:

2

10 1 5 1

seG

s s

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Example 12.1

Consider three values of the desired closed-loop time constant: . Evaluate the controllers for unit step changes in both the set point and the disturbance, assuming that Gd = G. Repeat the evaluation for two cases:

1, 3, and 10c

a. The process model is perfect ( = G).

b. The model gain is = 0.9, instead of the actual value, K = 2. Thus,

G

K

0.9

10 1 5 1

seG

s s

The controller settings for this example are:

3.75 1.88 0.682

8.33 4.17 1.51

15 15 15

3.33 3.33 3.33

τ 1c τ 3c 10c

2cK K

0.9cK K

τIτD

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Figure 12.3 Simulation results for Example 12.1 (a): correct model gain.

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Simulation results for Example 21.1(b): incorrect model gain.

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PID vs. IMC

*

*

* *

* *

*

*

* *

* *

1

1 1

1

1 1

1

1

PID:

IMC:

1

11

1

1

csp

c c

c csp

c c c c

c

c

c c

c

c

c

p

c

c

s

G GY Y D

G G G G

G G G GY Y D

G G G G G

G

G G

G G

G G G G

G

G

G

Y Y D

G

G

G

G G

PID Controller Design Procedure Based on IMC Method –Step 1:

factor process model

0

where

time delays, positive zeros

/

Note that

| 1 steady-state gains

G G G

G g

G G G

G

PID Controller Design Procedure Based on IMC Method –Step 2: derive IMC transfer function

* 1

where

1 a low-pass filter with a steady-state gain of one

1

the desired closed-loop time constant

a positive integer (usually 1)

c

r

c

c

G fG

fs

r

PID Controller Design Procedure Based on IMC Method –Step 3:

derive PID transfer function

*

*1c

cc

GG

G G

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Example

*

11/1 Pade approximation

12

112

11 ;

2 112

1 12

s

c

KG s e

s

sKG s

s s

KG s s G s

s s

s sG s f

K

*

I D

*

1

1

11

1

Select

1 12

11 1 1

2 2

1 2

2

1 2 ;

111

2

1

22

2

1

;

1

2

1

2

cc

c

c

c

c

c

c

c

s s

KG

GG G

s s sK

fs

s

K s ss

K

sK

K

s

Controller Synthesis Criteria in Time Domain

Time-domain techniques can be classified into two groups:

(a) Criteria based on a few points in the response

(b) Criteria based on the entire response, or integral criteria

Approach (a)

Based on settling time, % overshoot, rise time, decay ratio (Fig. 5.10 can be viewed as closed-loop response).

Several methods based on 1/4 decay ratio have been proposed, e.g., Cohen-Coon and Ziegler-Nichols.

2

2

2 1Decay Ratio exp

41

1Overshoot exp

21

0.2

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Comparison of Ziegler-Nichols and Cohen-Coon Equations for Controller Tuning (1940’s, 50’s)

Controller Ziegler-Nichols Cohen-Coon

Proportional CKK 31

CKK

Proportional +

Integral

33.3

9.0

I

CKK

2.20.1

33.033.3

083.09.0

I

CKK

Proportional +

Integral +

Derivative

5.0

0.2

2.1

D

I

CKK

2.00.1

37.0

813

632

270.035.1

D

I

CKK

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Based on assumed open-loop model: ( ) (FOPDT)1OL

sKes

sG

Approach (b) - Criteria

• Integral of absolute value of error (IAE)

• Integral of square error (ISE)

• Time-weighted IAE (ITAE)

20

ISE ( )e t dt

0

IAE ( )e t dt

0

ITAE ( )t e t dt

Approach (b) - Remarks

Pick controller parameters to minimize integral.

1. IAE allows larger overall deviation than ISE (with smaller overshoots).

2. ISE needs longer settling time

3. ITAE weights errors occurring later more heavily

Approximate optimum tuning parameters are correlated with K, , (Table 12.3).

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Example 1

0.977

0.680

10Design a PI controller for load change

2 1

Use ITAE criterion

110 0.859 1.69 0.169

2

2 10.674 1.08 1.85

2

s

c c

II

G s es

K K

Example 1

ITAE 0.169 1.85

IAE 0.195 2.02

ISE 0.245 2.44

cK I

Example 2

3.54

7 1

(a) design for load changes (aggrssive)

large overshoot for set-point changes

(b) design for set-pont changes (conservative)

sluggish response to load disturbances

sG s es

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Summary of Tuning Relationships

1. KC is inversely proportional to KPKVKM .

2. KC decreases as / increases.

3. I and D increase as / increases (typically D = 0.25 I ).

4. Reduce Kc, when adding more integral action; increase Kc, when adding derivative action

5. To reduce oscillation, decrease KC and increase I .

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Disadvantages of Tuning Correlations

1. Interactions are ignored (decreased stability limits).

2. Derivative action equipment specific.

3. First order + time delay model can be inaccurate.

4. Kp, can vary.

5. Resolution, measurement errors decrease stability margins.

6. ¼ decay ratio not conservative standard (too oscillatory).

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Example 12.4

Consider a lag-dominant model with θ / τ 0.01:

100

100 1sG s e

s

Design four PI controllers:

a) IMC

b) IMC based on the integrator approximation in Eq. 12-33

c) IMC with Skogestad’s modification (Eq. 12-34)

d) Direct Synthesis method for disturbance rejection (Chen and Seborg, 2002): The controller settings are Kc = 0.551 and

τ 1c

τ 2c

τ 1c

τ 4.91.I

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Evaluate the four controllers by comparing their performance for unit step changes in both set point and disturbance. Assume that the model is perfect and that Gd(s) = G(s).

Solution

The PI controller settings are:

Controller Kc

(a) IMC 0.5 100

(b) Integrator approximation 0.556 5

(c) Skogestad 0.5 8

(d) DS-d 0.551 4.91

I

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Figure 12.8. Comparison of set-point responses (top) and disturbance responses (bottom) for Example 12.4. The responses for the Chen and Seborg and integrator approximation methods are essentially identical.

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On-Line Controller Tuning1. Controller tuning inevitably involves a tradeoff between

performance and robustness.

2. Controller settings do not have to be precisely determined. In general, a small change in a controller setting from its best value (for example, ±10%) has little effect on closed-loop responses.

3. For most plants, it is not feasible to manually tune each controller. Tuning is usually done by a control specialist (engineer or technician) or by a plant operator. Because each person is typically responsible for 300 to 1000 control loops, it is not feasible to tune every controller.

4. Diagnostic techniques for monitoring control system performance are available.

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Controller Tuning and Troubleshooting Control Loops

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Ziegler-Nichols Rules:

These well-known tuning rules were published by Z-N in 1942:

controller Kc I D

P

PI

PID

0.5 KCU

0.45 KCU

0.6 KCU

-

PU/1.2

PU/2

-

-

PU/8

Z-N controller settings are widely considered to be an "industry standard".

Z-N settings were developed to provide 1/4 decay ratio -- too oscillatory?

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Modified Z-N settings for PID control

controller Kc I D

original

Some overshoot

No overshoot

0.6 KCU

0.33 KCU

0.2 KCU

PU/2

PU/2

PU/3

PU/8

PU/3

PU/2

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a

dKCU

4

Figure 12.15 Typical process reaction curves: (a) non-self-regulating process, (b) self-regulating process.

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Figure 12.16 Process reaction curve for Example 12.8.

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Figure 12.17 Block diagram for Example 12.8.

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