CHAPTER 14

Exercises

E14.1

(a)

(b) For the vA source, . (c) Similarly

(d) In part (a) we found that the output voltage is independent of the load resistance. Therefore, the output resistance is zero.

E14.2 (a)

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(b)

E14.3

Direct application of circuit laws gives , , and .

From the previous three equations, we obtain .

Then applying circuit laws gives , , , and

These equations yield . Then substituting values and using the fact that we find

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E14.4 (a)

(Because of the summing-point restraint, )

(Because )

Thus, and (b)

(Note: We assume that )

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E14.5

From the circuit, we can write , , and . From these

equations, we find that . Then because io is independent of RL, we conclude that the output impedance of the amplifier is infinite. Also Rin is infinite because iin is zero.

E14.6 (a)

Using the above equations we eventually find that

(b) Substituting the values given, we find Av = 131.

(c) Because iin = 0, the input resistance is infinite.

(d) Because is independent of RL, the output resistance is zero.

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E14.7 We have from which we conclude that

E14.8

Applying basic circuit principles, we obtain:

From these equations, we eventually find

E14.9 Many correct answers exist. A good solution is the circuit of Figure 14.11 in the book with We could use standard 1%-tolerance resistors with nominal values of k and k.

E14.10 Many correct answers exist. A good solution is the circuit of Figure 14.18 in the book with and We could use standard 1%-tolerance resistors with nominal values of k and

k.

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E14.11 Many correct selections of component values can be found that meet the desired specifications. One possibility is the circuit of Figure 14.19 with:

a 453-k fixed resistor in series with a 100-k trimmer (nominal design value is 500 k)RB is the same as R1

k M M

After constructing the circuit we could adjust the trimmers to achieve the desired gains.

E14.12 The corresponding Bode plot is shown in Figure 14.22 in the book.

E14.13 (a) (b) The input frequency is less than fFP and the current limit of the op amp is not exceeded, so the maximum output amplitude is 4 V.

(c) With a load of 100 the current limit is reached when the output amplitude is 10 mA 100 = 1 V. Thus the maximum output amplitude without clipping is 1 V.

(d) In deriving the full-power bandwidth we obtained the equation:

SRSolving for Vom and substituting values, we have

V

With this peak voltage and RL = 1 k, the current limit is not exceeded.

(e) Because the output, assuming an ideal op amp, has a rate of change exceeding the slew-rate limit, the op amp cannot follow the ideal output, which is

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. Instead, the output changes at the slew-rate limit and the output waveform eventually becomes a triangular waveform with a peak-to-peak amplitude of SR (T/2) = 2.5 V.

E14.14 (a)

Applying basic circuit laws, we have and . These

equations yield .(b)

Applying basic circuit principles, algebra, and the summing-point restraint, we have

(c)

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The drop across Rbias is zero because the current through it is zero. For the source Voff the circuit acts as a noninverting amplifier with a gain Therefore, the extreme output voltages are given by

(d)

Applying basic circuit principles, algebra, and the summing-point restraint, we have

Thus the extreme values of caused by Ioff are

(e) The cumulative effect of the offset voltage and offset current is that Vo ranges from -37 to +37 mV.

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E14.15 (a)

Because of the summing-point constraint, no current flows through Rbias so the voltage across it is zero. Because the currents through R1 and R2 are the same, we use the voltage division principle to write

Then using KVL we have

These equations yield

Assuming an ideal op amp, the resistor Rbias does not affect the gain since the voltage across it it zero.

(b) The circuit with the signal set to zero and including the bias current sources is shown.

We want the output voltage to equal zero. Using Ohm’s law, we can write

. Then writing a current equation at the inverting input, we have . Finally, because of the summing-point restraint, we have These equations eventually yield

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as the condition for zero output due to the bias current sources.

E14.16

Because no current flows into the op-amp input terminals, we can use the voltage division principle to write

Because of the summing-point restraint, we have

Writing a KCL equation at the inverting input, we obtain

Substituting for vy and solving for the output voltage, we obtain

If we have the equation for the output voltage reduces to

E14.17 (a)

for

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for

and so forth. A plot of vo(t) versus t is shown in Figure 14.37 in the book.

(b) A peak-to-peak amplitude of 2 V implies a peak amplitude of 1 V. The first (negative) peak amplitude occurs at Thus we can write

which yields

E14.18 The circuit with the input source set to zero and including the bias current sources is:

Because the voltage across R is zero, we have iC = IB, and we can write

(a) For C = 0.01 F we have (b) For C = 1 F we have Notice that larger capacitances lead to smaller output voltages.

E14.19

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Because , we have and

E14.20

E14.21 The transfer function in decibels is

For we have

This expression shows that the gain magnitude is reduced by 20n decibels for each decade increase in f.

E14.22 Three stages each like that of Figure 14.40 must be cascaded. From Table 14.1, we find that the gains of the stages should be 1.068, 1.586, and 2.483. Many combinations of component values will satisfy the requirements of the problem. A good choice for the capacitance value is 0.01 F, for which we need

Also is a good choice.

Problems

P14.1 The differential voltage is:

and the common-mode voltage is:

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P14.2 An ideal operational amplifier has the following characteristics:1. Infinite input impedance.2. Infinite gain for the differential input signal.3. Zero gain for the common-mode input signal.4. Zero output impedance.5. Infinite bandwidth.

P14.3*

P14.4 The terminals of a real op amp include the inverting input, the noninverting input, the output, and one or more power-supply terminals.

P14.5 According to the summing-point constraint, the output voltage of an op amp assumes the value required to produce zero differential input voltage and zero current into the op-amp input terminals. This principle applies when negative feedback is present but not when positive feedback is present.

P14.6* The steps in analysis of an amplifier containing an ideal op amp are:

1. Verify that negative feedback is present.2. Assume that the differential input voltage and the input currents are zero.3. Apply circuit analysis principles including Kirchhoff’s and Ohm’s laws to write circuit equations. Then solve for the quantities of interest.

P14.7 The inverting amplifier configuration is shown in Figure 14.4 in the text. The voltage gain is given by , the input impedance is equal to R1, and the output impedance is zero.

P14.8 This is an inverting amplifier having a voltage gain given by . Thus we have

Sketches of vin(t) and vo(t) are

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P14.9* The circuit has negative feedback so we can employ the summing-point constraint. Then successive application of Ohm’s and Kirchhoff’s laws starting from the left-hand side of the circuit produces the results shown:

From these results we can use KVL to determine that from which we have

P14.10 This circuit has positive feedback and the output can be either +10 V or -10 V. Writing a current equation at the inverting input terminal of the op amp we have

Solving we find

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For V, we have V. On the other hand for V, we have V. Notice that for vx positive the output remains stuck at its positive extreme and for vx negative the output remains stuck at its negative extreme.

P14.11 Using the summing-point constraint, we have and

Solving, we have

P14.12 Using the summing-point constraint, we have and

Thus, we have

P14.13 Using the summing-point constraint, we have and

Solving, we have

P14.14 The noninverting amplifier configuration is shown in Figure 14.11 in the text. Assuming an ideal op amp, the voltage gain is given by

, the input impedance is infinite, and the output impedance is zero.

P14.15*The circuit diagram of the voltage follower is:

Assuming an ideal op amp, the voltage gain is unity, the input impedance is infinite, and the output impedance is zero.

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P14.16 If the source has a non-zero series impedance, loading (reduction in voltage) will occur when the load is connected directly to the source. On the other hand, the input impedance of the voltage follower is very high (ideally infinite) and loading does not occur. If the source impedance is very high compared to the load impedance, the voltage follower will deliver a much larger voltage to the load than direct connection.

P14.17 (a)

(b)

(c) No current flows through the 3-k resistor. Thus .

(d)

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(e)

P14.18

From the circuit we can write:

Thus we have

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P14.19*The circuit diagram is:

Writing a current equation at the noninverting input, we have(1)

Using the voltage-division principle we can write:(2)

Using Equation (2) to substitute for v1 in Equation (1) and rearranging, we obtain:

P14.20 Analysis of the circuit using the summing-point constraint yields

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Substituting the expression given for vin yields

Then setting the dc component to zero, we have

which yields R2 = 10 k.

P14.21 (a)

Since io is independent of the load, the output impedance is infinite.

(b) The circuit diagram is:

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Writing KVL around loop #1, we have

Writing KVL around loop #2, we have

Algebra produces . Since io is independent of the load, the output impedance is infinite.

P14.22 (a) This is an inverting amplifier having and . The

input power is

The output power is

The power gain is

(b) This is a noninverting amplifier having . Therefore , and . Thus, the noninverting amplifier has the larger power gain.

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P14.23*

(a)

(b) Since vo is independent of RL, the output behaves as a perfect voltage source, and the output impedance is zero.

(c) The input voltage is zero because of the summing-point constraint, and the input impedance is zero.

(d) This is an ideal transresistance amplifier.

P14.24 The inverting amplifier is shown in Figure 14.4 in the text and the voltage gain is . Thus to achieve a voltage gain magnitude of 2, we would select the nominal values such that

. However for 5%-tolerance resistors, we have

Thus we have

Thus Av 2 plus 10.5% minus 9.5%.

P14.25 The noninverting amplifier is shown in Figure 14.11 in the text, and the voltage gain is . Thus to achieve a voltage gain magnitude of 2, we would select the nominal values such that

. However for 5%-tolerance resistors, we have

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Thus we have

Thus Av 2 5%.P14.26*The circuit diagram is:

Because of the summing-point constraint, we have vin 0. Thus Rin 0. Because the output current is independent of RL, the output impedance is infinite. In other words looking back from the load terminals, the circuit behaves like an ideal current source.

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P14.27

By the voltage-division principle, we have

Then, we can write

Thus, as T varies from 0 to unity, the circuit gain varies from -1 through

to 0 to +1.

P14.28 (a) This circuit has negative feedback. It is the voltage follower and

has unity gain except that the output voltage cannot exceed 5 V. The output waveform is:

(b) This circuit has positive feedback, and vo = +5 if the differential input voltage vid is positive. On the other hand, vo = -5 if vid is negative. In this circuit, we have

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Thus, the output waveform is:

P14.29*(a) This circuit has negative feedback. Assuming an ideal op amp, we

have .

(b) This circuit has positive feedback. Therefore, the summing-point constraint does not apply.

From the circuit, we can write

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Solving for vid, we have

If vid > 0, then vo = +5. On the other hand, if vid < 0, then vo = -5.The output waveform is

P14.30 Very small resistances lead to excessively large currents, possibly exceeding the capability of the op amp, creating excessive heat or overloading the power supply.

Very large resistances lead to instability due to leakage currents over the surface of the resistors and circuit board. Stray pickup of undesired signals is also a problem in high-impedance circuits.

P14.31 Use the inverting amplifier configuration:

Pick R2nom = 10R1nom to achieve the desired gain magnitude.Pick R1nom > 10 kΩ to achieve input impedance greater than 10 kΩ.Pick R1nom and R2nom < 10 MΩ because higher values are impractical.

Many combinations of values will meet the specifications. For example:

(a) Use 5% tolerance resistors. R1 = 100 kΩ and R2 = 1 MΩ.(b) Use 1% tolerance resistors. R1 = 100 kΩ and R2 = 1 MΩ.(c) R2 =1 MΩ 1% tolerance. R1 = 95.3 kΩ 1% tolerance

fixed resistor in series with a 10-kΩ adjustable resistor. After constructing the circuit, adjust to achieve the desired gain magnitude.

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P14.32*To achieve high input impedance and an inverting amplifier, we cascade a noninverting stage with an inverting stage:

The overall gain is:

Many combinations of resistance values will achieve the given specifications. For example:

. (Then the first stage becomes a voltage follower.) This is a particularly good choice because fewer resistors affect the overall gain, resulting in small overall gain variations.R4 = 100 kΩ, 5% tolerance.R3 = 10 kΩ, 5% tolerance.

P14.33 We use a noninverting amplifier and place a resistor in parallel with the input terminals to achieve the desired input impedance.

R1 = 1 kΩ, 1% tolerance.Many combinations of values for R2 and R3 will meet the given specifications. For example:

R2 = 1 kΩ, 1% tolerance.R3 = 9.09 kΩ, 1% tolerance.

(These values result in a nominal gain of 10.09, which is within the specified range.)

P14.34 Here are two answers:

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Many other correct answers exist.

P14.35*One possibility is to place unity-gain voltage follower circuits between the sources and the input terminals of the circuits designed for Problem P14.34. A better answer (because it requires fewer op amps) is:

All resistors are 1% tolerance.

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P14.36 To avoid excessive variations in because of changes in Rs, we need to have . Rin =100 kΩ is sufficiently large. Thus, a suitable circuit is

R1 and R2 should be 1% tolerance resistors.

P14.37 To avoid excessive gain variations because of changes in the source resistances, we need to have input resistances that are much greater than the source resistances. Many correct answers exist. Here is one possibility:

The fixed resistors should be specified to have a tolerance of 1% because they are more stable in value than 5% tolerance resistors. The adjustment procedure is:

1. Set v1= 0 and v2 = + 1 V. Then, adjust the 2-kΩ potentiometer to obtain vo = 3 V.

2. Set v1= 1 V and v2 = 0. Then, adjust the 1-kΩ potentiometer to obtain vo = -10.

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P14.38*A solution is:

P14.39 (a)

From the circuit, we can write:

Dividing the respective sides of the previous equations yields:

Substituting values, we obtain:

(compared to unity for an ideal op amp)(b)

(compared to ∞ for an ideal op amp)

(c) The circuit for determining the output impedance is:

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(versus Zo = 0 for an ideal op amp)

P14.40 (a) From the circuit (shown in Figure P14.40 in the text), we can write:

Algebra results in:

Substituting values, we obtain: (compared to -10 for an ideal op amp)

(b) From the circuit, we can write:

Algebra results in

Substituting values, we obtain: (compared to 1 kΩ for an ideal op amp

(c) To find the output impedance, we zero the input source and connect a test source to the output terminals. The circuit is:

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where

Substituting values, we obtain: for an ideal op amp

P14.41*Equation 14.34 states:

Thus, for A0CL = 10, we have

For A0CL = 100, we havefBCL = 150 kHz

P14.42 Equation 14.23 gives the open-loop gain as a function of frequency:

For f = 100 Hz, we have

Similarly, we have

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P14.43 Equation 14.32 gives the closed-loop gain as a function of frequency:

However, the dc closed-loop gain is given as 10 so we have

For f = 10 kHz, we have

Solving, we find 20.65 kHz. Then the gain bandwidth product is

P14.44 Equation 14.32 gives the closed-loop gain as a function of frequency:

The phase shift is Thus at 200 kHz, we havewhich yields MHz. Then the gain

bandwidth product is .

P14.45 Alternative 1:

The closed-loop bandwidth is .

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Alternative 2:

For each stage, we have and the gain as a function of frequency is:

The overall gain is

To find the overall 3-dB bandwidth, we have

Solving, we find that

Thus, the two-stage amplifier has wider bandwidth.

P14.46*

P14.47 (a)

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(b) . (It is limited by the maximum output voltage capability of the op amp.)

(c) In this case, the limit is due to the maximum current available from the op amp. Thus, the maximum output voltage is:

(d) In this case, the slew-rate is the limitation.

(e)

P14.48 The desired output voltage is

and the rate of change of the output is

The maximum rate of change of the output is

Thus, we require the slew rate to be at least as large as the maximum rate of change of the output voltage.

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P14.49 To avoid slew-rate distortion, the op-amp slew-rate specification must exceed the maximum rate of change of the output-voltage magnitude. For the gain and input given in the problem, the output voltage is

The rate of change is

The maximum value occurs at t = 0, and is 10 V/s. Thus the required minimum slew-rate specification is 10 V/s or 107 V/s.

P14.50 To avoid slew-rate distortion, the op-amp slew-rate specification must exceed the maximum rate of change of the output-voltage magnitude. For a voltage follower, the gain is unity. For the input given in the problem, the output voltage is

The rate of change is

The maximum value occurs at t = 3, and is 6 V/s. Thus, the required minimum slew-rate specification is 6 V/s or 6106 V/s.

P14.51*The output waveform is

The rate of change is:

P14.52 (a)

(b) The limit on peak output voltage is due to the current limit of the op amp. Because R2 is much greater than RL, the current through R2 can be neglected. Thus, we have:

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(c) In this case, . (This is the maximum voltage that the op amp can achieve.)

(d) In this case, the slew rate limits the maximum voltage.

P14.53 (a) One op amp is configured as an inverting amplifier with a gain of -2 and the other op amp is configured as a noninverting amplifier with

a gain +2. Thus, we can write:

(b)

(c) The peak value of at the threshold of clipping is 28 V.

P14.54*See Figure 14.29 in the text.

P14.55 The net effect of bias currents, offset current and offset voltage is to add a constant (dc) term to the desired output signal. Often this is undesirable.

P14.56 A FET-input op amp has much lower values of bias current and offset current than a BJT-input op amp.

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P14.57*The worst-case outputs due to the offset voltage are:

For the bias current, the worst case output voltages are:

For the offset current, the worst-case output voltages are:

Due to all of the imperfections, the extreme output voltages are:

P14.58 The circuit shown in Figure P14.58 is a poor design because no dc path is provided for the bias current flowing into the noninverting input terminal. The bias current would charge the capacitance eventually resulting in a large voltage that would exceed the linear range of the op amp.

The solution is to add a resistance as shown:

To minimize the effect of the bias currents, we should select:

P14.59 (a) The circuit with the signal source zeroed and including the offset

voltage source is:

The output voltage is:

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Thus to keep less than 100 mV in magnitude, we need an op amp with that is less than 9.09 mV.

(b) The circuit with only the bias current sources is:

The output voltage is:

Thus to keep less than 100 mV in magnitude, we need an op amp with less than 1μA.

(c) If we add a resistance in series with the noninverting input terminal, the effects of the bias currents will cancel. The circuit is:

(d) With the resistance of part (c) in place, the output voltage due to the offset current is:

Thus to keep less than 100 mV in magnitude, we need an op amp with less than 1 μA.

P14.60*The circuit diagram is shown in Figure 14.33 in the text. To achieve a nominal gain of 10, we need to have R2 = 10R1. Values of R1 ranging from about 1 kΩ to 100 kΩ are practical. A good choice of values is R1 = 10 kΩ and R2 = 100 kΩ.

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P14.61 The circuit diagram is shown in Figure 14.34 in the text. To achieve a nominal gain of 10, we need to have R2 = 9R1. Values of R1 ranging from about 1 kΩ to 100 kΩ are good. A good choice of values is R1 = 20 kΩ andR2 = 180 kΩ. Any value of R in the range from 1 kΩ to 1 MΩ is acceptable.

P14.62 (a) The differential and common-mode components of the input signal are:

(b) As discussed in the book, the first-stage gain for the differential signal is which for the values given is 10. On the other hand, the first-stage gain for the common-mode component is unity. Thus the output voltages are:

(c) Assuming ideal op amps and perfectly matched components, the output of the circuit is

P14.63*This is an integrator circuit, and the output voltage is given by:

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Each pulse reduces vo by 0.5 V. Thus, 20 pulses are required to produce vo = -10V.

P14.64 This is a differentiator circuit, and the output is given by:

A sketch of versus is:

P14.65 Let displacement in meters. Then, we have

and we want

and

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A circuit that produces the desired voltages is:

We need . Suitable component values are:

P14.66*All of the circuits are of the form:

This is the inverting amplifier configuration and the gain is

(a)

where The magnitude Bode plot is:

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(b)

where

The magnitude Bode plot is:

(c)

where

The magnitude Bode plot is:

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P14.67 The gain is:

In decibels, the gain magnitude is

The sketch is:

P14.68 The gain is:

In decibels, the gain magnitude is

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The sketch is:

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