chapter 05 - msp430 isa

Chapter 5 – MSP430 ISAThe Instruction Set

Chapter 05 - MSP430 ISA 2BYU CS/ECEn 124

Topics to Cover…

MSP430 ISA Assembler Primer Instruction Formats Double Operand Instructions Single Operand Instructions Jump Instructions Addressing Modes Instruction Length Instruction Cycles Instruction Disassembly


Problem Machine

More concrete, machine-dependent; errorprone, harder to write, read, debug, maintain

Abstract, machine-independent;easier to write, read, debug, maintain

Ass

em

ble

r

415E 0001410F532F5F0E4EE1 0000415E 0001531E410F532F5F0E415D 0001410F532F5F0D4EED 0000415F 0001531F410E532E5F0E41EE 0000

Machinelanguageinstructions

Instruction =Many cycles

Levels of Transformation

Com

pile

r

MOV.B 0x0001(SP),R14MOV.W SP,R15INCD.W R15ADD.W R15,R14MOV.B @R14,0x0000(SP)MOV.B 0x0001(SP),R14INC.W R14MOV.W SP,R15INCD.W R15ADD.W R15,R14MOV.B 0x0001(SP),R13MOV.W SP,R15INCD.W R15ADD.W R15,R13MOV.B @R14,0x0000(R13)MOV.B 0x0001(SP),R15INC.W R15MOV.W SP,R14INCD.W R14ADD.W R15,R14MOV.B @SP,0x0000(R14)

Assemblylanguageinstructions

One statement =Many instructions

Cod

erlampDoesntWork(){ if(unPlugged) { plugin(); } else if(burnedOut) { replace(); } else { buyNewLamp(); }}

High-levellanguagestatements

One algorithm =Many statements

Algorithm

Problem solvedby Algorithm

En

gine

er

Problem

Problem


Instruction Set Architecture

The computer ISA defines all of the programmer-visible components and operations of the computer

Memory organization address space -- how may locations can be addressed? addressibility -- how many bits per location?

Register set how many? what size? how are they used?

Instruction set opcodes data types addressing modes

ISA provides all information needed for someone that wants to write a program in machine language (or translate from a high-level language to machine language).

MSP430 ISA


MSP430 ISA

RISC/CISC machine 27 orthogonal instructions

8 jump instructions 7 single operand instructions 12 double operand instructions

4 basic addressing modes. 8/16-bit instruction addressing formats.

Memory architecture 16 16-bit registers 16-bit Arithmetic Logic Unit (ALU). 16-bit address bus (64K address space) 16-bit data bus (8-bit addressability) 8/16-bit peripherals

MSP430 ISA


MSP430 Registers

R0 (PC) – Program Counter Points to (has the address of) the next instruction to be fetched. Each instruction occupies an even number of bytes. Therefore, the

least significant bit (LSB) of the PC register is always zero. After executing an instruction, the PC register will have

incremented by 2, 4, or 6 and point to the next instruction. R1 (SP) – Stack Pointer

The MSP430 CPU pushes the return address of subroutine calls and interrupts on the stack.

User programs store local data on the stack. The SP can be incremented or decremented automatically with

each stack access. The stack “grows down” thru RAM and thus SP must be initialized

with a valid RAM address. SP always points to an even address, so its LSB is always zero.

MSP430 ISA


MSP430 Registers

R2 (SR/CG1) – Status Register The status of the MSP430 CPU is found in register R2. Only accessible through register addressing mode - all other

addressing modes are reserved to support the constant generator.

MSP430 ISA

Carry bitC

Zero bitZ

Negative bitN

General interrupt enableGIE

Turns off the CPU.CPUOFF

Oscillator offOSCOFF

Turns off the DCO dc generator.SCG0

Turns off the SMCLK.SCG1

Overflow bitV

R3 (CG2) – Constant Generator

R4-R15 – General Purpose registers

Register As Constant Remarks

R2 00 - Register mode

R2 01 (0) Absolute mode

R2 10 00004h +4, bit processingR2 11 00008h +8, bit processing

R3 00 00000h 0, word processing

R3 01 00001h +1R3 10 00002h +2, bit processingR3 11 0FFFFh -1, word processing


16 bit Arithmetic Logic Unit (ALU). Performs instruction arithmetic and

logical operations. Instruction execution affects the state

of the following flags: Zero (Z) Carry (C) Overflow (V) Negative (N)

The MCLK (Master) clock signal drives the CPU and ALU logic.

MSP430 ALU

MSP430 ISA


MSP430 Memory OrganizationMSP430 ISA

A little-endian machine stores the least significant byte first (lowest address) within a word data type.

Chapter 05 - MSP430 ISA 10

Quiz 5.1

Pair up with another student and answer the following questions:

1. What is an ISA?

2. List distinctive properties of the MSP430 ISA.

BYU CS/ECEn 124

MSP430 ISA


Quiz 5.1 (answers)

Pair up with another student and answer the following questions:

1. What is an ISA?

2. List distinctive properties of the MSP430 ISA.

BYU CS/ECEn 124

All of the programmer-visible components and operations of the computer

27 orthogonal instructions7 addressing modes.8/16-bit addressing formats.16 16-bit registersConstant generator

16-bit Arithmetic Logic Unit (ALU). 16-bit address bus (64K address space)16-bit data bus (8-bit addressability)8/16-bit peripheralsLittle-endian storage order

MSP430 ISA


MSP430 Assembler

A typical assembly language line has four parts:

1. label—starts in the column 1 and may be followed by a colon (:) for clarity.

2. operation—either an instruction, which is translated into binary machine code for the processor itself, or a directive, which controls the assembler.

3. operands—data needed for this operation (not always required).

4. comment—text following a semicolon (;).

start: mov.w #0x0280,sp ; setup stack pointer

Label: Operation Operands Comment

Assembler Primer


MSP430 Assembler

Labels are case sensitive, but instructions and directives are not - pick a style and stick with it.

Use comments freely in assembly language – otherwise your program is unreadable and very difficult to debug.

The default base (radix) of numbers in assembly language is decimal. The C-style notation 0xA5 for hexadecimal numbers is now widely accepted by assemblers. Other common notations include $A5, h'A5' and 0A5h. Binary numbers can similarly be written as 10100101b.

Use symbolic names for constants and expressions. The ".equ" and ".set" assembler directives provide macro text replacement for this purpose. (Make upper case.)

Assembler Primer


Assembler Coding StyleAssembler Primer

;*************************************************************************; CS/ECEn 124 Lab 1 - blinky.asm: Software Toggle P1.0;; Description: Toggle P1.0 by xor'ing P1.0 inside of a software loop.;*************************************************************************DELAY .equ 0 .cdecls C,"msp430.h" ; MSP430 .text ; beginning of executable codereset: mov.w #0x0280,SP ; init stack pointer mov.w #WDTPW+WDTHOLD,&WDTCTL ; stop WDT bis.b #0x01,&P1DIR ; set P1.0 as output

mainloop: xor.b #0x01,&P1OUT ; toggle P1.0 mov.w #DELAY,r15 ; use R15 as delay counter

delayloop: sub.w #1,r15 ; delay over? jnz delayloop ; n jmp mainloop ; y, toggle led

.sect ".reset" ; MSP430 RESET Vector .word reset ; start address .end

Labels start in column 1 and are 10 characters or fewer.

Instructions / DIRECTIVES start in column 12.

Operands start in column 21.

Comments start in column 45.

Use macros provided in the MSP430 header file.

The ".cdecls" directive inserts a header file into your program.

Assembler directives begin with a period (.)

The ".end" directive is the last line of your program.

Instructions are lower case and macros are UPPER CASE.

No line should exceed 80 characters.

Begin writing your assembly code after the ".text" directive.


MSP430 Instructions

There are three formats used to encode instructions for processing by the CPU core: Double operand Single operand Jumps

The instructions for double and single operands, depend on the suffix used, (.w) word or (.b) byte

These suffixes allow word or byte data access If the suffix is ignored, the instruction processes

word data by default

Instruction Formats


MSP430 Instructions

The MSP430 ISA uses three formats to encode instructions for processing by the CPU core: Double operand Single operand Jumps

Single and double operand instructions process word (16-bits) or byte (8-bit) data operations. Instruction suffix selects word (.w) or byte (.b) Instructions process word data by default.

The first 4-bits (nybble) of an instruction is called the opcode and specifies the instruction format.

Instruction Formats


MSP430 InstructionsInstruction Formats

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0

Instruction Register

Memory0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0

0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1

0 0 1 0 1 1 1 1 1 1 1 0 0 1 0 0

0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 1

0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0

mov.w r5,r4

rrc.w r5

jc main

mov.w #0x0600,r1

Opcode Instruction Format0000 Undefined

Single Operand0001 RCC, SWPB, RRA, SXT, PUSH, CALL, RETI0010 JNE, JEQ, JNC, JC

Jumps0011 JN, JGE, JL, JMP0100 MOV

Double Operand

0101 ADD0110 ADDC0111 SUBC1000 SUB1001 CMP1010 DADD1011 BIT1100 BIC1101 BIS1110 XOR1111 AND

1111111011011100101110101001100001110110010101000011001000010000

4 to 16 Decoder

Opcode

PC


MPS430 Instruction Formats

Format I: Instructions with two operands:15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Opcode S-reg Ad b/w As D-reg

MSP430 Instructions

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Opcode b/w Ad D/S-reg

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Opcode Condition 10-bit, 2’s complement PC offset

Format II: Instruction with one operand:

Format III: Jump instructions:


Format I: Double Operand

Double operand instructions:Mnemonic Operation Description

Arithmetic instructions

ADD(.B or .W) src,dst src+dstdst Add source to destination

ADDC(.B or .W) src,dst src+dst+Cdst Add source and carry to destination

DADD(.B or .W) src,dst src+dst+Cdst (dec) Decimal add source and carry to destination

SUB(.B or .W) src,dst dst+.not.src+1dst Subtract source from destination

SUBC(.B or .W) src,dst dst+.not.src+Cdst Subtract source and not carry from destination

Logical and register control instructions

AND(.B or .W) src,dst src.and.dstdst AND source with destination

BIC(.B or .W) src,dst .not.src.and.dstdst Clear bits in destination

BIS(.B or .W) src,dst src.or.dstdst Set bits in destination

BIT(.B or .W) src,dst src.and.dst Test bits in destination

XOR(.B or .W) src,dst src.xor.dstdst XOR source with destination

Data instructions

CMP(.B or .W) src,dst dst-src Compare source to destination

MOV(.B or .W) src,dst srcdst Move source to destination

Double Operand Instructions


Example: Double Operand

Copy the contents of a register to another register Assembly: mov.w r5,r4 Instruction code: 0x4504

One word instruction The instruction instructs the CPU to copy the 16-bit 2’s

complement number in register r5 to register r4

Opcodemov

S-regr5

AdRegister

b/w16-bits

AsRegister

D-regr4

0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0

Double Operand Instructions


Format II: Single Operand

Single operand instructions:

Mnemonic Operation Description

Logical and register control instructions

RRA(.B or .W) dst MSBMSB…LSBC

Roll destination right

RRC(.B or .W) dst CMSB…LSBC Roll destination right through carry

SWPB( or .W) dst Swap bytes Swap bytes in destination

SXT dst bit 7bit 8…bit 15 Sign extend destination

PUSH(.B or .W) src SP-2SP, src@SP Push source on stack

Program flow control instructions

CALL(.B or .W) dst SP-2SP,PC+2@SPdstPC

Subroutine call to destination

RETI @SP+SR, @SP+SP Return from interrupt

Single Operand Instructions


Example: Single Operand

Logically shift the contents of register r5 to the right through the status register carry

Assembly: rrc.w r5 Instruction code: 0x1005

One word instruction The CPU shifts the 16-bit register r5 one bit to the right

(divide by 2) – the carry bit prior to the instruction becomes the MSB of the result while the LSB shifted out replaces the carry bit in the status register

Opcoderrc

b/w16-bits

AdRegister

D-regr5

0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1

Single Operand Instructions


Jump Instruction Format

Jump instructions are used to direct program flow to another part of the program.

The condition on which a jump occurs depends on the Condition field consisting of 3 bits:

000: jump if not equal 001: jump if equal 010: jump if carry flag equal to zero 011: jump if carry flag equal to one 100: jump if negative (N = 1) 101: jump if greater than or equal (N = V) 110: jump if lower (N V) 111: unconditional jump

Jump Instructions

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Opcode Condition 10-bit, 2’s complement PC offset


Jump Instruction Format

Jump instructions are executed based on the current PC and the status register

Conditional jumps are controlled by the status bits Status bits are not changed by a jump instruction The jump off-set is represented by the 10-bit, 2’s

complement value:

Thus, the range of the jump is -511 to +512 words, (-1023 to 1024 bytes ) from the current instruction

Note: Use a BR instruction to jump to any address

22 offsetoldnew PCPCPC

Jump Instructions


Example: Jump Format

Continue execution at the label main if the carry bit is set Assembly: jc main Instruction code: 0x2fe4

One word instruction The CPU will add to the incremented PC (R0) the value

-28 x 2 if the carry is set

OpcodeJC

ConditionCarry Set

10-Bit, 2’s complement PC offset-28

0 0 1 0 1 1 1 1 1 1 1 0 0 1 0 0

Jump Instructions


Today…

Exam I Thursday, Feb 7 thru Monday, Feb 11 Testing Center, Grant Building 60 Questions, Chapters 1 through 5 50% penalty if you miss exam Good idea to have scratch paper on hand 1 page, handwritten notes Take the pre-test exam!! Study slides, homework, and reading material

BYU CS/ECEn 124


Quiz 5.2

1. How are the sixteen MSP430 registers the same?

2. How do they differ?

3. What does 8-bit addressibility mean?

4. Why does the MSP430 have a 16-bit data bus?

5. What does the following instruction do?

addc.w r11,r12

BYU CS/ECEn 124

MSP430 Instructions


Quiz 5.2 (answers)

1. How are the sixteen MSP430 registers the same?

16-bits, orthogonal, single cycle access

2. How do they differ?4 special, 12 work

3. What does 8-bit addressibility mean?

Smallest accessible size of memory

BYU CS/ECEn 124

MSP430 Instructions


Quiz 5.2 (answers)

4. Why does the MSP430 have a 16-bit data bus?

Speed! Convenient for instruction and stack access

5. What does the following instruction do?

addc.w r11,r12Fetches the contents of registers r11, r12, and the carry bit, uses the ALU to sum these values, and stores the results back in register r12.

BYU CS/ECEn 124

MSP430 Instructions

MSP430 Addressing Modes


MPS430 Addressing Modes

BYU CS/ECEn 124

1 ;**************************************************** 2 .cdecls C,"msp430.h" ; MSP430 3 000 .text 4 5 8000 540A reset: add.w r4,r10 ; r10 = r4 + r10 6 8002 541A add.w 6(r4),r10 ; r10 = M(r4+6) + r10 8004 0006 7 8006 542A add.w @r4,r10 ; r10 = M(r4) + r10 8 8008 543A add.w @r4+,r10 ; r10 = M(r4++) + r10 9 800a 501A add.w cnt,r10 ; r10 = M(cnt) + r10 800c 0012 10 800e 521A add.w &cnt,r10 ; r10 = M(cnt) + r10 8010 801E11 8012 503A add.w #100,r10 ; r10 = 100 + r10 8014 0064 12 8016 531A add.w #1,r10 ; r10 = 1 + r1013 8018 5090 add.w cnt,var ; var = M(cnt) + M(var) 801a 0004 801c 0004 14 15 801e 0000 cnt: .word 016 8020 0000 var: .word 0

Addressing Modes

RegisterIndexed RegisterIndirect RegisterIndirect Auto-incSymbolic or PC relative

Absolute

Immediate

Constant


Source Addressing Modes

The MSP430 has four basic addressing modes for the source address: 00 = Rs - Register 01 = x(Rs) - Indexed Register 10 = @Rs - Register Indirect 11 = @Rs+ - Indirect Auto-increment

When used in combination with registers R0-R3, three additional source addressing modes are available: label - PC Relative, x(PC) &label – Absolute, x(SR) #n – Immediate, @PC+

Addressing Modes


Destination Addressing Modes

There are only two basic addressing modes for the destination address: 0 = Rd - Register 1 = x(Rd) - Indexed Register

When used in combination with registers R0/R2, two additional destination addressing modes are available: label - PC Relative, x(PC) &label – Absolute, x(SR)

Addressing Modes


00 = Register ModeAddressing Modes

Registers

CPUMemory

ADDER

add.w r4,r10 ;r10 = r4 + r10

PCPC

R10

R4

IRData Bus (1

cycle)0x540

a0x540a PC

ALU

Address Bus

+2


Memory

BYU CS/ECEn 124

01 = Indexed ModeAddressing Modes

Registers

Address Bus

Data Bus (+1 cycle)

Data Bus (+1 cycle)

CPU

ADDER

add.w 6(r4),r10 ;r10 = M(r4+6) + r10

0x0006

PCPCPC

R10

R4

IRData Bus (1

cycle)0x541

a0x541a PC

ALU

Address

Bus

+2+2


Memory

BYU CS/ECEn 124

10 = Indirect Register ModeAddressing Modes

Registers

Address Bus

Data Bus (+1 cycle)

CPU

ADDER

add.w @r4,r10 ;r10 = M(r4) + r10

PCPC

R10

R4

IRData Bus (1

cycle)0x542

a

Address Bus

0x542a PC

ALU

+2


Memory

BYU CS/ECEn 124

Addressing Modes

Registers

Data Bus (+1 cycle)

CPU

ADDER

11 = Indirect Auto-increment Mode

add.w @r4+,r10 ;r10 = M(r4+) + r10

PCPC

R10

R4

IRData Bus (1

cycle)0x543

a

Address Bus

PC0x543

a

Address Bus0002

ALU

+2


Memory

BYU CS/ECEn 124

Addressing Modes

Registers

Address Bus

Data Bus (+1 cycle)

Data Bus (+1 cycle)

CPU

ADDER

01 w/R0 = Symbolic Mode (PC Relative)

cnt

add.w cnt,r10 ;r10 = M(cnt) + r10

0x000c

PCPCPC

PC

R10

IRData Bus (1

cycle)0x501

a0x501a PC

ALU

Address

Bus

+2+2


Memory

BYU CS/ECEn 124

Addressing Modes

Registers

Address Bus

Data Bus (+1 cycle)

Data Bus (+1 cycle)

CPU

ADDER

cnt

01 w/R2 = Absolute Mode

0000

add.w &cnt,r10 ;r10 = M(cnt) + r10

0xc018

PCPCPC

R10

IRData Bus (1

cycle)0x521

a0x521a PC

ALU

Address

Bus

+2+2


Memory

BYU CS/ECEn 124

Addressing Modes

Registers

CPU

ADDER

11 w/R0 = Immediate Mode

add.w #100,r10 ;r10 = 100 + r10

PCPCPC

R10

Data Bus (+1 cycle)

IRData Bus (1

cycle)0x503

a PC0x503

a0x0064

ALU

Address

Bus

+2+2


Memory

BYU CS/ECEn 124

Addressing Modes

Registers

CPU

ADDER

Constant Generator

add.w #1,r10 ;r10 = #1 + r10

PCPC

R10

00000001000200040008ffff

IRData Bus (1

cycle)0x531

a

Address Bus

PC0x531

a

ALU

+2


Memory

BYU CS/ECEn 124

Addressing Modes

Registers

Address Bus

Data Bus (+1 cycle)

Data Bus (+1 cycle)

CPU

ADDER

3 Word Instruction (6 cycles)

cnt

add.w cnt,var ;var = M(cnt) + M(var)

0x000c

PCPCPC

varAddress Bus

Data Bus (+1 cycle)

Data Bus (+1 cycle)

PC

Data Bus (+1 cycle)0x021

8

IRData Bus (1

cycle)0x509

00x5090PC PC

ALU

Address

Bus

+2+2+2

Instruction Length

Instruction Length

1 word for instruction

Format I:

Format II:

Format III:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Opcode S-reg Ad b/w As D-reg

MSP430 Instructions

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Opcode b/w Ad D/S-reg

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Opcode Condition 10-bit, 2’s complement PC offset

1 additional word for each of the following addressing modes:

Source index mode (As = 01)

mov 10(r4),r5mov cnt,r5mov &P1IN,r5

BYU CS/ECEn 124 Chapter 05 - MSP430 ISA 44

mov #100,r5 Source immediate mode (As = 11, SR = PC)

mov r4,10(r5)mov r4,cntmov r4,&P1OUT

Destination index mode (Ad = 1)

BYU CS/ECEn Chapter 6 - MSP430 Microarchitecture 45

Quiz 5.3

What is the length (in words) for each of the following instructions?

Instruction L Instruction Ladd.w r5,r6 mov.w EDE,TONIadd.w cnt(r5),r6 mov.b &MEM,&TCDATadd.w @r5,r6 mov.w @r10,r11add.w @r5+,r6 mov.b @r10+,tab(r6)add.w cnt,r6 mov.w #45,TONIadd.w &cnt,r6 mov.w #2,&MEMadd.w #100,r6 mov.b #1,r11mov.w r10,r11 mov.w #45,r11mov.w @r5,6(r6) mov.b #-1,-1(r15)mov.w 0(r5),6(r6) mov.w @r10+,r10

Instruction Length

1.2.3.4.5.6.7.8.9.

10.

11.12.13.14.15.16.17.18.19.20.


Quiz 5.3 (solution)

What is the length (in words) for each of the following instructions?

Instruction L Instruction Ladd.w r5,r6 mov.w EDE,TONIadd.w cnt(r5),r6 mov.b &MEM,&TCDATadd.w @r5,r6 mov.w @r10,r11add.w @r5+,r6 mov.b @r10+,tab(r6)add.w cnt,r6 mov.w #45,TONIadd.w &cnt,r6 mov.w #2,&MEMadd.w #100,r6 mov.b #1,r11mov.w r10,r11 mov.w #45,r11mov.w @r5,6(r6) mov.b #-1,-1(r15)mov.w 0(r5),6(r6) mov.w @r10+,r102

12221121

221232133

Instruction Length

1.2.3.4.5.6.7.8.9.

10.

11.12.13.14.15.16.17.18.19.20.3 1

Blinky Lab 47BYU CS/ECEn 124

Cycles Per Instruction...

Instruction timing: 1 cycle to fetch instruction word +1 cycle if source is @Rn, @Rn+, or #Imm +2 cycles if source uses indexed mode

1st to fetch base address 2nd to fetch source Includes absolute and symbolic modes

+2 cycles if destination uses indexed mode +1 cycle if writing destination back to memory +1 cycle if writing to PC (R0) Jump instructions are always 2 cycles

Instruction Clock Cycles


Example Cycles/Length...

Example Src Dst Cycles Length

add R5,R8 Rn Rm 1 1

add @R5,R6 @Rn Rm 2 1

mov @R5+,R0 @Rn+ PC 3 1

add R5,4(R6) Rn x(Rm) 4 2

add R8,EDE Rn EDE 4 2

add R5,&EDE Rn &EDE 4 2

add #100,TAB(R8) #n x(Rm) 5 3

add &TONI,&EDE &TONI &EDE 6 3

add #1,&EDE #1 &EDE 4 2



Quiz 5.4

How many cyclesfor each instruction?

;*******************************************************************************; CS/ECEn 124 Lab 3 - blinky.asm;*******************************************************************************; cycles = ---; MCLK = --- cycles / 10 seconds = --- Mhz; CPI = MCLK / ---; MIPS = MCLK / CPI / 1000000 = --- MIPS

.cdecls C,LIST, "msp430.h" ; MSP430COUNT .equ 0 ; delay count;------------------------------------------------------------------------------ .text ; beginning of executable code;------------------------------------------------------------------------------RESET: mov.w #0x0280,SP ; init stack pointer mov.w #0x5a80,&0x0120 ; stop WDT (WDTCTL) bis.b #0x01,&0x0022 ; set P1.0 as output (P1DIR)

mainloop: xor.b #0x01,&0x0021 ; toggle P1.0 (P1OUT) mov.w #COUNT,r15 ; use R15 as delay counter


;------------------------------------------------------------------------------; Interrupt Vectors;------------------------------------------------------------------------------ .sect ".reset" ; MSP430 RESET Vector .word RESET ; start address .end



Quiz 5.4 (solution)

How many cyclesfor each instruction?

;*******************************************************************************; CS/ECEn 124 Lab 3 - blinky.asm;*******************************************************************************; cycles = ---; MCLK = --- cycles / 10 seconds = --- Mhz; CPI = MCLK / ---; MIPS = MCLK / CPI / 1000000 = --- MIPS

.cdecls C,LIST, "msp430.h" ; MSP430COUNT .equ 0 ; delay count;------------------------------------------------------------------------------ .text ; beginning of executable code;------------------------------------------------------------------------------RESET: mov.w #0x0280,SP ; init stack pointer mov.w #0x5a80,&0x0120 ; stop WDT (WDTCTL) bis.b #0x01,&0x0022 ; set P1.0 as output (P1DIR)

mainloop: xor.b #0x01,&0x0021 ; toggle P1.0 (P1OUT) mov.w #COUNT,r15 ; use R15 as delay counter


;------------------------------------------------------------------------------; Interrupt Vectors;------------------------------------------------------------------------------ .sect ".reset" ; MSP430 RESET Vector .word RESET ; start address .end

254

41

122



Quiz 5.5

Given a 1.2 MHz processor, what value for DELAY would result in a 1/4 second delay?

DELAY .equ ???

mov.w #DELAY,r12 ;

delay1: mov.w #1000,r15 ;

delay2: sub.w #1,r15 ; jne delay2 ; sub.w #1,r12 ; jne delay1 ;



Quiz 5.5 (solution)

Given a 1.2 MHz processor, what value for DELAY would result in a 1/4 second delay?

DELAY .equ ???

mov.w #DELAY,r12 ; 2 cycles

delay1: mov.w #1000,r15 ; 2 cycles

delay2: sub.w #1,r15 ; 1 cycle jne delay2 ; 2 cycles sub.w #1,r12 ; 1 cycle jne delay1 ; 2 cycles

2 + DELAY (2 + 3000 + 1 + 2)3000

1 second = 1,200,000 cycles0.25 seconds = 1,200,000 / 4 = 300,000 cycles

300,000 cycles = 2 + (DELAY x 3005) cycles

300000 – 2DELAY = ---------- 3005 = 99.833 = 100


Disassembling Instructions


How to Disassemble MSP430 Code

1. Begin with a “PC” pointing to the first word in program memory.

2. Retrieve instruction word and increment PC by 2.3. Find and list the corresponding instruction mnemonic

using the opcode (most significant 4-9 bits).4. Append “.b” or “.w” using the b/w bit (0=word, 1=byte).5. If double operand instruction, decode and list source

operand (Table 5).6. If single or double operand instruction, decode and list

destination operand (Tables 3 and 5).7. If jump instruction, sign extend the 10-bit PC offset,

multiply by 2, and add to the current PC. List that address.

Instruction Disassembly


R0

BYU CS/ECEn 124

How to Disassemble MSP430 Code

1. Begin with a “PC” pointing to the first word in program memory.2. Retrieve instruction word and increment PC by 2.


0xf800: 40310xf802: 02800xf804: 40b20xf806: 5a800xf808: 01200xf80a: d3d20xf80c: 00220xf80e: e3d20xf810: 00210xf812: 430f0xf814: 831f0xf816: 23fe0xf818: 3ffa

0100 0000 0011 0001

R0


0100 0000 0011 0001

BYU CS/ECEn 124

How to Disassemble MSP430 CodeInstruction Disassembly


R0mov

3. Find and list the corresponding instruction mnemonic using the opcode (most significant 4-9 bits).

4. Append “.b” or “.w” using the b/w bit when appropriate (0=w, 1=b).

.wmov


0100 0000 0011 0001

BYU CS/ECEn 124



R0movmov.w

5. If double operand instruction, decode and list source operand.

0x0280#

R0



R0

0100 0000 0011 0001

BYU CS/ECEn 124



movmov.w 0x0280


6. If single or double operand instruction, decode and list destination operand.

,r1#


R0

0100 0000 0011 0001

BYU CS/ECEn 124



movmov.w 0x0280,r1

Repeat process for next instruction.

0100 0000 1011 0010

#


Addressing ModesInstruction Disassembly

Address Mode As Registers Syntax Operation

Register 00 R0-R2, R4-R15 Rn Register Contents.

0 00 R3 #0 0 Constant source / bit bucket destination

Symbolic 01 R0 ADDR (PC+next word) points to operand. (X(PC))

Indexed 01 R1, R4-R15 X(Rn) (Rn+X) points to operand. X is next code word.

Absolute 01 R2 &ADDR Next code word is the absolute address. (X(SR))

+1 01 R3 #1 +1 Constant

Indirect 10 R0-R1,R4-R15 @Rn Rn points to operand.

+4 10 R2 #4 +4 Constant

+2 10 R3 #2 +2 Constant

Immediate 11 R0 #N Next word is the constant N. (@PC+)

Indirect auto-inc 11 R1,R4-R15 @Rn+ Rn points to operand, Rn is incremented (1 or 2).

+8 11 R2 #8 +8 Constant

-1 11 R3 #-1 -1 Constant

So

urc

eD

esti

nat

ion

Address Mode Ad Registers Syntax Operation

Register 0 R0-R2, R4-R15 Rn Register Contents.

Symbolic 1 R0 ADDR (PC+next word) points to operand. (X(PC))

Indexed 1 R1, R4-R15 X(Rn) (Rn+X) points to operand. X is next code word.

Absolute 1 R2 &ADDR Next code word is the absolute address. (X(SR))

- - R3 - Undefined


Quiz 5.6

Disassemble the following MSP430 instructions:Address Data0x8010: 40310x8012: 06000x8014: 40B20x8016: 5A1E0x8018: 01200x801a: 430E0x801c: 535E0x801e: F07E0x8020: 000F0x8022: 12300x8024: 000E0x8026: 83910x8028: 00000x802a: 23FD0x802c: 413F0x802e: 3FF6





mov instruction

0100 0000 0 0 11 0001 mov ,r1.w #0x0600

0=word, 1=byte

SR=PC, indirect, auto-inc mode(immediate)

DR=R1, register mode

Quiz 5.6 (solution)

R0R0R0


0100 0000 1 0 11 0010

BYU CS/ECEn 124



mov instruction

mov ,&0x0120.w #0x5a1e

0=word, 1=byte


DR=R2, indexed register mode(Absolute)

mov.w #0x0600,r10100 0000 0 0 11 0001

Quiz 5.6 (solution)

R0R0R0R0




mov instruction

mov ,r14.w #0

0=word, 1=byte

DR=R14, Register mode

mov.w #0x0600,r10100 0000 0 0 11 0001

mov.w #0x5a1e,&0x01200100 0000 1 0 11 0010

0100 0011 0 0 00 1110

SR=R3, Constant 0

Quiz 5.6 (solution)

R0R0




add instruction

add ,r14.b #1

0=word, 1=byte

DR=R14, Register mode

mov.w #0x0600,r10100 0000 0 0 11 0001

mov.w #0x5a1e,&0x01200100 0000 1 0 11 0010

0101 0011 0 1 01 1110

SR=R3, Constant 1

mov.w #0,r140100 0011 0 0 00 1110

Quiz 5.6 (solution)

R0R0




mov.w #0x0600,r10100 0000 0 0 11 0001

mov.w #0x5a1e,&0x01200100 0000 1 0 11 0010

mov.w #0,r140100 0011 0 0 00 1110

and instruction

1111 0000 0 1 11 1110 and ,r14.b #0x000f

0=word, 1=byte


DR=R1, register mode

add.b #1,r140101 0011 0 1 01 1110

Quiz 5.6 (solution)

R0R0R0


R0

BYU CS/ECEn 124



mov.w #0x0600,r10100 0000 0 0 11 0001

mov.w #0x5a1e,&0x01200100 0000 1 0 11 0010

mov.w #0,r140100 0011 0 0 00 1110

push instruction

0001 00100 0 11 0000 push.w#0x000e

0=word, 1=byteDR=R0, indirect, auto-inc mode

(immediate)

Quiz 5.6 (solution)

R0

1111 0000 0 1 11 1110 and ,r14.b #0x000fadd.b #1,r140101 0011 0 1 01 1110

R0


R0

BYU CS/ECEn 124



mov.w #0x0600,r10100 0000 0 0 11 0001

mov.w #0x5a1e,&0x01200100 0000 1 0 11 0010

mov.w #0,r140100 0011 0 0 00 1110

0001 00100 0 11 0000 push.w#0x000e

Quiz 5.6 (solution)

R0

1111 0000 0 1 11 1110 and ,r14.b #0x000fadd.b #1,r140101 0011 0 1 01 1110

R0

1000 0011 1 0 01 0001

sub instruction

sub ,0(r1).w #1

0=word, 1=byteSR=R3, Constant 1DR=R1, indexed register mode




mov.w #0x0600,r10100 0000 0 0 11 0001

mov.w #0x5a1e,&0x01200100 0000 1 0 11 0010

mov.w #0,r140100 0011 0 0 00 1110

0001 00100 0 11 0000 push.w#0x000e

Quiz 5.6 (solution)

R0

1111 0000 0 1 11 1110 and ,r14.b #0x000fadd.b #1,r140101 0011 0 1 01 1110

R0

1000 0011 1 0 01 0001 sub ,0(r1).w #1

0010 00 1111111101 jne

jne instruction

0x8026

(-3 x 2) + 0x802c


Quiz 5.6 (solution)


mov.w #0x0600,r1

mov.w #0x5a1e,&0x0120

mov.w #0,r14add.b #1,r14and.b #0x0f,r14

push #0x000e

sub.w #1,0(r1)

jne 0x8026mov.w @r1+,r15

0100 0000 0 0 11 0001

0100 0000 1 0 11 0010

0100 0011 0 0 00 11100101 0011 0 1 01 11101111 0000 0 1 11 1110

000100100 0 11 0000

1000 0011 1 0 01 0001

001000 11111111010100 0001 0 0 11 1111


chapter 05 - msp430 isa

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