Chameleon Chip

Submitted by:

Name:Manoj kumar Mahalik

Reg. No.:0601106119

Branch:Information Technology

Agenda1.Introduction2.Multifunction Implementation3.Architecture 4.Embedded Processor System5.Reconfigurable Processing Fabric6.Programmable I/O7.Technologies Used In Chip8.Design Process9.Comparison With Other Technologies10.Advantages11.Disadvantages12.Applications13.Conclusion

Prelude

Advantages:•very high performance and efficientDisadvantages:•not flexible (can’t be altered after fabrication)• expensive

Hardware(Application Specific Integrated Circuits)

Software-programmed processors

Advantages:•software is very flexible to changeDisadvantages:•performance can suffer if clock is not fast•fixed instruction set by hardware

Chameleon computing

Advantages:•fills the gap between hardware and software •much higher performance than software•higher level of flexibility than hardware

A chameleon processor is a reconfigurable microprocessor with erasable hardware that can rewire itself dynamically.

This allows the chip to adapt effectively to the programming tasks demanded by the particular software they are interfacing with at any given time.

Reconfigurable processor usually contains several parallel processing computational units known as functional blocks.

While reconfiguring the chip, the connections inside the functional blocks and the connections in between the functional blocks are changing,

that means when a particular software is loaded the present hardware design is erased and a new hardware design is generated by making a particular number of connections active while making others idle.

1.Introduction

This will define the optimum hardware configuration for that particular software.

It takes just 20 microseconds to reconfigure the entire processing array.

Reconfigurable processors are currently available from Chameleon Systems, Billions of Operations (BOPS), and PACT (Parallel Array Computing Technology).

Among those only Chameleon is providing a design environment, which allows customers to convert their algorithms to hardware configuration by themselves. 

2.Multifunction ImplementationIn a conventional ASIC or FPGA, multiple algorithms are implemented as separate hardware modules. Four algorithms would divide the chip into four functional areas.

With Reconfigurable Technology, the four algorithms are loaded into the entire reconfigurable Fabric one at a time.

So finally the result is: much higher performance, lower cost and lower power consumption

Machine design supposes that some pins are considered as the configuration inputs and another as data or control inputs and outputs.

A new chip must inside determine the set of the function blocks (FB), which are used to construct the circuit, rules of their interconnections and ways of the input/output connections.

The most important parts are the logic circuits, which configure function blocks according to data in the configuration memory.

The various possible connections between functional blocks are encoded to bits known as Configuration bits. Resulting configuration stream is downloaded into configuration memory through configuration inputs.

Thus, a new Reconfigurable machine is established.

3. Architecture

4.Embedded Processor Systemtem

32-bit ARC Processor

32-bit PCI Controller

64-bit Memory Controller

DMA Subsystem

Configuration Subsystem

5.Reconfigurable Processing Fabric(RPF)

The Fabric provides unmatched algorithmic computation power to Chameleon Chip. It consists of 84,32-bit Data path Units and 24, 16×24-bit Multipliers,Operating at 125Mhz, they provide up to 3,000 16-bit Million Multiply-Accumulates Per Second and 24,000 16-bit Million Operations Per Second.

The fabric is divided into Slices, the basic unit of reconfiguration.

The CS2112 has 4 Slices with 3 Tiles in each. Each tile can be reconfigured at runtime Tiles contain :

Datapath Units Local Store Memories 16x24 multipliers Control Logic Unit

Continued….

The high-performance 32bit Data path Unit (DPU): The Tile includes seven Data path Units. The DPU is a data processing module that directly supports all C and Verilog operations.

Data Path Unit(DPU))

6.Programmable I/ORCP includes banks of Programmable I/O (PIO) pins which provide tremendous bandwidth.

Each PIO bank of 40 PIO pins delivers 0.5 GBytes/sec I/O bandwidth.

7.Technologies Used In Chip

1. eCONFIGURABLE™ TECHNOLOGY:

eConfigurable™ Technology is used for instantaneous reconfiguration.

With eConfigurable Technology; the four algorithms are loaded into the entire reconfigurable processing Fabric one at a time.

2. C~SIDE Development Tools :

With this software development tool,Chameleon Systems are providing the ability for the customers to do the programming themselves thus keeping the secrecy of their algorithms. The Chameleon Systems Integrated Development Environment (C~SIDE) is a complete toolkit for designing, debugging and verifying RCP designs. C~Side uses a combined C language and Verilog flow to map algorithms into the chip’s reconfigurable processing fabric (RPF).

3. eBIOS: 

It provides a interface between the Embedded Processor System and the Fabric.

eBIOS provides resource allocation, configuration management and DMA services.

The eBIOS calls are automatically generated at compile time, but can be edited for precise control of any function. 

8.Design Process

9.Comparison With Other Technologies

Today’s system architects have at their disposal an arsenal of highly integrated, high-performance semiconductor technologies, such as application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), digital signal processors (DSPs), and field-programmable gate arrays (FPGAs). However, system architects continue to struggle with the requirement that communication systems deliver both performance and flexibility.

Enter the reconfigurable processor, an entirely new category of semiconductor solution that serves as a system-level platform for a broad range of applications.

10.Advantages

Early and fast design

Reducing development cost

Can more quickly adapt to new requirements and standards

Increasing bandwidth

Reducing power

Reducing manufacturing cost.

11.Disadvantages

Inertia – Engineers slow to change .Inertia is the worst problem facing reconfigurable computing

 RCP designs requires comprehensive set of tools

'Learning curve' for designers unfamiliar with reconfigurable logic 

12.ApplicationsWireless Base stations 

Wireless Local Loop (WLL) 

High-Performance DSL (Digital Subscriber Line Technology) 

Software-Defined Radio (SDR) 

13.Conclusion

These new chips called chameleon chips are able to rewire themselves on the fly to create the exact hardware needed to run a piece of software at the utmost speed.

They will reduce the prices of the gadgets of the information age.