PROJECT REPORT

ON

IMPLEMENTATION OF BUILT IN SELF TEST FOR TESTING

COMBINATIONAL CIRCUITS USING FPGA

Submitted in partial fulfillment of the requirement for the award of the Degree of

Bachelor of TechnologyIn

ELECTRONICS AND COMMUNICATION ENGINEERING

By

A.MANIKANTA (11621A0401)

B.PRABHU KIRAN (11621A0407)

S.NIKHIL (11621A0451)

Under the esteemed guidance of

Mr. A.SAI PRASAD GOUD

Asst. Professor

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

Aurora's Engineering College

(Affiliated to JNTU, Hyderabad)Bhuvanagiri, Nalgonda District – 508 116

i

(2014-2015)

Aurora's Engineering College(Affiliated to JNTU, Hyderabad)

Bhuvanagiri, Nalgonda District – 508 116

CERTIFICATE

This is to certify that the project report entitled “IMLEMENTATION OF BUILT IN SELF

TEST FOR TESTING COMBINATIONAL CIRCUITS USING FPGA” is being

submitted by A.MANIKANTA (11621A0401), B.PRABHU KIRAN (11621A0407) and

S.NIKHIL (11621A0451) in partial fulfillment for the award of the Degree of Bachelor of

Technology in Electronics and Communication Engineering to the Jawaharlal Nehru

Technological University is a record of bonafide work carried out by them under my

guidance and supervision. The results embodied in this major project report have not been

submitted to any other University or Institute for the award of any degree or diploma.

Mr. A.Sai Prasad goud Mr. G.M.Ganesh (Internal Guide) (Coordinator)

Mr. V.Kumara swamy Prof.J.Srikanth (Head of Department) (Principal)

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ACKNOWLEDGEMENT

We wish to take this opportunity to express my deep gratitude to all the people who

have extended their cooperation in various ways in my project work. It is our pleasure to

acknowledge the help of those individuals.

We would like to express deep sense of gratitude to the, Prof.J.SRIKANTH,

Principal Aurora’s Engineering College, Bhuvanagiri, for giving us the opportunity to take

up this project.

We extend our sincere thanks to Mr.V.KUMARA SWAMY Head of Department

of Electronics and Communication Engineering (ECE), Aurora’s Engineering College

Bhuvanagiri, for his encouragement and valuable guidance in bringing shape to this

dissertation.

We express our profound gratitude to our Internal Guide Mr. A.SAI PRASAD

GOUD, Department of ECE, Aurora’s Engineering College Bhuvanagiri, for his support

and encouragement in completing our project .We thank all the members of faculty and our

colleagues of ECE dept, whose appreciation has been a good motivation for us.

Finally we express our sincere thanks and gratitude to our family members and

friends for their magnanimous encouragement and out poring their knowledge and

experience throughout the duration of the project.

A.MANIKANTA (11621A0401)

B.PRABHU KIRAN (11621A0407)

S.NIKHIL (11621A0451)

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ABSTRACT

Accurate diagnosis is an essential requirement in many testing environments, since it is the

Basis for any repair or replacement strategy used for chip or system fault- tolerance.

In this paper we present the first approach able to diagnose faulty programmable logic

Blocks (PLBs) in Field Programmable Gate Arrays (FPGAs) with maximal diagnostic

Resolution. Our approach is based on a new Built- In -Self- Test (BIST) architecture for

FPGAs and can accurately locate any single and most multiple faulty PLBs. An adaptive

Diagnostic strategy provides identification of faulty PLBs with a 7% increase in testing

time over the complete detection test, and can also be used for manufacturing yield

enhancement. We present results showing identification of faulty PLBs in defective ORCA

chips.

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CONTENT

CHAPTER PAGE NO

LIST OF FIGURES viii

LIST OF TABLES xi

CHAPTER 1

INTRODUCTION

1.1 Faults in Integrated Circuits 02

1.1.1 Catastrophic Faults 02

1.1.2 Parametric Faults 03

1.2 Perspectives Reviews on On-Chip Testing Techniques 06

1.2.1 Reasons for On-Chip Testing Compared with Off-chip Testing 06

1.2.2 Comparisons between Digital and Analog On-Chip Testing 07

1.2.3 Comparisons between DFT and BIST Techniques 07

1.3 Existing BIST Techniques for Analog Mixed-Signal LSI 09

1.3.1 BIST Techniques Based on Input Vectors 10

1.3.2 BIST Techniques Based on Test Operation Modes 11

1.3.3 BIST Techniques Based on Domains of Fault Analysis 12

1.4 Dissertation Developments 13

1.4.1 Motivations 13

1.4.2 Research Objectives 13

1.4.3 A Strategy for BIST Architecture 14

1.4.4 Scopes of Research and Contributions 15

1.5 Thesis Organizations 17

CHAPTER 2

LINEAR FEEDBACK SHIFT REGISTERS

2.1 Background on Linear Feedback Shift Registers 19

2.2 How to Create a LFSR Sequence 22

2.2.1 Linear Feedback Shift Registers in Cryptography 27

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2.3 How to Find the Connection Polynomial 31

2.3.1 Recovering the Connection Polynomial from a LFSR Sequence 31

2.3.2 Massey’s Algorithm 31

CHAPTER 3

COMBINATIONAL CIRCUITS

3.1 Different Types Of Modules 40

CHAPTER 4

OUTPUT RESPONSE ANALYZERS

4.1Principle Behind ORA’s 55

4.2 Different Compression Methods 56

4.2.1 Transition Counting 56

4.2.2 Syndrome Testing (Or Ones Counting) 56

4.2.3 Accumulator Compression Testing 56

4.2.4 Parity Check Compression 57

4.2.5 Cyclic Redundancy Check (CRC) 57

4.3 Response Analysis 57

4.4 Multiple Input Signature Registers (Misr) 59

4.5 Masking / Aliasing 64

CHAPTER 5

READ-ONLY MEMORY

5.1 Introduction 67

5.2 How The Device Works 67

5.3 Mask Programmable ROMs 68

5.4 Multimedia Card 72

5.4.1 EPROM 72

5.4.1.1 EPROM Floating Gate Transistor Characteristic Theory 73

5.4.1.2 EPROM Cell Size And Die Size 78

5.4.2 EEPROM 79

5.4.2.1 Parallel EEPROM 80

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5.4.2.2 Serial EEPROM 80

5.4.2.3 Multi-Level Analog Storage EEPROM 86

CHAPTER 6

SIMULATION RESULTS AND RTL SCHEMATIC DIAGRAMS

6.1 Linear Feedback Shift Register 87

6.1.1 Rtl Schematic Diagram 87

6.1.2 Simulation Results of Lfsr 87

6.2 Circuit Under Test 89

6.2.1 Circuit under Test Rtl Schematic 89

6.2.2 Simulation Results of Circuit Under Test 89

6.3 Multiple Input Signature Register 90

6.3.1 Rtl Schematic Of Misr 90

6.3.2 Simulation Results of MISR 91

6.4 Read Only Memory (Rom) 92

6.4.1 Rtl Schematic Of Rom 92

6.4.2 Simulation Results Of Rom 93

6.5 Top Module (Bist) 93

6.5.1 Rtl Schematic Of Top Module 93

6.5.2 Simulation Results Of Bist 95

CHAPTER – 7

CONCLUSION & FURUTE SCOPE

6.1 Conclusion 98

6.2 Future Scope 98

BIBLIOGRAPHY 100

APPENDIX A: ABOUT SOFTWARE TOOL 101

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LIST OF FIGURES

FIGURE NO NAME OF THE FIGURE PAGE NO

1.1 Examples Of Bridging Defects And Gate-Oxide Shorts 04

1.2 Examples Of Opens Caused By Foreign And

Contaminating Particles

05

1.3 Probability Of Faulty And Faulty Free Distribution By

Parameter Variation

06

1.4 A Generalized Block Diagram Of Bist Architecture 08

1.5 Classification Diagrams Of Bist Techniques 09

1.6 Architectures Of Classical And Recent Bist Test

Strategies

14

1.7 Block Diagram Of Dissertation 17

2.1 Examples Of Lfsrs 20

2.2 White Noise Machine 21

2.3 Figures 4&5 Are The Models Of Lfsrs 23

2.4 1-Bit Lfsr Diagram 23

2.5 Minimal Lfsr With C(X)=1+X+X4 And L=4 38

3.1 Block Diagram 39

3.2 Block Diagram Of Half Adder 40

3.3 Circuit Diagram Of Half Adder 40

3.4 Block Diagram Of Full Adder 41

3.5 Circuit Diagram Of Full Adder 42

3.6 Block Diagram Of 4 Bit Parallel Adder 43

3.7 Block Diagram 4 Bit Parallel Subtractor 44

3.8 Circuit Diagram Of Half Subtractor 45

3.9 Circuit Diagram Of Full Subtractor 46

3.10 Block Diagram Of Multiplexer 47

3.11 Block Diagram Of De-Mux 49

3.12 Block Diagram Of Decoder 49

3.13 Block Diagram Of 2to4 Line Decoder 50

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3.14 Circuit Diagram Of 2 T0 4 Line Decoder 51

3.15 Block Diagram Of Encoder 52

3.16 Block Diagram Priority Encoder 53

3.17 Circuit Diagram Of Priority Encoder 54

4.1 Example Of Fault Detection And Signature Aliasing 58

4.2 3bit Misr Circuit Diagram 59

4.3 Misr With Scan Generator 61

4.4 4-Bit Misr Block Diagram 62

4.5 Misr Function Diagram 63

5.1 Read Only Memory Schematic 68

5.2 ROM Programmed By Channel Implant 70

5.3 Memory Cell Schematic 71

5.4

5.5

Double-Poly Structures (EPROM/Flash Memory Cell

Cross Section Of A Conventional Mos Transistor And A

Floating-Gate Mos Transistor

72

74

5.6 Nor EPROM Configuration 77

5.7 Typical 1mbit EPROM Cells 78

5.8 EPROM Feature Sizes 79

5.9 Xircom 1mbit EEPROM Cell 82

5.10 Hitachi 1mbit EEPROM Cell 83

5.11 Xicor 128kbit Serial EEPROM Functional Diagram 84

5.12 Sgs-Thomson 1kbit Serial EEPROM 85

5.13 Microchip 16kbit Serial EEPROM Cell 86

6.1 RTL Schematic Of LFSR 87

6.2 Lfsr Simulation Results 88

6.3 Rtl Schematic Of Circuit Under Test 89

6.4 Simulation Result Of Circuit Under Test 90

6.5 Rtl Schematic Of MISR 91

6.6 Simulation Results Of MISR Block 92

6.7 Rtl Schematic Of Rom 92

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6.8 Simulation Result Of Rom 93

6.9 Rtl Schematic Of Bist 94

6.10 Expanded Rtl Schematic Of Bist 94

6.11 Simulation Results Of Top Module Or Bist 97

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LIST OF TABLES

TABLE NO NAME OF THE TABLE PAGE NO

3.1 Truth Table Of Half Adder 40

3.2 Truth Table Of Full Adder 41

3.3 Truth Table Of Half Subtractor 45

3.4 Truth Table Of Full Subtractor 46

3.5 Truth Table Of Mux 48

3.6 Truth Table Of 2to4 Line Decoder 51

3.7 Truth Table Of Priority Encoder 53

3.8 Truth Table Of Encoder 54

4.1 Multiplier Test Pattern 61

5.1 EPROM Feature Sizes 79

5.2 1mbit Parallel EEPROM Feature Sizes 81

5.3 EEPROM Serial Configuration Feature Sizes 84

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