CEC 220 Digital Circuit DesignIntroduction to VHDL

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Lecture Outline

Friday, February 21 CEC 220 Digital Circuit Design

• Introduction to VHDL

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Introduction to VHDL

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• Large digital systems are unwieldy to design manually E.g. design a H.264 video transcoder

• Hardware Description Languages (HDL) allow for design automation Design Simulation Synthesis Verification

RTL: Register Transfer Level

ESL: Electronic Sys Level

Introduction to VHDLVHDL Description of Combinational Logic Circuits

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• Basic example

E <= D or (A and B);

Signal_Name <= Expression;

Behavioral Description

Introduction to VHDLVHDL Description of Combinational Logic Circuits

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• Basic example

Assignment operator

Concurrent statements

Evaluated anytime variables changes

If a delay time is not specified then the default is used

Dataflow Description

Introduction to VHDLVHDL Description of Combinational Logic Circuits

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• A Second Example:

CLK <= not CLK after 10 ns;

A concurrent statement

Introduction to VHDLVHDL Description of Combinational Logic Circuits

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• Consequences of a concurrent statement

Introduction to VHDLVHDL Description of Combinational Logic Circuits

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• VHDL Syntax: Signal names and other VHDL identifiers may contain

letters, numbers, and the underscore character (_). An identifier must start with a letter, and it cannot end with

an underscore. VHDL is mostly case insensitive. Thus, C123 and ab_23 are legal identifiers, but 1ABC and

ABC_ are not. Every VHDL statement must be terminated with a

semicolon. White space is ignored. In VHDL double dash (--) precedes a comment. Words such as and, or, and after are reserved words with

special meanings.

Introduction to VHDLVHDL Description of Combinational Logic Circuits

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• VHDL Operators: Binary Logical Operators: and, or, nand, nor, xor, xnor Relational Operators: =, /=, <, <=, >, >= Shift Operators: sll, srl, sla, sra, rol, ror Arithmetic Operators: +, -, &, *, /, mod, rem

concatenation

Introduction to VHDLVHDL Description of Combinational Logic Circuits

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• Vector Operations

Introduction to VHDLVHDL Description of Combinational Logic Circuits

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• VHDL Models for Multiplexers

sel <= A & B; -- select signalwith sel select F <= I0 when “00”, I1 when “01”, I2 when “10”, I3 when “11”;

F <= I0 when (A = ‘0’) else I1;

Conditional assignment Selective assignment

Introduction to VHDLVHDL Description of Combinational Logic Circuits

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• Examples: Implement the following VHDL conditional statement using

two 2:1 MUXs: o F <= A when D=‘1’ else (B when E = ‘1’ else C);

Given that A <= “01101” and B <= “11100”, what is the value of:o F<= (not B & ‘1’ or A & ‘1’) and ‘1’ & A;

Introduction to VHDLVHDL Description of Combinational Logic Circuits

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• Examples: Draw the circuit represented by the following VHDL

statements: o F<= not A and not B and I0;

G<=not A and B and I1;

Write the VHDL statements for 2-input NAND gates with 4-ns delays to implement a function

Next Lecture

Friday, February 21 CEC 220 Digital Circuit Design

• More VHDL Entity, architecture, modules, arrays, …

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