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CC2538 System-on-Chip Solution for 2.4-GHzIEEE 802.15.4 and ZigBee/ZigBee IPApplicationsTexas Instruments CC2538 Family of ProductsVersion C

User's Guide

Literature Number: SWRU319CApril 2012Revised May 2013

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Contents

Preface ...................................................................................................................................... 261 Architectural Overview ....................................................................................................... 32

1.1 Target Applications ........................................................................................................ 331.2 Overview .................................................................................................................... 331.3 Functional Overview ...................................................................................................... 36

1.3.1 ARM Cortex-M3 ................................................................................................... 361.3.1.1 Processor Core ............................................................................................. 361.3.1.2 Memory Map ................................................................................................ 361.3.1.3 System Timer (SysTick) ................................................................................... 361.3.1.4 Nested Vector Interrupt Controller ....................................................................... 371.3.1.5 System Control Block ...................................................................................... 371.3.1.6 MPU .......................................................................................................... 37

1.3.2 On-Chip Memory ................................................................................................. 371.3.2.1 SRAM ........................................................................................................ 371.3.2.2 Flash Memory ............................................................................................... 371.3.2.3 ROM ......................................................................................................... 38

1.3.3 Radio ............................................................................................................... 381.3.4 AES Engine with 128, 192 256 Bit Key Support ............................................................. 381.3.5 Programmable Timers ........................................................................................... 38

1.3.5.1 MAC Timer .................................................................................................. 391.3.5.2 Watchdog Timer ............................................................................................ 391.3.5.3 Sleep Timer ................................................................................................. 391.3.5.4 CCP Pins .................................................................................................... 39

1.3.6 Direct Memory Access ........................................................................................... 391.3.7 System Control and Clock ....................................................................................... 401.3.8 Serial Communications Peripherals ............................................................................ 41

1.3.8.1 USB .......................................................................................................... 411.3.8.2 UART ........................................................................................................ 411.3.8.3 I2C ............................................................................................................ 421.3.8.4 SSI ........................................................................................................... 43

1.3.9 Programmable GPIOs ........................................................................................... 431.3.10 Analog ............................................................................................................ 43

1.3.10.1 ADC .......................................................................................................... 441.3.10.2 Analog Comparator ........................................................................................ 441.3.10.3 Random Number Generator .............................................................................. 44

1.3.11 cJTAG, JTAG and SWO ........................................................................................ 441.3.12 Packaging and Temperature ................................................................................... 44

2 The Cortex-M3 Processor ................................................................................................... 452.1 The Cortex-M3 Processor Introduction ................................................................................. 462.2 Block Diagram ............................................................................................................. 462.3 Overview .................................................................................................................... 47

2.3.1 System-Level Interface .......................................................................................... 472.3.2 Integrated Configurable Debug ................................................................................. 472.3.3 Trace Port Interface Unit ........................................................................................ 48

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2.3.4 Cortex-M3 System Component Details ........................................................................ 482.4 Programming Model ....................................................................................................... 48

2.4.1 Processor Mode and Privilege Levels for Software Execution ............................................. 492.4.2 Stacks .............................................................................................................. 492.4.3 Register Map ...................................................................................................... 492.4.4 Register Descriptions ............................................................................................ 512.4.5 Exceptions and Interrupts ....................................................................................... 612.4.6 Data Types ........................................................................................................ 61

2.5 Instruction Set Summary ................................................................................................. 613 Cortex-M3 Peripherals ..................................................................................................... 65

3.1 Cortex-M3 Peripherals Introduction .................................................................................. 663.2 Functional Description .................................................................................................... 66

3.2.1 SysTick ............................................................................................................. 663.2.2 NVIC ................................................................................................................ 67

3.2.2.1 Level-Sensitive and Pulse Interrupts .................................................................... 673.2.2.2 Hardware and Software Control of Interrupts .......................................................... 67

3.2.3 SCB ................................................................................................................ 683.2.4 MPU ................................................................................................................ 68

3.2.4.1 Updating an MPU Region ................................................................................. 693.2.4.1.1 Updating an MPU Region Using Separate Words ................................................ 693.2.4.1.2 Updating an MPU Region Using Multiple-Word Writes ........................................... 703.2.4.1.3 Subregions .............................................................................................. 70

3.2.4.2 MPU Access Permission Attributes ...............................................................