Build-In Self-Test of FPGA Build-In Self-Test of FPGA Interconnect Delay FaultsInterconnect Delay Faults

Laboratory for Reliable Computing (LaRC)

Electrical Engineering Department

National Tsing Hua University

Adviser: Prof. Cheng-Wen Wu

Student: Chun-Chieh Wang

May 13, 2004

2

OutlineOutline Introduction

Island-style FPGA Architecture

Previous Work

The Proposed Method

Experimental Results

Conclusions and Future Work

3

Introduction (1/2)Introduction (1/2) Field programmable gate arrays (FPGAs) have

been wildly used. Rapid prototyping and functional verification Reconfigurable platform for many applications

Today’s FPGA 250,000 to millions equivalent gates At higher speed beyond 100 MHz

FPGA could provide user-defined function in a system by its reconfigurable feature.

4

Introduction (2/2)Introduction (2/2) FPGA delay-fault testing is becoming more

important. Many users implement more circuits operating at

high speed in FPGA. VDSM processes have resulted in more defects

affecting the delays in the circuit.

The BIST is the trend of FPGA delay-fault testing. At speed testing Without require expensive ATE

5

FPGA Architecture ClassificationFPGA Architecture Classification Island-style

Xilinx Virtex ,Altera 8K …Ⅱ

Hierarchy-style

Xilinx XC6200, Prof. Huang’s FPGA …CLB

CLB

CLB

CLB

6

Island-style FPGAIsland-style FPGA CLB

Configurable Logic Block

Interconnect Global and local

Interconnect Wire Segments and CIPs

(Configurable Interconnect Points)

I/O Block

IOB IOB

IOB IOBIO

BIO

B

IOB

IOB

Figure 1: Island-style FPGA Architecture

CLB CLB

CLB CLB

7

Configurable Interconnect PointConfigurable Interconnect Point

B

ConfigurationMemory Bit

A B

(d) MUX CIP (e) compound CIP

(a) basic structure

A B

Figure 2: Configurable Interconnect Points

A

A B

(c) break-point CIP

(b) cross-point CIP

8

Switch MatrixSwitch Matrix

Compound CIP

Figure 3: Switch Matrix

9

Hierarchical Routing ResourcesHierarchical Routing Resources

CLBCLBCLBCLB

(d) Direct Connection

(c) Double Line

(b) Single Line

(a) Long Line

CLBCLBCLBCLB

CLB CLBCLBCLB CLB CLB CLBCLB

10

FPGA Manufacturing TestingFPGA Manufacturing Testing Application-independent

FPGA test classification CLB Test Interconnect Test

Approximately 80% of the transistors in an FPGA are dedicated to the routing resources.

CLB Test Interconnect Test

11

Fault Models of CLB TestFault Models of CLB Test LUT: stuck-at faults in memory

Multiplexer: functional faults (stuck-on/stuck-off)

D flip-flop: functional faults

Input/Output lines: stuck-at faults

LUT

LUT

LUT

Q

QSET

CLR

D

Q

QSET

CLR

D

Xilinx Spartan Series CLB

12

Fault Models of Interconnect TestFault Models of Interconnect Test CIPs: stuck-close (stuck-on) and stuck-open

(stuck-off)

Wires stuck at 0/1, open wire, and shorted wires

Detecting the CIPs faults also detects stuck-at faults in configuration memory bits that control the CIPs

Compound CIP

Figure 3: Switch Matrix

13

Logic BIST ArchitectureLogic BIST Architecture

Pass/Fail

TPG #1 TPG #2

BIST Start

BUT BUT BUT…

BUT BUT BUT…

ORA ORA ORA…

Row of TPGsRow of BUTs

Row of BUTs

Row of BUTs

Row of BUTs

Row of ORAs

Row of ORAs

Row of ORAs

Test Session #1

Row of BUTs

Row of ORAs

Row of ORAs

Row of ORAs

Row of TPGs

Row of BUTs

Row of BUTs

Row of BUTs

Test Session #2

TPG : Test Pattern GeneratorORA : Output Response AnalyzerBUT : Block Under Test

source: VTS 96 “Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!)

14

Interconnect BIST Architecture (1/2)Interconnect BIST Architecture (1/2)

source: ITC1998 ” Built-in self-test of FPGA interconnect “

TPG ORA

Start

Done P/F

WUTs

WUTs

1

1

1

1

0

0 0

0

1

1

15

Interconnect BIST Architecture (2/2)Interconnect BIST Architecture (2/2)

source:ITC2000 “Novel technique for built-in self-test of FPGA interconnects”

P/FTPG

Parity Code

GeneratorWUTs k

WUTs_Parity

ORA

A parity checker

16

Oscillator-Loop MethodOscillator-Loop Method The first BIST-based delay-fault testing approach for

FPGAs.

source:2002 IEEE Int’l On-Line Testing Workshop “BIST-Based Delay-Fault Testing in FPGAs”

I PUTs FIRST

LAST

OSC

CounterI

FIRST

LAST

OSC

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The traditional path delay fault model is not practicable for FPGA manufacturing testing since it is application-independent.

Single-Line-Segment delay fault model

At speed testing

BIST approach

The comparison-based BIST architecture only could detect the maximum difference between PUTs.

Compare with the clock

FPGA Delay-Fault Testing Issue FPGA Delay-Fault Testing Issue

18

Single-Line-Segment Delay Fault ModelSingle-Line-Segment Delay Fault Model Single-line-segment delay fault

The delay of a line segment is large enough to cause some paths covering this line segment exceeds some specified duration. ~ ylpeng ‘s thesis

The total number of faults = The total number of segments.

CLB CLB

19

Slack vs. Fault SizeSlack vs. Fault Size PUT has different ability to detect fault due to the different

length of PUT .

For getting the best detectability, we should make PUT as short as possible.

A B C10 10 10

TPUT_spec

A B C10 7.5 7.5

Slack=5

TPUT_actual

TPUT_actual+TFault_Size on A segment

A B CFaultTFault_Size on A segment = 5

time

10

A Fault B C

5 7.5 7.5

10 10 7.5 7.5

PASS Fail

20

The Basic Idea and Implement Issue The Basic Idea and Implement Issue The clock skew effect should be considered and be tested

before our test.

F.F.2F.F.1

BA

CLK

PUT

Figure 4: A Simple Case of Delay-fault Testing

QD QD

CLKT

PUT_actualT

clock skewT

Figure 5: Clock Skew Effect

T CLK

21

Q

QSET

CLR

D

1

Start

Q

QSET

CLR

D

1

EC

D1 Q1

D2 Q2

ECMode_Select

0

PUT

11stst BIST Circuit (Rising Transition) BIST Circuit (Rising Transition)

Assumption :

1.TQ1→D2 < TQ1→D1

2.TQ2→EC < TQ1→D1

3.Ignore the clock skew between two F.F.s

The logical value of Q1

Normal 1 → 0 → 1

Faulty 1 → 0 → 0

0 → 1

1 → 0 → 1 → 0

1→ 0 → 1

1 → 0 → 1

1 → 1 → 0

22

Q

QSET

CLR

D

0

Start

Q

QSET

CLR

D

1

EC

D1 Q1

D2 Q2

ECMode_Select

1

PUT

11stst BIST Circuit (Falling Transition) BIST Circuit (Falling Transition)

Assumption :

1.TQ1→D2 < TQ1→D1

2.TQ2→EC < TQ1→D1

3.Ignore the clock skew between two F.F.s

The logical value of Q1

Normal 0 → 1 → 0

Faulty 0 → 1 → 1

0 → 1

0 → 1 → 0 → 1

0 → 1 → 0

1 → 0 → 1

1 → 1 → 0

23

WE & NS Switch Testing IssueWE & NS Switch Testing Issue

After 16 TCs, we have fully tested these components :

All line segments (not involved with IOB)

All NE, WS, WN, and ES switches (not involved with IOB)

CLB CLBWE

24

Consider the Clock Skew in the TestConsider the Clock Skew in the Test

Q

QSET

CLR

D

Q

QSET

CLR

D

CLK1

PUT

CLK2

Tclk

TPUT_SPEC

Tclk with skew effect

T 'clk with skew effect

T 'clk = Tclk + k

Assumption: the spec. of clock skew between 2 adjacent F.F.s < k

25

Clock Skew TestClock Skew Test

Assumption: the spec. of clock skew between 2 adjacent F.F.s < k

TPUT_actual

T 'clk with skew effect

( T 'clk = Tclk + k )

Tslack

… …Undetectable Case

Detectable Case

( Skew > k )

( Skew > k )

CLB CLB

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The 2The 2ndnd BIST Circuit BIST Circuit

The logical value of Q2

Normal 0 → 0 → 1

Faulty 0 → 0 → 0

Q3

Q

QSET

CLR

D

0

Start

Mode_Select

PUT

Q

QSET

CLR

D

0

Q

QSET

CLR

D

1

0

Mode_Select0

0→ 1 → 1 0→ 0 → 1

Q1D1 D2 Q2

D3

27

How to Reduce TCs (1/2)How to Reduce TCs (1/2)

Q

QSET

CLR

D

Start

Q

QSET

CLR

D

EC

D1 Q1

D2 Q2

ECMode_Select

PUT1

PUT2

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How to Reduce TCs (2/2)How to Reduce TCs (2/2)

Q

QSET

CLR

D

Start

Mode_Select

PUT1

Q

QSET

CLR

D

Q

QSET

CLR

D

Mode_Select

PUT2

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Test FlowTest Flow

Generate the TCs for 1st BIST Circuit

Is it possible to reduce more TCs?

FPGA Architecture

Finish

Test the clock skew with the tested

segment

Generate the TCs for 2nd BIST Circuit

Reducing TCs method

Yes

No

Is any PUT too long ?

Reducing TCs method

Is it possible to reduce more TCs? Yes

No

Yes

No

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Experimental ResultsExperimental Results Target Device : Xilinx Spartan Series FPGA

We only consider the single-length line in our experiment.

36 Test Configurations

BIST Type Target Segment (Target Fault) No. of TCs

1 All line segments & NE, WS, WN, and ES switches

16

2 The clock skew between 2 adjacent F.F.s 4

2 All WE, NS switch 16

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Feature Coverage Feature Coverage Feature Coverage : CLB Block Coverage : 100.000% CLB Pin Coverage : 100.000% I/O Pin Coverage : 0.000% Track Coverage : 87.500% Switch Coverage : 86.963% Total Feature Coverage : 87.891%

Effective Feature Coverage for BIST: CLB Block Coverage : 100.000% CLB Pin Coverage : 100.000% Track Coverage : 100.000% Switch Coverage : 100.000% Total Feature Coverage : 100.000%

32

Effective F.C. vs. Fault Size Effective F.C. vs. Fault Size Assumptions

Tsegment_spec is uniform on each segment Tsegment_slack = 10% of Tsegment_spec

0%

20%

40%

60%

80%

100%

0 2 4 6 8 10

Fault Size ( 0.1 unit time)

Eff

ective

Fau

lt C

over

age

sizefaultspecificthetrwSegmentsTotalofThe

SegmentsCoveredofTheCoverageFault ...

#

#

33

Conditional Delay Fault CoverageConditional Delay Fault Coverage

Sample Count: 1KEach Segment Spec: 3.5 nsDefect Count (mean): 1.3Slack over Spec: 10% (.35ns)FPGA Size: 14x14

DefectSize(ns)

Delay Fault Coverage

0.35 97.06%

0.70 97.39%

1.05 99.53%

1.40 99.66%

1.75 98.22%

2.10 99.51%

2.45 99.77%

2.80 100%

3.15 100%

Index

1

2

3

4

5

6

7

8

9

samplestotalofThe

samplesdectectedofTheCoverageFault

#

#

34

Conclusions and Future WorkConclusions and Future Work We proposed a new BIST-based approach to

FPGA interconnect delay-fault testing. It could be easily implemented in the different

FPGA architecture. It is also independent of the end application and

FPGA array size.

The test phase must be developed for a specific CLB and/or interconnect architecture.

Automatic configuration generation for FPGA test is useful and needful.