boosters for driving long on-chip interconnects : design issues, interconnect synthesis and...
TRANSCRIPT
Boosters for Driving Long On-chip Interconnects: Design Issues,
Interconnect Synthesis and Comparison with Repeaters
Ankireddy NalamalpuIntel Corporation/Hillsboro
Wayne BurlesonUMASS/Amherst
Partially Funded by SRC under research ID 766
Motivation
• Interconnect delay will dominate DSM• Limited performance by using traditional techniques
(Repeaters) for driving on-chip interconnects• Repeaters are area and power hungry
• This study aims to provide• New high-performance circuit technique (Booster) for
driving interconnects• Over-all Booster design methodology to integrate into
automatic interconnect synthesis tools• Study/comparison Boosters with Repeaters
Repeater Design
• Classical delay optimal repeater solution when delay of repeaters equals interconnect delay [Bakoglu85]
• Repeater design solutions model short-channel effects in DSM using Alpha Power MOSFET model [Friedman98b, Nalamalpu00b]
Repeater Design Limitations
• Limited performance with Repeaters in DSM due to non-negligible interconnect resistance
• Increasing Repeater Area and Power with technology scaling [Sylvester98, Sylvester99]
• 700,000 repeaters in 70nm CMOS [Cong99]• Increased design problems with repeaters driving bi-directional and multi-source
buses • Inverting Polarity
0
10
20
30
40
50
60
0.25 0.2 0.15 0.1 0.05Technology Generation(m)
Pow
er(W
)
1x106
2x106
3x106
4x106
5x106
6x106
# of
Rep
eat e
rs
Repeaters + Wire
Wires Only
# Rep
eate
rs
[Plot from Sylvester99]
Review of Previous Work
• Regenerative Feed-back Repeaters for driving programmable interconnections[Dobbelaere95]• Extremely sensitive to Noise• Meta-stability• Two-sided Timing Constraints• Limit in performance gain
Driver Driver
Receiver Receiver2,4…Inverters
Interconnect Interconnect
Review of Previous Work
• Differential, Small-swing and other design techniques[Lima95,Friedman98a]• Requires more circuit design sophistication• Cumbersome for automatic interconnect synthesis tools• Require multiple Power Supply’s in some cases
We need simple and yet high-performance circuit technique that can be integrated into automatic interconnect synthesis tools
Proposed Design
• Our proposed circuit (Booster) differs from the existing designs in one or more of the following• High Performance
• Simpler and requires fewer transistors
• Noise immunity
• Eliminates Meta-stability
• We formulate analytical design rules for Boosters to be part of automatic interconnect synthesis tool
Driver
Receiver
Driver
Receiver
Input rin
InterconnectInterconnectbp
tn
Booster Circuit
Skewed Inverters
Driver
Feed-back
bout
fout
N=1.0
N=1.0
P=2.0
P=2.0
N=1.0
P=2.0
Full Keeper
Booster Simulations • RLC 5 T-Interconnect
model in 0.16m CMOS • Feedback path
• Improves the speed of driver
• Prevents turning-off booster prematurely thereby eliminating two-sided timing constraints
• Makes circuit glitch immune
Inverter Outputs
Firing
Feed-back Path
Input
Booster Design
• Skewed inverters respond to opposite ends of voltage transition
• Driving both the inverters to feed-back path improves noise immunity
• Full keeper helps noise cause• Booster firing time depends on switching thresholds
of inverters• Boosters attach to the wire rather than interrupting it
so can be used for bi-directional signals• Boosters don’t impact the polarity of the signal
Booster Design Methodology
• Analytically determine number of boosters and their placements for driving given interconnect load• Consider only delay optimality• Minimize power/area impact without losing
significant speed-up
• Boosters no good for driving very short wires due to fast transients in small RC loads (how short?)
• In-order to place a booster• Firing time < Time Constant
• Booster Transient variation > 2.5, to minimize total number of boosters
Booster Placement
BR1 BR2 BR3
BR1, BR2, BR3 = Boosters
350
300
250
200
150
100
500.5 2.0 3.01.51.0 2.5
Booster Transient Variation
Delay with Booster(ps)
Delay without Booster(ps)
Booster Analytical Model
• Using simple inverter model(which will suffice)
ttt vVVvV ddabpdda
Vdds 3
2
5
2
2
vkC
LL
CLrddn
rr
kwRCRC
Ls
212
1)1ln(
5
22
10
Length = L1
Node(a) Node(b)
Length = L3Length = L2
bp
tn
Booster Analytical Model
• Using more accurate alpha-power law based inverter analytical model [Nalamalpu00b] • Alpha power MOSFET law [Sakurai90] models
short-channel effects• Repeater model is within 5% error of SPICE
vk
LCLRvV
IvvL
ddprd
d
dd
d
ddd wkC
LR
L
bC
L 2
5
3ln 11
000
01
Rule for Number of Boosters
• When boosters(BR1, BR2, BR3) are initially off• L1,L2 and L3 will be different for identical segment delays due to
characteristics of signal propagation along RC line
• Unlike Repeaters, placing non-optimal number of boosters doesn’t impact performance as much as power
Number of Boosters
Interconnect Delay
Short-circuit Power
• To Minimize number of boosters• Any down stream booster (e.g.BR2) should be fired
only after improved upstream signal transient (e.g. A, BR1 is active) propagates downstream (e.g.B)
• L1<L2<L3<L4 for identical segment delays
L1 L2
Rule for Number of BoostersL3 L4
BR1, BR2, BR3, BR4 = Boosters
BR1 BR2 BR3 BR4
Booster Placement Sensitivity
Realistic floor-plans will have several placement constraints• Inter block routing
• Repeater staggering to reduce inductive and capacitive coupling
• To ensure the design is manageable (e.g. verifiable, reusable)
• To maintain datapath’s regularity
Block A Block BBlock C
No Glue Logic
Booster Placement Sensitivity
• Repeaters are shown to be sensitive to placement variation[Nalamalpu00a]• Worst case placement scenario’s results in performance degradation
by as much as 30%
• Boosters relatively insensitive to placement variation due to its dependence on transient
SPICE Simulations
• We used delay optimal repeater design solution obtained by using alpha-power MOSFET model[Nalamalpu00b]
• Booster design rules for finding number of boosters and their placements are used to minimize design cost without losing significant speed (<5%)
• CMOS 0.16 m process is used for SPICE simulations• Interconnect load is represented using RLC 5 T-model
Repeaters
Boosters
SPICE Simulations
CL
(pF)
Rt
(k)
Speed-up (%)
1.0 1.0 2 5 300 360 349 434 19.2
1.25 1.25 2 6 300 432 451 567 20.6
4.0 1.0 4 11 750 1518 688 829 17.0
2.0 5.0 5 17 750 816 933 1287 27.6
20 1.0 9 22 1350 6732 1380 1792 23.1
)( k
)( mDbooster DrepeaterWbooster Wrepeater
nbooster
(m) (m) (ps) (ps)
nrepeater
Boosters Vs Repeaters
• Boosters shown to out-perform Repeaters by 20% for all kinds of interconnect loads (both capacitive and resistive dominated)
• Boosters interconnect driving distance is 3x that of Repeaters resulting in fewer Boosters
• Significant reduction in Area over Repeaters (more than 100% depending on interconnect load)
• Boosters are insensitive to placement variation• Boosters don’t impact the polarity of the signal
Booster Applications
• Uni/bi-directional interconnects
• Multi-source/sink buses
• Programmable Interconnections in FPGA’s
Booster
Booster Booster Booster
On Switches
Off Switches
Booster Applications
Long AND domino gates (e.g decoders)• Precharge from top of
the stack and discharge is from bottom of the stack
• Bi-directional signaling can be improved using boosters
Booster Limitations
• Boosters don’t break lines however for buffering, modularity and signal integrity reasons it is desirable to break long lines
• Boosters are not well understood by CAD tools and designers
Conclusions
• We presented analytical design solutions, both hard optimization and softer realistic design problems
• We propose to combine Boosters with Repeaters in some cases to handle both modularity and signal integrity issues
• Boosters find application in long dynamic ANDs, and multi-source interconnects in addition to conventional point-to-point long lines
Future Work
• Integration into interconnect synthesis tool with Repeaters
• Impact on bi-directional multi-source lines which could directly impact VLIW, FPGA, Routers, multi-processor, memory and other highly connected architectures
Acknowledgements
Sriram Srinivasan for insightful comments Prof. Arnold Rosenberg for the initial
theoretical motivations in exploring booster circuits
SRC for partially supporting under Research ID 766
UMASS has filed for several patents related to Booster technology
References
[Dobbelaere95] Dobbelaere et al , Regenerative Feed-back Repeaters for Programmable Interconnections, JSSC, 1995
[Lima95] T. Lima et al, Capacitance Coupling Immune Accelerator for Resistive Interconnects, IEEE Trans. on Electron Devices, 1995
[Friedman98a] Secareanu et al, Transparent Repeaters, GLSVLSI,1998
[Nalamalpu00a] A. Nalamalpu et al, Quantifying and Mitigating Placement Constraints, 2000
[Sakurai90] Sakurai et al , Alpha-Power MOSFET Model, JSSC,1990
[Nalamalpu00b] A. Nalamalpu et al , Repeater Ramp based Analytical Model, ISCAS,2000
References
[Sylvester98] D.Sylvester et al, Getting to the bottom of deep sub-micron, ICCAD, 1998
[Sylvester99] D.Sylvester et al, Getting to the bottom of deep sub-micron II, ISPD, 1999
[Friedman98b] V.Adler et al, Repeater Design to Reduce Delay and Power, IEEE Trans. Circuits and System II, 1998
[Bakoglu85] Bakoglu et al, Optimal Interconnection Circuits for VLSI, IEEE Trans. Electron Devices, 1985