basic interconnects

8/7/2019 Basic Interconnects

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EE213 VLSI Design Stephen Daniels 2003

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Basic Interconnects

VLSI Design EE213

These slides contain some notes on interconnectionsin VLSI circuits. Full details are in Pucknell andEshraghian pages 94 - 107


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Introduction

Wiring-Up of chip devices takes place through variousconductors produced during processing

Today, interconnects constitute the main source of delay inMOS circuits

We will examine: Sheet Resistance Resistance / Unit Area Area Capacitance Delay Units CMOS Inverter Delay Rise and Fall Time Estimation


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Sheet Resistance Resistance of a square slab of material R AB = L/A => R = L/t*W Let L = W (square slab) => R AB = /t = R s ohm / square

t w L

A

B

R AB = ZR sh

Z = L/W


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Typical sheet resistance values for materialsare very well characterised

Layer Rs (Ohm / SqAluminium 0.03

N Diffusion 10 50

Silicide 2 4

Polysilicon 15 - 100

N-transistor Channel 10 4

P-transistor Channel 2.5 x 10 4

Typical Sheet Resistances for 5m Technology


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Polysilicon

N - diffusion

N-type Minimum Feature Device

R = 1sq x Rs = Rs = 10 4

L

W2

2


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Polysilicon

N - diffusion

L = 2

W = 8

R = Z RsR = (L/W) * RsR = 4 10 4


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Exercise

Calculate the ON resistance for a depletion pull upNmos inverter with Z pu : Z pd ratio 4:1

Use sheet resistance values given in earlier slide


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Area Capacitance of Layers Conducting layers are separated from each

other by insulators (typically SiO2) This may constitute a parallel plate

capacitor, C = 0 ox A / D (farads) D = thickness of oxide, A = area, ox = 4 F/m 2 Area capacitance given in pF/m 2


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Capacitance Standard unit for a technology node is the

gate - channel capacitance of the minimumsized transistor (2 x 2 ), given as Cg

This is a technology specific value


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References Pucknell and Eshraghian pages 94 - 102


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Delay Unit For a feature size square gate, = Rs x Cg i.e for 5m technology, = 10 4 ohm/sq x 0.01pF = 0.1ns Because of effects of parasitics which we have not

considered in our model, delay is typically of the order of 0.2 - 0.3 ns

Note that is very similar to channel transit time sd


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CMOS Inverter Delay Pull-down delay = Rpd x 2 Cg Pull-up delay = Rpu x 2 Cg Asymmetry in rise and fall due to resistance difference

between pull-up and pull-down (factor of 2.5) (due tomobilities of carriers)

Delay through a pair of inverters is 2 (fall time) + 5 (rise time) Delay through a pair of CMOS inverters is therefore 7


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CMOS Inverter Delay Asymmetry can be improved by reducing resistance of pull

- up

Reduce resistance of pull - up by increasing channel width( typically by a factor of 2.5) Note that increasing channel width also increases the

capacitance

The overall delay (after increasing channel width by 2.5)will be the same 7


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CMOS Inverter Rise and Fall Time

Estimation T f ~ 3C L / VDD r ~ 3C L / VDD (Derivations for the above are in Pucknell and Eshraghian

Pages 105 - 107) So, r / f = n/ p Given that (due to mobilities) n = 2.5 p, rise time is

slower by a factor of 2.5 when using minimum dimensionsof n and p transistors

basic interconnects

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