BNL Update and Issues

D. Lynn, May, 25 2012

HV Multiplexing update

DC-DC stave width

SP Stave PPB replacement

Trigger document

HV Multiplexing

• Quad HV switching box using commercial SiC JFETs built and tested at BNL. Each channel biased BNL module with no change in ENC and DTN noise.

• Box rated to 500V

• Shipped to RAL for stavelet testing

HV Multiplexing

• Mounted two boards with 4 dies, and one board with 2 die.

• Plan was to test boards to 700 V and characterize die prior to irradiation

• Started testing with practice 2-die board. Sparking occurred between 500-700 V

• Encapsulated both 4-die boards. Both ran to 700 V with no problem.

• SiC company uses encapsulation also. But I think improved wire bonding pattern should help

Board mounted with four SiC JFETs Encapsulated Board

Original Packaged Parts Set of 3 Potted Parts on Circuit Board # 1Number 1 Number 2 Number 3VDS [V] IG [pA] IS [pA] IG [pA] IS [pA] IG [pA] IS [pA]

0 0 0 0 0.0 0 0 VDS [V] IG [µA] IS [µA] IG [pA] IS [pA] IG [pA] IS [pA] IG [pA] IS [pA]30 0 0.1 0 0.1 4 0.1 0 - - 0 0 0 0 0 040 0 0.1 0 0.1 4 0.1 30 0.17 3.90 3 18 1 1 1 60,00050 0 0.1 0 0.2 5 0.1 40 0.37 4.00 3 23 1 1 2 68,00060 0 0.2 0 0.2 5 0.2 50 0.82 4.20 5 29 1 1 3 76,00070 0 0.2 0 0.3 5 0.2 60 1.73 4.40 5 36 2 1 4 84,00080 0 0.3 0 0.3 5 0.2 70 3.60 4.60 5 41 3 1 4 91,00090 0 0.3 0 0.3 6 0.2 80 7.10 4.70 6 48 3 1 5 99,000100 0 0.3 0 0.3 6 0.3 90 12.40 4.90 7 56 3 1 6 105,000200 1 0.9 0 0.9 8 0.7 100 20.60 5.20 7 65 4 1 6 111,000300 4 1.3 13 1.0 12 1 200 344.00 12.80 15 170 8 1 17 175,000400 17 1.5 41 1.2 24 1.3 300 >1000 24 341 12 2 25 285,000500 45 1.7 72 1.4 73 1.6 400 31 545 17 2 41 291,000600 120 1.8 195 1.5 160 1.6 500 54 862 34 2 79 346,000700 217 1.9 500 1.8 330 2.1 600 112 1,170 128 2 205 403,000800 485 2.1 950 1.8 613 2.1 700 310 1,645 519 4 550 457,000900 848 2.4 1738 2.1 1080 2.11000 1339 2.4 2948 2.2 2025 2.51100 2500 2.7 4941 2.5 3736 2.5 Potted Parts on Circuit Board # 21200 4150 2.9 7875 2.6 6993 2.61300 6300 3.3 11950 3.0 12617 2.71400 9580 3.3 16785 3.1 23310 2.7 VDS [V] IG [pA] IS [nA] IG [pA] IS [pA] IG [pA] IS [nA] IG [pA] IS [nA]1500 14180 3.5 22450 3.3 41680 2.9 0 0 0 0 0 0 0 0 01600 19130 3.6 29500 3.3 75430 3.1 30 3 268 2 0 20 794 7 1,367

40 4 286 3 0 23 832 8 1,42850 5 305 4 0 28 868 11 1,48560 6 316 4 0 32 899 13 1,52870 7 332 5 0 35 929 15 1,57780 8 347 6 0 38 956 17 1,61990 9 359 7 0 42 984 20 1,663

100 9 371 9 2 45 1,001 22 1,679200 20 485 17 7 87 1,209 51 1,996300 38 582 28 16 180 1,358 85 2,238400 80 677 44 23 445 1,502 129 2,451500 220 766 84 32 1,250 1,625 189 2,644600 800 853 237 41 3,475 1,741 308 2,823700 2400 944 840 51 8,200 1,852 678 2,996

Device #4Device #1 Device #2 Device #3

Device #1 Device #2 Device #3 Device #4

Leakage Current

• Die leakage current more varied than that of packaged parts.

• Reason not yet known

JFET performance

• Transistor characteristics of all eight die very good

• Will gamma irradiate these very soon

HV Multiplexing Plan

• Irradiate two boards soon with gammas

• Ordered more die. We are building three more boards. Intention is to irradiate these with protons in August

• Still need to investigate other devices

Shieldless LBNL DC-DC Stavelet

Full length DC-DC stave

•Uses CF tubes, although could be built with Al/polycarbonate sides. What do we want? Has to be compatible with module mounting fixture at RAL.•What should be facing width? •What are bus cable widths?

More information regarding the converter widths. Will assume stays as is (13.5mm width) until we hear otherwise.

Regards, Ashley

-------- Original Message -------- Subject: RE: RE: Future DC-DC Developments for ATLAS StripsDate: Fri, 27 Apr 2012 15:58:18 +0000From: Georges Blanchot <Georges.Blanchot@cern.ch>To: Ashley Greenall <ashley@hep.ph.liv.ac.uk>

Hello, We will try to keep the width the same as on the SM01C and STV10 power modules, I think it is 13.5 mm. A width of 5mm is too narrow. Georges

Full length SP Stave

•What is timescale?

•Will this be chain of modules or chain of hybrids?

•Do we want PPB (chain of hybrids), PPB2 (chain of modules), Ashley’s PPBR* board, or new board? Mitch’s SPP compatible with PPB and PPB2. New board needed to be compatible with SPP and star configuration.

Trigger DocumentL0 accept rate: 500 kHz

L0 latency: ~ 5-6 ms

L1 accept rate: 200 kHz

L1 latency: 20 ms

• Following Stanford, subsystems were asked if the could achieve the trigger performance in box to the right

• I along with others looked into the question. See M. Warren’s talk at the the May 8 ITK-Subcomitte meeting.

• I did a less sophisticated calculation than Matt’s but got the same answer. My calculation is in the backup documents to Matt’s presentation.

• For reference I put the updated version here. The reason I mention this is that some of you may be interested in how the trigger/occupancy/GBT rates/ HCC data rates are related; until a few weeks ago I had no understanding of this.

• Two conclusions are however: with today’s technology it appears the barrel can just about achieve this rates if we discard error correction in the GBT.

• The real test on the trigger rates will be the petals. And in particular the ROI (Region-of-interest) algorithm for the ABC130 appears to fail for the petals….work will be focusing on this in the future.