blocker tolerant software defined receivers
TRANSCRIPT
1
Hooman Darabi
7/25/13
Blocker Tolerant Software Defined Receivers
2
Receiver Noise and Linearity
• Small signal linearity:
IIP2, IIP3
Y
XABAD
Operates here
GGD
fB1 fB22fB1-fB2• Large signal linearity:
Gain compression
• Reciprocal mixing
• Harmonic mixing
• Receiver NF sets the sensitivity, range:
Set by the standard10Log(KT), dBm/Hz
Sensitivity = -174 + NF + 10Log(BW) +SNRRS=50ΩΩΩΩ
RX
Blo
cke
rs: I
n/O
ut-
Ban
d
3
Reciprocal Mixing
• PB + PN(∆∆∆∆B) + 10×LOG(BW) = PD – SNR
• BNF = 174 + PB + PN
fLO
PD
PBSNR
BWfLO
Noisy LO
∆∆∆∆fB
4
Harmonic Rejection & Aliasing in Mixers
Weldon, JSSC 2001
• Square-wave LO harmonically rich
• More phases alleviates the issue
• More energy in main, less in higher harmonics
-6
-4
-2
0
2
2 4 8 16
32
# of Phases
Gai
n, d
B
)(M
SinM π
π
1.0
1.5
2.0
Alia
sin
g
=
1
1/31/5
Aliasing = 1+1/32+1/52+…= ππππ2/2
5
RF IC
Large Blocker
Duplexer
RX Desired
TX Leakage
3/4G Full-Duplex Problem
• Duplexer is a dual-band filter• Similar issue due to co-existence
TX RX
RX-Band NoiseIIP2IIP3
6
Ideal Receiver
fIF = fIN - fLO
ADCADC
IFfLO
RF
• Filter only rejects out-of-band blockers
• In-band blockers require a high-resolution ADC
• Power hungry
• Invented by Armstrong in 1918
• Down-conversion relaxes IF signal processing
• Lower power
-99dBm
0dBm-26dBm
Mitola 1995
7
Ideal Receiver Challenges
• Scalable
• Broad-band: Low-noise, Blocker tolerant
• Low-power
Murmann
97
03 09
15
Year (ADC)
FoM
Current RX
FoM = p/fs/2^ENOB
06
09
Year (3G RX)
I DD, m
A
30
50
70
12
BCM2093
Mikhemar
8
Narrow-Band Filtering Concerns
• Large blockers compress the receiver
• External filtering is narrow-band and costly
-99dBm
0dBm
Mu
lti-
Ban
d R
ece
ive
r
Swit
ch
15-20dB
6.6V p-p
9
N-Path Filtering Concept
• Very high-Q passives needed
• N-path filtering extends Nyquist rate1
SC LPF
fc 2fcfc/2
SC LPF
SC LPF
SC LPF
…… ………… ……
ININOUT
OUT
fc 2fc
NY=N×(fc/2)
L. Franks, Bell Syst. Tech. J., 1960
10
Passive Mixers as High-Q Filters
)()(2
)(2 LOBBLOBBSWin jsZjsZRsZ ωω
π++−+≈
LO1
LO2
LO3
LO4
0
IRF
VRF
0
High-Q BPF from low-Q LPF
fLO
fLO
LO1
LO4
0
LO2
LO3
VRF
IRF
ZBB
Mirzaei, TCAS 2010
Blo
cke
r
11
Current-Mode Receivers
• Passive mixers to achieve high-Q filtering
• Current mode LNA: LNTA
• Enhance the blocker tolerance
GM
0fRF
fRF
0
BUF
BUF
12
Front-End Matching Concerns
• Wide-band matching
• Good linearity
• NF suffers
RS=50ΩΩΩΩ
RS
• Narrow-band matching
• Good NF
• Modest linearity
NF > 3dB
Matching
RS
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Mixer-First Receivers
• N = 1 / (sinc (ππππ/M))2 > 1
• NF > 3dB in practice at GHz frequencies Andrews, JSSC 2010
LO1
LO2
LO3
LO4TI
A_I
I
TIA
_Q Q
RS
VS
SW Resistance, ΩΩΩΩ
NF,
dB
0
1
2
3
4
5
0 10
20
30
40
50
gAlia
S
bb
S
DS NKTRM
v
R
ONrF
sin
2
)4(
)(1 ×
++=• For M phases:
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Noise Cancelling Concept
• Used in broad-band LNA’s
• Poor linearity
RS
RIN=RS
VIN+- ααααVIN
+- -rmIIN
IIN
+VOUT
-
rm = αααα × RS
Relative GainN
F0
Bruccoleri, ISSCC 2002
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Noise Cancelling RX Architecture
• Low noise and linear
• No Balun required
RS
RS = RSW + 2RBB/ππππ2
-+
BW << ∆∆∆∆fB
-+
GM αααα = -GM×RLA+
VOUT
-
Low resistance
Noise and linearity bottleneck
RLA
RLM
rm = RLM
Murphy, ISSCC 2012
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Noise & Linearity Performance of NC RX
• GM noise dominant, no need to provide matching
F ≅≅≅≅ (1+vGM2/4KTRS)×N
• Similarly main path distortion cancelled:
IIP3 ≅≅≅≅ (1+RS/RIN)3/2 × IIP3_AUX
RS
GM+
VOUT
-
TIA_A
TIA_M
Suppressed by GM
Upconverts, Cancelled
Dominant
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Over-Sampling Mixer Architecture
• Synthesizes arbitrary 8-phase LO:
TIA K0
TIA K1
TIA K7
ΣΣΣΣVOUT
…
IRF
8-P
has
e
√2
Harmonic Combination
∑=
−=7
0
)8
()(x
xRFOUTT
xtswKtiV
1
1/7
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Complete NC Receiver Architecture
GM
10ΩΩΩΩ
50ΩΩΩΩ
I
Q
We
igh
tin
g &
Re
com
bin
atio
n
…LO0LO1
LO7
4fLO ÷4
NF ≈ 1 + 1/GMRS
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RF GM Cell
• Class AB transconductance
• Scalable
• Linear due to class AB and low-impedance loading
0.0
0.1
0.2
0.3
-0.7
-0.5
-0.4
-0.2
0.0
0.2
0.3
0.5
0.7
GM
≈ 10ΩΩΩΩ
N P
Overall
VDD
GM
, S
2.7×
Input, V
1×
20
Baseband TIA
• Most power efficient
• Noise: vbb2 ≈ 4KTγγγγ/Gm ≈ 4KT/40ID
• Input resistance: Rin ≈ RF / AOPEN ≈ RF / (Gm(RFllRL))
0
5
10
15
20
25
1 4 13
44
143
464
151
2
492
4
Width, µµµµm
g m/I
D, V
-1
NMOSPMOS
Gm
RF
RL
Gm = gmn+gmp ≈ 40××××ID
Rin
vbb2
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Receiver Scalability
VD
D
4tr
S××××T = 8VDD
• Inherently relies on high-speed logic, switches
• In 40nm, tr ≈ 10pS:
– 12.5GHz for 2-phase (overlapping)
– 3.12GHz for 8-phase
• Scales w/ technology
8-Phase
T = 32tr
VD
D
tr
3tr
tf
S××××T = 8VDD
2-Phase
T = 8tr
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Noise Figure
• 1/f corner reduces from 100kHz to less than 10kHz
• Corresponds to <-113dBm GSM sensitivity
NC ON
NC OFF
NF,
dB
RF Input, MHz
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Blocker Noise Figure
• 4.1dB 0dBm BNF, mostly limited by reciprocal mixing
BN
F, d
B
Blocker Power, dBm
3GPP Requirement
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Linearity
• Close to 0dBm 1dB compression at maximum gain
NC ON
NC OFFP
1-d
B, d
Bm
Blocker Distance, MHz
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NF vs. Relative Phase Correction
• Robust at optimum point
NF,
dB
Relative Phase, ⁰
Uncompensated
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Summary of Performance
Architecture Mixer first NC LNA NB SAW-Less NC RX
RF Range 0.1-2.4GHz 0.4-6GHz 900/1800 0.1-2.7GHz
Input SE Differential Differential SE
NF at 2GHz 7dB 4.4dB 4.1dB 1.8dB
0dBm BNF NA 13dB 7dB 4.1dB
3rd/5th HR 35/43dB None None 42/45dB
OB IIP3 25dBm 10dBm NA 14dBm
RX Current 12mA 12mA 37mA 12mA
Area 2mm2 2mm2 1.4mm2 1.2mm2
Technology 65nm 40nm 65nm 40nm
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NC RX Die Photo
• Die area: 1.2mm2
• Inductor-less
Single-EndedDifferential
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Reciprocal Mixing Issue System Approach
• Start w/ a low-power/cost VCO
• Deal with its consequences in system level
• Proper phase noise estimation is key
Receiver Chain
Noisy VCONoise
Estimation
-Desired + RM
RM Replica
Desired
Reciprocal mixing NF = 174 – PB -PN
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Symmetry of Reciprocal Mixing
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RM Cancellation Architecture
31
Limiter Based Architecture
32
Noise Aliasing in a Limiter
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Protoype RM Cancelling Receiver
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Measured Blocker Noise Figure
• Blocker offset as low as 10MHz
• SS NF of about 2.4dB
Blo
cker
NF,
dB
5
15
25
35
-25 -20 -15 -10Blocker Power, dBm
19dB
Effective LO FoM=188dB
After
Before
Before, Ideal LO
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RM Cancelling RX Die Photo
• 40nm CMOS, 1.4mm2
36
Receiver Architecture for Coexistence
• Second path to divert blocker away
• Relaxes noise and linearity of main receiver
LC-
matchGm
RXLO VCO/PLL
TIA/LPF
TIA/LPF
fRXfb
fRXfb
ZIN :
fRXfb
Short at fb
Open at fRX
Aux Path
Reciprocal mixing NF = 174 – PB -PN
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N-Path Impedance Implementation
• Clocker by the aggressor TX LO
LO1
LO3
ZBB(s)
LO2
LO4
0
ZBB(f)
Zin(f)
fRXfb
Zin(f)
f
LO1
LO3
LO2
LO4
25% duty-cycle clocks @ fb
f-3dB,h (f-3dB,h << fb)
0f
TX Signal
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Coexistence Receiver Architecture
LC-match
Gm
RXLO VCO/PLL
TIA/LPF
TIA/LPF
fRXfb
PRX
Pb
PRX
Pbfb fRX
H1(f)
Main path TF
LO @ fb
+
-TIA
TIA+
-fb fRX
Zin
fb fRX
H2(f)
Aux path TF
LO @ fRX
39
Measured Blocker Noise Figure
• NF > 25dB if Aux path de-activated
Blo
cker
NF,
dB
Blocker Power, dBm
Desired at 2GHz,Blocker at 1.9GHz
40
RX Performance Summary
[1] T. Sowlati, et al., "Single-chip multiband WCDMA/HSDPA/HSUPA/EGPRS transceiver with diversity receiver and 3G DigRF interface without SAW filters in transmitter / 3G receiver paths," ISSCC, 2010, pp. 116-117.[2] M. Nilsson, et al., "A 9-band WCDMA/EDGE transceiver supporting HSPA evolution," ISSCC, 2011, pp. 366-368.[3] Y. H. Chung, et al., "A 4-in-1 (WiFi/BT/FM/GPS) connectivity SoC with enhanced co-existence performance in 65nm CMOS,“ ISSCC, 2012.
Parameter [1] [2] [3] This work
NF, dB 2.5 2.5 4 1.7
OB IIP3, dBm -2.5 -4 -14 -2.5
OB IIP2, dBm > 50 58 N/A > 50
0dBm Blocker NF, dB N/A 13.5
Battery Current, mA 65 44 46 10
Total RX Area, mm2 6.7 3.4 2.2 0.93
Technology 130nm 90nm 65nm 40nm
Application Cellular Cellular WiFi Generic
41
Coexistence RX Die Photo
40nm CMOS with active area of 0.93mm2
42
Summary & Conclusions
• Scalable
• Immune to large blockers and/or low-power
RS
Noise Canc.
RM Canc.
Coexistence
Nφφφφ MX First
DSP