bist
TRANSCRIPT
Chapter 6Chapter 6Chapter 6Chapter 6Design for Testability and Design for Testability and
BuiltBuilt--In SelfIn Self--TestTest
Jin-Fu LiAdvanced Reliable Systems (ARES) LabAdvanced Reliable Systems (ARES) Lab.
Department of Electrical EngineeringNational Central UniversityNational Central University
Jungli, Taiwan
OutlineBasicsDesign-for-Testability (DFT) Techniques
Ad Hoc DFT Structural Methods
ScanScanPartial ScanBISTBoundary ScanSyndrome-Testable DesignC-Testable Designg
Built-In Self-Test (BIST) TechniquesSignature AnalysisPseudorandom Pattern Generator (PRPG)Built-In Logic Block Observer (BILBO)
SAdvanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 2
Summary
Definitions Definition
A fault is testable if there exists a well-specified procedure to expose it which is implementable with procedure to expose it, which is implementable with a reasonable cost using current technologies. A circuit is testable with respect to a fault set
h h d f lt i thi t i t t blwhen each and every fault in this set is testableDefinition
Design for testability (DFT) refers to those Design for testability (DFT) refers to those design techniques that make test generation and test application cost-effective
Electronic systems contain three types of components: (a) digital logic, (b) memory blocks and (c) analog or mixed signal circuitsblocks, and (c) analog or mixed-signal circuitsIn this chapter, we discuss DFT techniques for digital logic
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 3
digital logic
Ad Hoc DFT Guidelines
Partition large circuits into smaller subcircuits to reduce test generation cost (using MUXed g ( gand/or scan chains)
T2T1
1 TTMode
C10
C2
T2T1Mode
0 00 11 0
NormalTest C1Test C21 0
1 0Test C2
0 1 1 0
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 4
Ad Hoc DFT Guidelines
Insert test points to enhance controllability & observability y
Test points: control points & observation points
OP
C1
0 1C2 C2
0
CP1 CP2CP3 CP4
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 5
Ad Hoc DFT Guidelines
Design circuits to be easily initializableProvide logic to break global feedback pathsProvide logic to break global feedback pathsPartition large counter into smaller onesAvoid the use of redundant logicAvoid the use of redundant logicKeep analog and digital circuits physically apartapartAvoid the use of asynchronous logic
d ( lConsider tester requirements (pin limitation, etc)Etc
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 6
Scan Design Approaches
They are effective for circuit partitioningThey provide controllability and observability They provide controllability and observability of internal state variables for testingThey turn the sequential test problem into a They turn the sequential test problem into a combinational oneFour major approachesFour major approaches
Shift-register modificationScan pathScan pathLevel-sensitive scan design (LSSD)Random accessRandom access
Circuit is designed using pre-specified design rules
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 7
rules.
Scan Design ApproachesConsider a representation of sequential circuits
X Z(primary inputs) (primary outputs)
Combinational LogicX Z
Yy (next state)(present state)
stateclk
To make elements of state vector controllable and observable we addand observable, we add
A TEST mode pin (T)A SCAN-IN pin (SI)A SCAN IN pin (SI)A SCAN-OUT pin (SO)A MUX (switch) in front of each FF (M)
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 8
A MUX (switch) in front of each FF (M)
Adding Scan Structure
PI PO
SFFCombinational
PI PO
SCAN-OUT
SFFlogic
SFF
SCAN-INT
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Scan Test Generation & Design Rules
Test pattern generationUse combinational ATPG to obtain tests for all Use combinational ATPG to obtain tests for all testable faults in the combinational logicAdd shift register tests and convert ATPG tests into scan sequences for use in manufacturing test
Scan design rulesUse only clocked D-type of flip-flops for all state variablesAt l t PI i t b il bl f t t At least one PI pin must be available for test; more pins, if available, can be usedAll clocks must be controlled from PIsAll clocks must be controlled from PIsClocks must not feed data inputs of flip-flops
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 10
Correcting a Rule Violation
All clocks must be controlled from PIs
Comb.logic
Comb
D1 Q
FF Comb.logicD2
CK
FF
Q
Comb.logic
Comb.logic
D1D2
CK
Q
FF
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 11
Correcting a Rule ViolationAdding a scan FF and a mux allows a feedback loop to be opened for testing
A B 0 1
A B
0 1
CK
FFA B 0
TTest
Testing derived clocks requires the use of a mux to bypass the division stagesyp g
FFCK Freq. DividerFF
CK Freq. Divider
0 1
FF
q
FF
0
Test
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 12
Correcting a Rule ViolationThe AND gates keep the bus drivers from being activated by the normal logic during testing
FFFF
FF
FF
FFFF
Test
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Scan Test Procedure
Step 1: Switch to the shift-register mode and check the SR operation by shifting in an p y galternating sequence of 1s and 0s, e.g., 00110 (functional test)Step 2: Initialize the SR---load the first patternStep 3: Return to the normal mode and apply the test patternStep 4: Switch to the SR mode and shift out the final state while setting the starting state g gfor the next test. Go to Step 3
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 14
Combining Test Vectors
I2PI POI2I1 O1 O2
Combinational
PI PO
SCAN-IN SCAN OUT
S2S1 N2N1
logic
Presen Nextt t
SCAN INT SCAN-OUT
S2S1 N2N1t
statestate
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Combining Test Vectors
I2I1PI
Don’t careor random
bitsPI
SCAN-IN S1 S2
0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0T
O1 O2PO
SCAN-OUT N1 N2
Sequence length = (ncomb + 1) nsff + ncomb clock periodsncomb = number of combinational vectors
b f fli fl
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nsff = number of scan flip-flops
Testing Scan Register
Scan register must be tested prior to application of scan test sequencesapplication of scan test sequencesA shift sequence 00110011 . . . of length n ff+4 in scan mode (TC=0) produces 00 01 nsff+4 in scan mode (TC 0) produces 00, 01, 11 and 10 transitions in all flip-flops and observes the result at SCAN-OUT outputpTotal scan test length: (ncomb+2)nsff+ncomb+4 clock periods(ncomb 2)nsff ncomb 4 clock periodsExample: 2,000 scan flip-flops, 500 comb. vectors, total scan test length ~ 106 clocksvectors, total scan test length 10 clocksMultiple scan registers reduce test length
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 17
Multiple Scan RegistersScan flip-flops can be distributed among any number of shift registers, each having a separate SCAN-IN and SCAN-OUT pinTest sequence length is determined by the longest scan shift registerJust one test control (TC) pin is essential
SCAN IN1 SCAN OUT1
T
Scan Registe 1SCAN-IN1 SCAN-OUT1
SCAN-IN1 SCAN-OUT2
Scan Register 1
Scan Register 2
SCAN-INK SCAN-OUTKScan Register 3
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Hierarchical ScanScan flip-flops are chained within subnetworks before chaining subnetworksAdvantages:
Automatic scan insertion in netlistCircuit hierarchy preserved – helps in debugging and design changes
Disadvantage: Non-optimum chip layout
Scanin ScanoutSFF1 SFF4
SFF3SFF1
Scanin Scanout
ScaninScanout
SFF2 SFF3 SFF2SFF4
Hierarchical netlist Fl t l t
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Hierarchical netlist Flat layout
Optimum Scan Layout
IO SFF
XX’
IOpad
Fli
cell
SCANINFlip-flopcell
Y Y’
T SCAN
Y Y
OUT
Interconnects
Routingchannels
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Active areas: XY and X’Y’
Automated Scan Design
Behavior, RTL, and logicDesign and verificationRule
i l ti g
Gate-level
Scan designrule audits
violations
Gate-levelnetlist
CombinationalATPG
Scan hardwareinsertionATPG insertion
Chi l t SS
Scannetlist
Combinationalvectors
Chip layout: Scan-chain optimization,timing verification
Scan sequenceand test program
generation
D i d t t
Scan chain order
Design and testdata for
manufacturing Mask dataTest program
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An Example of DFT Compiler Flow
check_test check_testinsert_scancompile -scan
Pre-Scan DRC
Insert ScanScan-Ready
Synthesis
Post-Scan DRC
HDLPreview
CoverageHDL g
Constraints:Scan style,speed, area
TechnologyLibrary:Gates, flip-flops,
Constraint-Based Scan Synthesis:Routing, balancing,p , p p
scan equivalents gate-level optimization
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 22
Source: H.-J. Huang, CIC
Shift Registers
Scan added:
SHFT_INSI
SHFT_OUT/ SODFFDFFDFF
SECLK
Revised:
SHIFT_OUTSHIFT_IN
SIDFF DFF DFF
CLKSE
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 23
Source: H.-J. Huang, CIC
Lockup Latch Insertion
F1 F2 latch F3
CLK_RTZ_1 CLK_RTZ_2tINV
clk1 clk1
clk2 clk2
Big Problem !!OK! Big Problem !!Rearrange clock domain or
insert lockup latch
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 24
Source: H.-J. Huang, CIC
Random Access Scan
Uses addressable latchesProvides random access to FFs via Provides random access to FFs via multiplexing—address selection
C/LX ZC/LX Z
C
L L L
CSI
L
SO
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Random Access ScanRandom access scan cell
DICK1
C=CK1&CK2CK1
SI +L
CK2Addr
AdvantagesF t i i l i t l th
AddrSO
Fast; minimal impact on normal pathFast for testing—random accessAbility to ‘watch’ a node in normal operation modeAbility to ‘watch’ a node in normal operation mode
DisadvantagesH d t i l i dd d
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Hardware cost is large; more pins added
Random Access Architecture
Combinational/Logic
Addressableclocks and controls Sin
SCKSi
dd essab estorage
elements Sout
SCKy-address Y
decoder
...
X decoderx-address
. . .
During normal operation the storage cells operate in their parallel-load mode
x address
their parallel load modeTo scan in a bit, the appropriate cell is addressed, the data are applied to sin
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 27
the data are applied to sin
Test Procedure
1. Set test input to all test points2 Apply the master reset signal to initialize all memory2.Apply the master reset signal to initialize all memory
elements3 Set scan in address and data and then apply the scan3.Set scan-in address and data, and then apply the scan
clock4 Repeat step 3 until all internal test inputs are scanned4.Repeat step 3 until all internal test inputs are scanned
in5 Clock once for normal operation5.Clock once for normal operation6.Check states of the output points7.Read the scan-out states of all memory elements by
applying appropriate X-Y signals
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Scan-Hold FFs (SHFFs)HOLD=0 Q & Q’ are fixed
SO
D
SIQ
SFFTC
CKQ
CK
HOLD
The control input HOLD keeps the output steady at previous state of flip-flopApplications
Reduce power dissipation during scan, etc.
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Scan Enters the Nanometer EraTrend in flip flop count with design size
[Source: EE Times]
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Scan Enters the Nanometer EraAdaptive scan architecture
[S EE Ti ]
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 31
[Source: EE Times]
Syndrome-Testable DesignDefinition
The syndrome of a Boolean function is , f nfkfS
2)()( ≡
fwhere is the number of 1s (minterms) in and is the number of independent input variablesA typical syndrome testing set up
2k f n
A typical syndrome testing set-up
CUT Syndrome C t
(Counter)
Exhaustive patterns
CUT
Reference syndrome
Syndrome register
ComparatorGo/No-go
A circuit is syndrome testable iff fault ,1)(0 ≤≤ fS
syndrome
∀ α )()( αfSfS ≠y ,Syndromes of logic gates
Gate nAND nOR nXOR NOT
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n2/1S )2/1(1 n− 2/1 2/1
Syndrome Computation
Consider a circuit having 2 blocks, f and g, with unshared inputsp
ff SSSS −+O/P Gate
SOR
f SSAND
gfgf SSSS 2−+XOR
f SS−1NAND
gfgf SSSS +−−1NOR
ExampleCalculate the syndrome of the following circuit
gfgf SSSS +S gf SS gfgf SSSS gf SS1 gfgf SSSS
Calculate the syndrome of the following circuit
S 1 1/4 3/4
S
S1
S2
S1 = 1-1/4 = 3/4S2 = 1-1/4 = 3/4S3 = 1/8
S4
S3
S4 = 1- S2 - S3 + S2S3 = 7/32S = S1S4 = 21/128
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 33
Syndrome-Testable Design
Consider the function . The circuit is syndrome untestable
zyxzf +=syndrome untestable
If the circuit has a fault , then the 2/1=fS
0/z≡α ,corresponding syndrome of the faulty circuit isThus the circuit is syndrome untestable
2/1' =fS
A realization C of a function f is said to be syndrome-testable if no single stuck-at fault causes the circuit to have the same syndrome as the fault-free circuit Syndrome is a property of function, not of implementation
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 34
Syndrome-Testable Design
DefinitionA logic function is unate in a variable xi if it can be g irepresented as an SOP or POS expression in which the variable xi appears either only in an uncomplemented form or only in a complemented uncomplemented form or only in a complemented formFor example:For example:
no unateunate in , not unate
212121 ),( xxxxxxf +=
313221321 ),,( xxxxxxxxxf ++= 32 , xxin
Theoreml l d d l
3331x
A 2-level irredundant circuit realizing a unate function in all its variables is syndrome testable
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 35
Syndrome-Testable Design
TheoremAny 2-level irredundant circuit can be made ysyndrome-testable by adding control inputs to the AND gates
For exampleThe function is syndrome untestable zyxzf +=
f ′Now add a control input , where 1 when in normal operation mode
l i/ h i t t d≡C
zycxzfc +=′∋
normal i/p when in test mode, and Syndrome testable
DrawbacksyfS =′=′ α,8/3 SS ′≠=′ 2/1α
DrawbacksOnly for combinational logicExhaustive; modification doubles test set size
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Exhaustive; modification doubles test set size
Easily Testable CircuitsRegularly structured circuits consists of an array of identical cells
They may be arranged in one-, two- or three-dimensional arrays
),( jii1−i i
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Iterative Logic ArraysCombinational regular structures are usually referred to as iterative logic arrays (ILAs)For example
N-bit comparators are often organized in a one-dimension array and each compares the corresponding bit from two numbersA parity tree consists of cells and every cell is A parity tree consists of cells and every cell is realized with a two-input XOR
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C-TestabilityDefinition
A C-testable array is an array testable with t t b f t t tt i d d t f th constant number of test patterns independent of the
size of the array
A cell is a combinational machine )( fΔΣA cell is a combinational machine , where is the cell function and and for
),,( fΔΣΔ→Σ:f I}1,0{=Σ
O}10{=Δ NOI ∈and for Definition
A cell function is injective if
}1,0{Δ NOI ∈,
)()()()( jifjifjiji ≠≠∀A cell function is injective if . If a function is injective and , then the function is bijective.
),(),(),,(),( 22112211 jifjifjiji ≠≠∀Δ=Σ
TheoremA -dimensional ILA with a bijective cell function is k
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C-testable
Design for C-TestabilityA 2’complement array multiplier
a c
b
s s
a c
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 40
Design for C-Testability
Modified the multiplier such that the inputs of the AND gate can be fully controlledg y
a c a cz
b
a cb
w
s ˆs s s s
a c a cb
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 41
Design for C-Testability
ˆ ˆ
Truth table of the multiplier cell Truth table of the modified multipliercell
za cs a csb0 0 0 00 0 0 1
0 0 0 00 0 1 0
za cs a csb0 0 0 00 0 0 1
0 0 0 00 0 1 10 0 0 1
0 0 1 00 0 1 10 1 0 0
0 0 1 00 0 1 00 0 0 10 1 0 0
0 0 0 10 0 1 00 0 1 10 1 0 0
0 0 1 10 0 1 00 0 0 10 1 0 0
0 1 0 10 1 1 00 1 1 11 0 0 0
0 1 1 00 1 1 00 1 0 11 0 0 0
0 1 0 10 1 1 00 1 1 11 0 0 0
0 1 1 10 1 1 00 1 0 11 0 0 01 0 0 0
1 0 0 11 0 1 01 0 1 1
1 0 0 01 0 1 01 0 1 01 0 0 1
1 0 0 01 0 0 11 0 1 01 0 1 1
1 0 0 01 0 1 11 0 1 01 0 0 1
1 1 0 01 1 0 11 1 1 01 1 1 1
1 1 1 01 1 0 11 1 0 11 1 1 1
1 1 0 01 1 0 11 1 1 01 1 1 1
1 1 1 01 1 0 11 1 0 01 1 1 1
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 42
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Test Pattern Application
Test application(Ii,Ji) are all possible combinations( i, i) pThus we only need apply (Ii,Ji), the array can be tested regardless of the array size
1J
I
2J 3J
2I3I 4I
)( ji
1I
2I2J 3J
3
3I 4I4J
4
5I),( ji2
3I 4I3J 4J
5I5J
6I
4J 5J 6J
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 43
Introduction to Built-In Self-Test
Built-in self-test (BIST):The capability of a circuit (chip/board/system) to
lftest itselfAdvantages of BIST
Test patterns generated on chip controllability Test patterns generated on-chip controllability increased(Compressed) response evaluated on-chip ( p ) p p
observability increasedTest can be on-line (concurrent) or off-lineTest can run at circuit speed more realistic; Test can run at circuit speed more realistic; shorter test time; easier delay testingExternal test equipment greatly simplified, or even q p g y p ,totally eliminatedEasily adopting to engineering changes
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Introduction to Built-In Self-Test
On-line BISTConcurrent (EDAC, NMR, totally self-checking ( , , y gcheckers, etc.):
Coding or modular redundancy techniques (fault tolerance)tolerance)
Module 1
Module 2Voter Output
Instantaneous correction of errors caused by temporary or permanent faults
Module N N-Modular Redundancy (NMR)
temporary or permanent faultsNonconcurrent (diagnostic routines):
Carried out while a system is in an idle state
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y
Introduction to Built-In Self-TestOff-line BIST
A typical BIST architecture
Functional Circuit(Ci it U d T t)PG RA Go/No-Go(Circuit Under Test)PG RA
Controller
Go/No Go
Test generationBIST
Controller
Test generationPrestored TPG, e.g., ROM or shift registerExhaustive TPG, e.g., binary counter, g , yPseudo-exhaustive TPG, e.g., constant-weight counter, combined LFSR and SRPse do andom patte n gene ato e g LFSR
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Pseudo-random pattern generator, e.g., LFSR
Introduction to Built-In Self-TestResponse analysis
Check-sum Ones countingTransition countingP it h kiParity checkingSyndrome analysisEtcEtc.
Linear feedback shift register (LFSR) can be both the test generator and response analyzerboth the test generator and response analyzerWe need a gold unit to generate the good signature or a simulatorsignature or a simulator
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 47
Signature AnalysisA compression technique based on the concept of cyclic redundancy checking (CRC) and
li d i h d i li f db k realized in hardware using linear feedback shift registers D fi itiDefinition
A function f(x1,x2,…,xn) is said to be linear if it can be expressed in the formbe expressed in the form
wherenn xaxaxaaf ⊕⊕⊕⊕= 22110
niai ,,1,0}1,0{ =∀∈whereThere are 2n+1 linear functions of n variablesLinear operations: modulo addition, module scalar
niai ,,1,0}1,0{ ∀∈
multiplication, & delayNonlinear operations: AND, OR, NAND, NOR, etc.
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 48
Linear Feedback Shift RegisterDefinition
A linear feedback shift register is a shift gregister with feedback paths which consist only of unit delays and XOR operators
Let M=fault-free circuit response, B=faulty circuit response, and E=error syndrome (H i ) h E M B th M B E (Hamming), where E=M B thus M=B E and B=M E
W d i it t t k B i t d ⊕
⊕ ⊕
We need a circuit to take B as input and compact it but still be able to tell if M!=B
LFSR is conside ed as a pop la app oach fo LFSR is considered as a popular approach for test response compaction
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 49
Structures of LFSRTwo types of generic standard LFSRs
C1 CNC2 CN-1
D FF D FF D FF
Y1 Y2 YN-1 YN
C1 CNC2 CN-1
D FF D FF D FF
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 50
Y1 Y2 YN-1 YN
Mathematical Foundation of LFSRAs a function of time, Yj can be expressed as
for H
)1()( 1 −= − tYtY jj 0≠j)()( jtYtYHence
If we denote the translation operator as Xk, h k i th ti t l ti it
)()( 0 jtYtY j −=
where k is the time translation unit
O th th h d Y (t) b d
jj XtYtY )()( 0=
On the other hand, Y0(t) can be expressed as
Th ∑=N
jjj tYCtY
10 )()(
Then for
=j 1
∑=N
j
jj XtYCtY
100 )()( Nj ≤≤1
=j 1
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 51
h ( )Mathematical Foundation of LFSR
We can rewrite the Y0(t) as
∑N
jXCYY )()(
Also
∑=
=j
jj XCtYtY
100 )()(
0)1)(( +∑N
jXCtYAlso,
We can rewrite this expression as
0)1)((1
0 =+∑=j
jj XCtY
0)()( XPtYWe can rewrite this expression asFor nontrivial solution, , we must have
0)()(0 =XPtY N
0)(0 ≠tY0)(XP
where 0)( =XPN
∑+=N
j
jjN XCXP
1
1)(
is called the characteristic polynomial of the LFSR
=j 1
)(XPN
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 52
the LFSR
LFSR for Signature AnalysisA serial input stream mn, mn-1,…, m1, m0entering the LFSR can be considered as the
ffi i t f l i lcoefficients of a polynomial01
11)( mXmXmXmXm n
nn
n ++++= −−
C1 CrC2 Cr-1C0
m(X) q(X)D FF D FF D FF
The LFSR is said to have a characteristic polynomial
m(X) q( )s1 s2 sr-1 sr
The LFSR is said to have a characteristic polynomial defined as follows
011
1)( cXcXcXcXc rr
rr ++++= −
−
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 53
LFSR for Signature AnalysisAssume that the initial state of the LFSR is Di=0, i=0,…,r-1, then the LFSR effectively di id (X) b (X) i divides any m(X) by c(X), i.e.,
Th i (X) i ll h )()()()( XsXCXqXm +•=
The quotient q(X) appears serially at the output of the SR. The remainder s(X) is in the SR after n+1 shifts:SR after n+1 shifts:
011
1)( sXsXsXsXs rr
rr ++++= −
−
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 54
An ExampleThe following LFSR divides any m(X) by c(X)=X5+X4+X2+1
DD DD D
Suppose m(x)=X7+X6+X5+X4+X2+1 then
D1D0 D3D2 D3m(X) q(X)
Suppose m(x)=X7+X6+X5+X4+X2+1, then q(X)=X2+1, and s(X)=X4+X2
I/P D D D D D O/PI/P D0 D1 D2 D3 D4 O/P10101111101
00
01
01
01
01
--
101-
000
000
001
100
011
101
101
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 55
Signature AnalysisLet m(X) be the input polynomial of degree k-1, q(X) the quotient, and s(X) the signature (remainder). ThenThen
m(X)=q(X)c(X)+s(X)The error syndrome can be represented as a The error syndrome can be represented as a polynomial e(X)
E.g., le m(X)=X4+X3+1(11001), and an erroneous E.g., le m(X) X +X +1(11001), and an erroneous input b(X)=X3+X+1(01011), then the error syndrome is 11001 01011=10010, and is
t d b (X) X4+X⊕
represented by e(X)=X4+XIn general, an erroneous input polynomial can be represented byrepresented by
B(X)=m(X)+e(X)
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 56
Signature AnalysisTheorem1: Input streams m(X) and b(X) have the same signature iff e(X) is a multiple of c(X)
Proof: an error is not detected when m(X) and b(X) have Proof: an error is not detected when m(X) and b(X) have the same signature, i.e., b(x)=q’(X)c(X)+s(X). Since m(X)=q(X)c(X)+s(X), we obtain (X) (X) b(X) (X)( ’(X) (X))e(X)=m(X)+b(X)=c(X)(q’(X)-q(X))
Theorem2: Undetected errors correspond to error patterns which are multiples of c(X)patterns which are multiples of c(X)Theorem3: If c(X) has 2 or more nonzero coefficients—i.e., at least 1 feedback term—then it ,can detect all single-bit errors
Proof: all nonzero multiples of c(X) must have at least 2 ffi i t Th f ith l 1 nonzero coefficients. Therefore, any error with only 1
nonzero coefficient cannot be a multiple of c(X) and must be detectable.
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 57
Aliasing ProbabilityTheorem4: for a k-bit response sequence, if all possible error patterns are equally likely, then the p obabilit of failing to detect an e o (i e the probability of failing to detect an error (i.e., the aliasing probability) by the LFSR of length r is
12 −rk
Proof: For a k-bit response, deg(m(X))=k-1, and 1212
−−
= kalP
Proof: For a k bit response, deg(m(X)) k 1, and deg(e(X))<=k-1. Therefore, the number of possible error polynomial is represented by e(X)=c(X)p(X) fo some non e o p(X) Since deg(c(X)) the for some nonzero p(X). Since deg(c(X))=r, the number of possible p(X)’s is 2k-r-1. Thus
12 −−rk
For a long sequence, k>>r Pal~1/2r
1212
−= kalP
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 58
g q , al /
Multiple-Input Signature RegisterThe structure of multiple-input signature register (MISR)
D1Dr-2 Dr-1D0
D FF D FF D FF
C1Cr C2Cr-1
The mathematical theory is a direct extension of the results shown aboveFor equally likely error patterns and long data streams, the aliasing probability for an MISR of rstages also is
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 59
stages also is . ralP 2/1≈
Response Compaction
Usually, we think of data compression as a process that preserves data integrity. This is why we given more attention here to data compaction, which may result in some losses There are several compaction testing techniquesThere are several compaction testing techniques
Parity testingOne countingOne countingTransition countingSyndrome calculationSyndrome calculationSignature analysis
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 60
Parity TestingThis is the simplest of all techniques but also the most lossyThe parity of responses to the test patterns is calculated as
where L is the length of the test and r is ∑ ==
Li rP , where L is the length of the test and ri is the response for the ith test pattern
The response of the circuit under test (CUT) to
∑ ==
i irP1
The response of the circuit under test (CUT) to pattern i and the partial product Pi-1 is illustrated as below
1−iP
D FFCUTirTest
Patterns
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 61
One CountingThe number of 1’s in the response stream is calculated and compared to the number of 1’s in the fa lt f ee esponsesfault-free responsesConsider the circuit shown below
ab
11110000
11001100
11000000
If we have a test of length L and the fault free count c
11001100
10101010
11101010 f
If we have a test of length L and the fault-free count is m, the possibility of aliasing is [C(L,m)-1] patterns out of a total number of possible strings of length L, p g g ,(2L-1)
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 62
Transition CountingIn transition counting compaction, it is only the number of transition 0 1 and 1 0 that are counted. Th s the signat e is gi en b Thus the signature is given by
, where the summation is ordinary addition and is XOR operation
11
1 +−=
=⊕∑ i
Li
i i rr⊕addition and is XOR operation
The compaction scheme is shown below⊕
1−irD FFCUT
irTest
Patterns
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 63
Pseudorandom Pattern GeneratorLogic BIST uses mostly pseudorandom (PR) tests. They are usually much longer than deterministic tests b t a e definitel less costl to gene atetests, but are definitely less costly to generatePR tests are generated using a LFSR or cellular automata automata By means of a simple circuit called an autonomous linear feedback shift register (ALFSR)g ( )Definition: an ALFSR is a LFSR with no external inputsFaults that are hard to detect with PR tests are called random pattern resistant faults
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 64
Pseudorandom Pattern Generator (PRPG)Example: the following ALFSR generates the pseudorandom sequence shown in the table below
Q1 Q2 Q3 Q4 output
Q1
Q2
State 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15=01 0
1 1
1 1
1 1
0 1
1 0
0 1
1 0
1 1
0 1
0 0
1 0
0 1
0 0
0 0
1 0
Q3
Q4
00
00
10
11
11
11
01
10
01
10
11
01
00
10
01
00
The output sequence is 000111101011001, which repeats after 15(2n-1) clocksMax period for an n-stage ALFSR=2n-1
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 65
p gAll-0 state of the register cannot occur in the max-length cycle
Mathematical Foundation of PRPGA generic structure of ALFSR
C1 CnC2 Cn-1Cn-2
Q1 Q2 Qn-1 Qn1−mama nma1+nma2−ma
A sequence of bits {am}=a0,a1,…,am,… can be associated with a polynomial—its generation function:
1−mm nm−1+−nma2−m
I th b fi th t th t t t f Q i
∑∞
==++++≡
010)(m
mm
mm XaXaXaaXG
In the above figure, assume that the current state of Qi is am-i, i=1,2,…,n, and the initial state of Qi is a-i=0, i=1,2,…,n, but a-n=1, then ∑= −=
n
i imim aca1
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 66
∑=i 1
Mathematical Foundation of PRPG
∑ ∑∞
= =−=
0 1
)(m
n
i
mimi Xac∑ ∞
==
0)(
mm
m XaXG ∑ ∑=
∞
=
−−=
n
i m
imim
ii XaXc
1 0
][1
11∑ ∑
=
∞
=
−−
−−
−− +++=
n
i im
imim
ii
ii XaXaXaXc
1∑ ∑∞n
mii ][1 0
11∑ ∑
= =
−−
−− +++=
i m
mm
ii
ii XaXaXaXc
])([ 11∑ −− +++=
ni
ii
i XGXaXaXc ])([1
1∑=
−− +++i
ii XGXaXaXc
∑ ∑ −−
−− +++=
n ni
ii
ii
i XaXaXcXGXc 11 )()(∑ ∑
= =i iiii
1 11 )()(
∑ ∑ −−
−− ++=+⇒
n ni
ii
ii
i XaXaXcXGXc 11 )()(1
= =i i1 1
∑∑ =
−−
−−
+
++=⇒ n i
n
ii
ii
i
Xc
XaXaXcXG 1
11
1
)()(
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 67
∑ =+
i i Xc1
1
Mathematical Foundation of PRPGNow is the characteristic polynomial of the LFSR as defined above. Since a-1=0, i=1,2,…,n-1, and a =1 we have
∑=+=
n
ii
i XcXc1
1)(
and a-n=1, we have
The sequence {a } is cyclic with the period assumed ∑∞
=
==0)(
1)(m
mm Xa
XcXG
The sequence {am} is cyclic, with the period assumed to be p
)(1)( 1−+++==∴ pXaXaaXG )()(
)( 110 −+++==∴ p XaXaaXc
XG)( 1
110−
−++++ pp
p XaXaaX)( 1
1102 −
−++++ pp
p XaXaaX+
110 p
)1)(( 21110 ++++++= −
−ppp
p XXXaXaapXaXaa +++ − )( 1
pp
XXaXaa
−+++
= −
1)( 110
1110
1 −+++=−
∴ pp
p
XaXaaX i.e., c(X) evenly divides into 1-Xp
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 68
110)( −paaaXc
i.e., c(X) evenly divides into 1 X
Theorems
Theorem: If the initial state of an n-stage LFSR is a-i=0, i=1,2,…,n-1, and a-n=1, then the LFSR sequence {am} i i di ith i d th t i th ll t i t is periodic with a period that is the smallest integer p for which c(X) divides 1-Xp
The period p<=2n-1The period p< 2 1For a given n, we want to find a c(X) that maximizes p
Definition: The sequences produced by max-length LFSRs are called pseudorandom sequences or m-sequences. The characteristic polynomial associated with an m-sequence is called a primitive polynomial with an m-sequence is called a primitive polynomial. An irreducible polynomial is one that cannot be factored
Pseudorandom sequences (or m-sequences) are not really random since they are produced by a fixed circuit.
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 69
TheoremsTheorem: An irreducible polynomial c(X) satisfies the following 2 conditions:
It h dd b f t i l di th t t It has an odd number of terms including the constant termIf its degree n>3, then c(X) must divide 1+Xp, where g , ( ) ,p=2n-1
Theorem: A primitive polynomial is irreducible if the smallest positive integer p that allows the polynomial smallest positive integer p that allows the polynomial to divide evenly into 1+Xp occurs for p=2n-1, where n is the degree of the polynomialg p y
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 70
Built-In-Logic-Block-Observer (BILBO)
A BILBO is a multi-purpose test module which serves as a test generator or a signature analyzer. It is composed of a row of FFs and some additional gates composed of a row of FFs and some additional gates for shift and feedback operation
Z1 Z2 Z3 Z4
B1B2
Z1 Z2 Z3 Z4
D D D DSI
01
B1 B2 Function0 11 10 0
All FFs are resetBehaves as separate latches—normal modeA linear shift register—SR mode
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 71
1 0 MISR/PRPG—test mode
STUMPS ArchitectureLogic BIST with STUMPS architecture
PRPG
CUT
PIs
T t BS
R
Test control signal
POs
MISR
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 72
Summary
Design-for-testability techniques Ad-hoc techniquesqScan LSSDRandom access scanSyndrome-testable C-testability
Scan is a popular DFT technique in modern IC designDFT can increase the controllability and observability of the circuit under test
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 73
Summary
Built-in self-test methodology is more and more important for deep submicron designsp p gTwo key components of BIST
Test pattern generatorp gE.g., LFSR
Response evaluatorE.g., BILBO
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 74