bharat bhushan j. electrical systems 6-3 (2010): 361 … · it is observed that using fuzzy logic...

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Department of Electrical Engineering, Delhi Technological University, Delhi Email: [email protected], madhusudan @dce.ac.in, [email protected]

Copyright © JES 2010 on-line : www.journal.esrgroups.org/jes

Bharat Bhushan

Madhusudan Singh

Girraj Kumar Bairwa

J. Electrical Systems 6-3 (2010): 361-376

Regular paper Performance Analysis of Indirect Vector Control Induction Motor using PI, Fuzzy and Neural Network Predictive Control

In this paper performance of an indirect vector control induction motor (IVCIM) have been studied with proportional plus integral (PI) Fuzzy and Neural Network (NN) based controllers. Implementation of PI, fuzzy logic control and NN predictive control for studies of regulation ofspeed in IVCIM is described under different operating conditions of induction motor. Simulation studies of IVCIM have been carried out in MATLAB. Motor currents, torque and speed of IVCIM have been analysed using three controllers. A comparative analysis performance of induction motor with three controllers has been presented. It is observed that using fuzzy logic control speed reaches at its desired value faster as compared to other controllers while using neural network predictive control motor currents and torque are stabilized (less fluctuating) quickly as compared to PI and Fuzzy controller

Keywords: Induction Motor, Indirect Vector Control, PI control, Fuzzy logic control, Neural Network Predictive control.

1. INTRODUCTION

The interest in sensor less drives of induction motor (IM) has grown significantly over the past few years due to some of their advantages, such as mechanical robustness and low maintenance. Senseless AC drives are in various modern industrial processes, with stringent performance requirement for higher power quality and productivity. Extensive research work on IVCIM is available in the literature on the performance analysis of IVCIM. Scalar control method has a simple control structure [1] and is implemented easily, within general-purpose industrial applications. To improve speed control performance of the scalar control method, and encoder or speed tachometer is required; however it is expensive and destroys the mechanical robustness of the induction motor. For achieving variable speed operation, the frequency control method [2] of the cage motor is the best method among all the methods of the speed control. There is a wide variety of applications such as machine tools, elevators; mill drives etc. where quick control over the torque of the motor is essential. Such applications are dominated by DC drives and cannot be satisfactorily operated by an induction motor drive with constant volt/hertz scheme. DC motors are easily controllable [3] than AC motors but they require much cost. The vector representation [4] is important because it gives a simple method of combining separate field components: if two sinusoidal distributed fields are combined, the vector representation of the resultant field is simply the sum of the component field vectors. With the vector control or field oriented control theory [5] induction motors can be controlled like a separately excited DC motor. Indirect field indirect field oriented control (FOC) or observers allow [6] FOC to be applied without special flux sensors. A hybrid system controller [7] incorporating fuzzy controller with vector-control method was proposed for induction motors. Speed sensors [8] are replaced by a flux model which needs the use of two additional voltage sensors. The benefits of squirrel cage induction motors-high robustness and low maintenance- make it widely used [9] through various industrial modern processes, with growing economical and performing

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demands. Use of PI controllers [10] for speed control of induction machine drives is characterized by an overshoot during tracking mode and a poor load disturbance rejection. Concept of fuzzy set theory and operation, fuzzy logic based controller etc. is presented by Berkely [11]. An auto tuning method based on fuzzy reasoning was proposed [12] for the speed controller in vector controlled induction motor drive system. A novel approach [13] was proposed by for design of fuzzy controllers without resorting to domain knowledge of the plant under control. Conditions in which we use fuzzy logic controller [14] were pointed out by indirect vector control induction motor drive. ANN application was pointed out to estimate the speed of induction motor at different load torque conditions. A new advanced control algorithm was proposed [15] for speed and flux tracking of an induction motor. The ANN provides a nonlinear modelling of motor drive system [16] without any knowledge of predetermined model and thus makes the drive system robust to noise, parameter variations, load changes. A resulting NN was proposed [17] to use as a numerical controller to replace the proposed original PI based controller in the indirect field oriented induction machine drive control structure. Learning through example is a powerful tool for indirect vector control speed drive [18-19]. A simple structure NN [20] is suggested for controlling the speed of the IM based on feedback linearization. In this paper an induction motor speed & torque involve PI, fuzzy and Neural Network control techniques. An implementation of PI, fuzzy logic and neural network predictive control for speed and torque regulation of IVCIM is presented. A comparative analysis of three controllers has been shown for IVCIM in term of motor currents, speed and torque.

2. INDIRECT VECTOR CONTROL INDUCTION MOTOR (IVCIM)

Output voltage control in PWM static power converters is performed by choosing at any instant the most appropriate duty cycles driving the converter switches. The duty cycle d is the ratio of the on-time of the switch to the duration T of the switching period:

offon

onon

ttt

Ttd

+== (1)

The PWM waveform can be obtained in different ways [14]. The classical analog implementation encompasses a comparator and an integrator, which generates a ramp from a constant signal. The output of the integrator gives either a sawtooth or triangular carrier at the sampling frequency Tf s

1= , which is compared to a reference signal in order to

determine the switching instants, as shown in fig. 1. With a sawtooth carrier of amplitude A, a reference signal u* in the range [0; A] will correspond to a duty cycle in the range [0; 1]. Instead, by using a triangular carrier which varies in the range [-A; A], the reference signal u* shall belong to the same interval in order to generate an output signal u with a duty cycle in the range [0; 1].

When digital signal processing methods are preferred, integrators are replaced by digital timers at frequency sc ff >> and the digitized reference signal is compared with the actual timer count at the high repetition rate fc to obtain the required time resolution. This process is referred to as natural sampling. However other sampling techniques exist which are optimized for digital platforms, especially for microprocessors.

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Fig. 1. Analog generation of PWM waveform.

The method used in this paper is referred to as symmetrical regular sampling [14]. It

allows to sample the reference waveforms at the very low repetition rate fs, i.e. just once in a sampling period. Referring to fig. 2, in order to simplify the discussion, the carrier has unity amplitude. The sampling instants are referred to as tsn, where subscript n denotes the n-th period. The switching instants are denoted by T1n and T2n, for negative and positive edges respectively.

Fig. 2. Symmetrical regular sampling.

The triangular carrier shown as a dotted line does not have to be generated as a signal

since, by means of geometrical relationships, it is possible to obtain equations which allow to compute the switching instants in real time, starting from the reference value u*. If both carrier and reference signal vary in the range [-1; 1] the switching instants are given by (2) and (3), where the subscript n has been omitted for the sake of simplicity.

( ))(14

*1 stuTT +⋅= (2)

( ))(142

*2 stuTTT −⋅+= (3)

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Instead, if the range for both carrier and reference signal is [-R; R], equations (2) and (3) become:

( ))(4

*1 stuR

RTT +⋅= (4)

( ) ( )[ ])(24

)(42

**2 ss tuRR

RTtuR

RTTT −+=−⋅+= (5)

which can be expressed also as:

( ))(4

1 *1 s

StuR

RfT +⋅= (6)

( ))(34

1 *2 s

StuR

RfT −⋅= (7)

As fig. 2 shows, this technique allows to generate a PWM signal with the desired duty cycle in which the low pulse is centered at the sampling instant. The duty cycle of the PWM output waveform varies in the range [-1; 1] as the reference signal goes from –R to R. Resolution α on the pulse width is given by the following formula:

sRf21=α (8)

3. RANDOM CENTER DISPLACEMENT PWM

The duty cycle of the switching signal does not depend on the location on the on-interval within the switching interval, i.e., the pulse position, nor on the length of the switching interval, i.e., the switching frequency. On the other hand, the presence of discrete harmonics in the spectrum is tied to periodical repetition of events. For these reasons, if either the pulse position or the switching frequency is varied in a random manner, the power spectrum of the output voltage of the converter acquires a continuous part, while the discrete (harmonic) part is significantly reduced. This is the basic principle of random pulse width modulation (RPWM) [1]. Several RPWM schemes are available, each with its set of advantages and disadvantages. The chosen scheme belongs to the family of fixed switching frequency techniques and it is referred to as Random Center Displacement (RCD) [2] or Random Pulse Position (RPP) [7]. Starting from a deterministic PWM waveform, which is e.g. left-aligned in the switching period, it consists in displacing the pulse center by a random amount TΔ from the alignment reference, as shown in fig. 3 for a signal with a constant duty cycle equal to 0.4.

u

0 T 2T 3Tt

Fig. 3. Typical Random Center Displacement waveform. This method is a variant of the random lead-lag (RLL) technique, which is simpler

because it consists of a random selection of only two possible positions, namely at the beginning or at the end of the interval.

To be coherent with the symmetrical regular sampling technique described in the previous section, it is possible to start from a deterministic PWM waveform whose low pulse is center-aligned in the switching period and then to apply the random displacement to the pulse position. To prevent overlap between consecutive PWM periods, it is required that the pulse displacement satisfies the following equation:

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dTT2

|| ≤Δ (9)

On the contrary, if the random displacement is applied to the high pulse position, to prevent overlap the following equation should be satisfied:

( )dTT −≤Δ 12

|| (10)

A practical RCD implementation could use a pseudo-random number generator whose output n is uniformly distributed. If, for example, ∈n [-100; 100], taking into account equations (9),(10) the pulse displacement could be determined as:

100/maxTnT Δ⋅=Δ (11)

where dTT2max =Δ or ( )dTT −=Δ 1

2max respectively.

4. CONTROL SCHEME FOR THE BUCK CONVERTER

The considered buck DC/DC converter was built for a previous work in order to measure and emulate the I-V behaviour of a photovoltaic array [15]. The rated power is about 3 kW and the design of the converter’s output filter was carried out so to obtain continuous-current conduction operation and output voltage ripple not exceeding a few percent. The above mentioned conditions led to choose the following values for the capacitor and the inductor: C=33 μF, L=3.7 mH. As for the power device, a power MESH IGBT was chosen in order to manage a maximum current of about 20 A. The converter was operated at constant switching frequency (10 kHz) and input DC voltage (250 V).

The present work proposes a general architecture which allows to control a buck converter by means of a conventional PID regulator in a closed-loop control system, as shown in fig. 4. Specifically, the algorithm is tested with the parameters expressed by (12), which correspond to a PI regulator designed with traditional methods [16] aimed to get suitable steady state error, bandwidth and stability margins.

0 ,22.0 ,002.0 === DIP KKK (12)

Fig. 4. Control scheme of the buck converter.

The output of the regulator, being the reference value for the duty cycle of the signal

which drives the IGBT of the converter, is saturated to a suitable range, namely [0.1; 0.9], to avoid the stall of the converter, i.e. a very long time interval during which the semiconductor device does not change state, due to a very high error signal.

The power switch is driven by either a deterministic or a random PWM signal,

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generated by the PWM modulator; its carrier frequency will be incremented to 25 kHz and made equal to the sampling frequency of the whole control system.

5. ALGORITHM IMPLEMENTATION

Aiming to test the algorithm on a starter board with an embedded Altera Cyclone III EP3C25F324 FPGA [17], it has been coded in VHDL and synthesized by using a software tool provided by the same manifacturer, i.e. Altera Quartus II [18]. In the following, the FPGA design flow is described. First, the design is coded and simulated to verify its correctness. Then the user assigns the pins of the FPGA chip by using the pin planner and invokes the logic synthesis: the software will optimize the design and will carry out the placement and routing automatically to generate the FPGA implementation file. Finally, the generated file can be downloaded to the FPGA for testing. This section explains the algorithm implementation, while the experimental set-up is fully described in section VI.

A modular architecture has been chosen, in order to build reusable blocks of code implemented as VHDL components. This has allowed also to verify individual components before integrating them into the closed-loop system and testing the final system on the experimental setup. The synopsis of the system is shown in fig. 5, in which the internal connections of clock and reset lines have been omitted for the sake of simplicity. Besides those which correspond to the control blocks of fig. 4, other components have been implemented, which allow additional features.

+-ADC interfacePID

controllersaturate

and scale

PWM generatorscale andapply offset

clockgenerators

SSD interfaceselect item

sel_ref

sel_disp

sel_random

output_pwm

pid_overflow

sclk (50 MHz)

ssd_addrssd_digitssd_dpssd_sign

adc_sclkadc_cs_nadc_dinadc_dout

square wavegenerator

selectreference

13

sampling_clkadc_clkdisplay_clkssd_clkpwm_clk

13

14

12

10 31 9

scaleand synch

1310

1310

reset inputs

rst_n

2

2

4

random numbergenerator

Altera Cyclone III EP3C25F324 FPGA

Fig. 5. Synopsis of the control system implemented on FPGA, with the I/O pin assignments. The select reference block, driven by the related input sel_ref, chooses whether the

reference voltage is equal to the value read by the first channel of the ADC, which is connected to an external potentiometer, or to the output of an internal 0.5 Hz square wave generator, in order to test the response of the system to a step input voltage. The ADC interface block allows the FPGA to be interfaced to a serial ADC located on an expansion board. Handshaking between FPGA and ADC is through four signals whose names are related to the peripheral, so that e.g. signal adc_dout goes into the FPGA.

A suitable block interfaces the FPGA to a 4-digit, 7-segment display (SSD), placed on a purposely designed board with a mechanical selector, connected to the sel_disp input, which allows to select the item to display (reference voltage or actual output voltage). The sel_random input allows to choose either deterministic or random PWM operation. Finally, two FPGA pins are connected respectively to the 50 MHz oscillator and to the reset button, which are located on the demo board. The following subsections describe thoroughly the implementation of the two main blocks of the control system (PID controller and PWM generator) and the various scaling blocks needed.

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A. PID controller The continuos-time transfer function of the PID regulator is given by (13), where KP, KI,

KD are the parameters of the controller, and E(s), V(s) denote the Laplace transforms of its input and output signals respectively.

sKs

KKsEsV

sG DIP ⋅+⋅+== 1)()(

)( (13)

In order to implement the control algorithm using digital technology, equation (13) has to be discretized [19]. Denoting the sampling period as T and using Euler’s backward approximation, the difference equations for the proportional, integral and derivative components of the PID regulator can be determined. If k denotes the k-th sampling instant and e(k), v(k) represent the sampled values of the input and output signals respectively, it is possible to say that:

)()()()( kDkIkPkv ++= (14) where:

( )⎪⎪

⎩

⎪⎪

⎨

⎧

−−=

⋅+−=⋅=

)1()()(

)()1()()()(

kekeT

KkD

keTKkIkIkeKkP

D

I

P

(15a,b,c)

Having obtained the discretized control algorithm, the focus is then placed on its efficient implementation. Since real numbers as defined in VHDL standard [20] are not synthesizable, two possibilities exist in order to manipulate such numbers: either to use nonstandard floating-point libraries (provided by FPGA manifacturers or self-written), or to use fixed-point notation. Aiming to make the software implementation simple, reusable with different sets of parameters and portable across different hardware devices, it has been decided to use fixed-point notation and to represent numbers using suitable scale factors.

The choice of signal width in fixed-point arithmetic is crucial in maintaining system stability. Even if a longer signal width reduces quantization effects, it results in an increase in hardware resources; on the other hand, a short signal width will affect the controller precision, causing an increase in control error or destabilization of the system [12]. In order to have a sufficient resolution, the range [-512; 511] has been chosen for the input signal of the PID controller. Instead, the coefficients of the PID regulator, multiplied by ten, can vary in the range [0; 255] so that the algorithm is able to implement a PID regulator with a set of actual coefficients in the range [0; 25.5] in 0.1 increments. Therefore, the following quantities can be considered:

DDIIPP KKKKKK ⋅=⋅=⋅= 10' ,10' ,10' (16) and substituted in equations (16a,b,c) so to obtain the equations to implement:

( )⎪⎪⎪

⎩

⎪⎪⎪

⎨

⎧

−−⋅⋅=⋅⋅

+−=

⋅=

−

−

)1()(10')(10

)(')1()(

10)('

)(

1

1

kekeTKkDT

keKkIkI

keKkP

D

I

P

(17a,b,c)

Referring to each fraction in (17a,b), it is worth noting that the product of the terms in the numerator should be calculated before performing the division by the denominator, in order to minimize the negative effect of the integer division.

The number of bits (nP) required to represent correctly the proportional output signal can be determined from (17a) by means of the following calculations:

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b)(18a, 1567.14log1 056,1351210255

max2max bitPnP P →=+==⋅=

As to (17c), remembering that e(k) is signed and that the sampling frequency is 25 kHz, it is possible to determine that nD=31. Equation (17b) for the integral part is recursive and it has a large denominator, thus some problems could arise. Firstly, if the absolute value of the input e(k) multiplied by 'IK is lower than the quantity 110 −⋅T , the second term in (17b) will be null due to the integer division and the integrator’s output will not increase nor decrease, in spite of a non-null input. Therefore it is convenient to define a new signal

)(10)( 1 kITkM ⋅⋅= − , so that (17b) can be written as: )(')1()( keKkMkM I ⋅+−= (19)

By choosing M(k) as the internal variable and by implementing (19) instead of (17b), the value of M(k) will increase or decrease correctly as e(k) varies. The output of the integrator, then, can be calculated as:

110)()( −⋅

=TkMkI (20)

The second problem is that signal M(k) could overflow. Therefore, the algorithm must include a check for this condition; specifically, in the proposed implementation, the maximum size allowed for VHDL signals has been chosen for M(k), i.e. 32 bit signed. Thus, by using (20), it is possible to determine that the number of bits required to represent correctly the integrator’s output signal is nI=15.

Finally, the three components will be summed according to (14), so the number of bits (nPID) required to represent correctly the PID output signal can be determined as follows:

( ) bitDIPnPID 3128.30log1 maxmaxmax2 →=+++= (21) In order to track past values of signals e(k) and M(k), two arrays have been used: a

2-elements, 10-bit array and a 2-elements, 32-bit array respectively. Each array acts like a shift register, since at each sampling instant a new element enters the array, the other ones are shifted back by one position and the oldest one exits the array.

In addition to what explained before, it is necessary to implement a suitable anti-windup action. It has been pointed out in section IV that the output of the PID regulator should be saturated to a suitable range to avoid the stall of the converter. Therefore, in order to keep the software as simple as possible, though effective, it has been chosen to use another saturator with the same limits applied to the integrator’s internal variable M(k) as an anti-windup technique.

B. PWM generator

The second main component of the control system is the PWM generator, which is able to generate both deterministic and random (RCD) PWM signals, as described in sections II and III. The parameter R for the symmetrical natural sampling technique has been set to 250, so that resolution on the pulse width is 80 ns, according to (8). Hence the reference signal u* will be represented with a signed 9 bit signal. The chosen sampling frequency is 25 kHz and it is equal to the theoretical carrier’s frequency.

A counter is needed to track time starting from the origin shown in fig. 2 (negative peak of the theoretical triangular carrier). Equations (6),(7) show that a remarkable simplification can be attained if the quantity

SRf41 is used as the timebase; this means that the PWM

clock, obtained by a division of the main 50 MHz clock, should be equal to SRf4 so there will be 4R ticks in a PWM period. Then the values which identify the switching instants will be expressed by the following simpler equations:

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)(' *1 stuRT += (22)

'4' 12 TRT −= (23) and they will belong to the following intervals: ]2;0['1 RT ∈ and ]4;2['2 RRT ∈ .

As to equation (23), it should be noticed that most compilers and synthesis tools will automatically optimize the calculation by substituting the product with shift and subtraction operations, as '2' 12 TRT −<<= , where << is the operator which shift the bits of R to the left (towards the MSB) by the specified amount. This comes in handy in order to save resources on the FPGA, or when the device does not have embedded hardware multiplicators.

As to the random modulation, the required pseudo-random number is obtained by means of a linear feedback shift register (LFSR), which is a shift register whose input bit is a linear function of its previous state [21]. The only linear function of single bits is XOR, thus the input bit is driven by an exclusive-OR of some bits of the overall shift register value. Since the register has a finite number of states, it must eventually enter a repeating cycle. However, an LFSR with a suitable length and a well-chosen feedback function can produce a sequence of bits which appears random and which has a very long cycle (max.

12 −N states). The bits which influence the input of the LFSR are called taps. Using the Fibonacci

implementation, the taps are XOR’ed sequentially with the output bit and then fed back into the leftmost bit, as shown in the example of fig. 6. The arrangement of taps is generally expressed as a polynomial mod 2, i.e. a polynomial whose coefficients can be either 1 or 0. For example, if the taps are those of fig. 6, the primitive polynomial is x16+x14+x13+x11+1, where the final one corresponds to the input to the first bit (i.e. x0, which is equivalent to 1). Another way to express the sequence of taps is through feedback sets, which omit the final unit term, e.g. [16, 14, 13, 11] for the LFSR of fig. 6.

Fig. 6. A 16 bit Fibonacci LFSR.

A maximal-length N-bit LFSR is an LFSR which cycles through all possible 2N − 1

states within the shift register except the state where all bits are zero, unless it contains all zeros, in which case it will never change. Tables of primitive polynomials for maximal-length LFSRs are given in [21]. It is worth noting that there can be more than one maximal-length feedback set for a given LFSR length and that, if [m, A, B, C] is one of them, the corresponding reversed mirror sequence [m, m-C, m-B, m-A] is also a maximal-length feedback set.

Summing up, a N-bit maximal-length LFSR is able to generate a uniformly distributed pseudo-random number in the range [1; 2N-1]. It has been implemented in VHDL by means of an unsigned, N bit, std_logic_vector variable, named lfsr_int and initialized to an all-ones configuration. However, a percentage in the range [-100; 100] is needed for the implementation of the chosen RPWM algorithm, according to (11). Therefore a random integer rand_int is obtained by subtracting the quantity 2N-1 from lfsr_int. Thus the range for rand_int is [-(2N-1-1); 2N-1-1], which includes zero and is symmetrical around it.

Then a random shift amount for the PWM pulse can be calculated and expressed as a percentage as follows:

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12100int_

1 −⋅= −N

randdeltaT (24)

The central low pulse can be shifted towards both directions by moving the position of the falling and rising edge, i.e. T1’ and T2’ respectively, by the same amount dT. The maximum amount is equal to the actual value of T1’. Hence the actual random amount, expressed in ticks, is given by:

100'1TdeltaTdT ⋅= (25)

By putting together (24) and (25), a simple expression can be obtained for determining dT in a single passage:

12'int_

11

−⋅= −NTranddT (26)

Again, the product of the terms in the numerator should be calculated before performing the division by the denominator. Since the maximum size allowed for VHDL signals is 32 bit signed, in order not to cause an overflow it should be 31

max1max 2'int_ <⋅Trand , which implies:

1122log

31

2 +⎟⎟⎠

⎞⎜⎜⎝

⎛+<

RN (27)

Referring to the implemented code, having chosen R=250, equation (27) reduces to N<23.03. Hence a 23 bit maximal-length LFSR is needed. One of the related primitive polynomials is defined by coefficients [23, 22, 21, 16]. Observing that the bit numbering of the std_logic_vector variable is opposite to the convention for taps numbering, the variable lfsr_int will be updated with the following VHDL assignment:

lfsr_int := (lfsr_int(0) xor lfsr_int(1) xor lfsr_int(2) xor lfsr_int(7)) & lfsr_int(lfsr_int'left downto 1);

Summarizing, at every increment of the variable t which tracks time, the following

operations are executed: • if t reaches the quantity 4R, i.e. at every sampling instant, it is reset to zero and the

values of lfsr_int and rand_int are updated; • the values of T1’ and T2’ are calculated according to (22) and (23); • if the sel_random input is high, the quantity dT is calculated with (26) and the

values of T1’ and T2’ are updated by adding dT to them; • the output PWM signal is set low if '' 21 TtT <≤ or high otherwise.

C. Scaling blocks As stated before, blocks ADC interface, PID controller and PWM generator have been

implemented as independent and reusable components. Therefore suitable scaling operations are needed in order to match the output of each component to the input of the one which comes after in the synopsis of fig. 5.

Considering the gain of the signal conditioning circuit described in the following section, the 10-bit output of the ADC interface block has to be multiplied by S1=250/48 in order to obtain the actual value of voltage signals. Scale factor S2=512/100 maps the input range of the PID controller to the range of the actual voltage error signal, multiplied by ten in order to increase its resolution and limited to the range [-100; 100], i.e. [-10 V; 10 V]; this means that the PID controller can sense actual voltage errors of at least ±0.1 V. Since the input signal has been multiplied by ten, the value of the PID output signal will have the same scaling and the inverse mapping should be applied (S3=100/512). The latter signal

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would be equal to the reference duty cycle multiplied by ten if the parameters (12) of the designed PID regulator belonged to the range [0; 25.5]. Since this is not true, the following parameters have been chosen for the implemented PID code:

⎪⎩

⎪⎨

⎧

=⋅=

=⋅==⋅=

0100

221002.0100

*

*

*

DD

II

PP

KK

KKKK

(28)

so that the PID output signal will be equal to the reference duty cycle multiplied by 1000. Therefore a scaled reference duty cycle in the range [-100; 100] is obtained by changing the scale factor to S3’=10/512. However, the input range for the PWM generator block is [-250; 250]. Therefore, a suitable mapping is required to pass the PID output to the input of the PWM generator: first the signal is multiplicated by S3”=500/100; then an offset O=-250 is added to it. Finally, scale factors S3’ and S3” can be combined in a single scale factor S3’”=S3’·S3”=50/512.

6. EXPERIMENTAL SET-UP AND RESULTS

The experimental set-up has been devised around a starter board with an embedded Altera Cyclone III EP3C25F324 FPGA [17]. This device is driven by an onboard 50 MHz oscillator and presents the following features: 25K logic elements, 66 blocks of M9K memory (0.6 Mbits), four PLLs, 214 I/O ports. Main features of the board are low cost, low power consumption, onboard SDRAM, SSRAM and EEPROM devices and High Speed Mezzanine Card (HSMC) connector, which allows the connection of a variety of expansion boards. An additional advantage is the onboard USB-Blaster programmer which allows to transfer the generated code to the FPGA via a USB connection by means of the JTAG protocol.

For this project a Nial Stewart GPIB expansion board [22] has been used which features several I/O connectors with bidirectional 3.3V-5V level shifters and, among other peripherals, an 8-channel, 10-bit, serial analog-to-digital converter (ADC), namely an AD7918 from Analog Devices [23], with an internal reference voltage of 2.5 V.

The level shifters of the Nial Stewart board allowed the FPGA to be interfaced to the control input of the buck DC/DC converter which has been described in section IV, and to the purposely designed SSD board, as stated in section V. These devices, in fact, work with standard TTL signals, while the FPGA uses 3.3V CMOS signals.

The output of the DC/DC converter is connected to a set of load resistors (150 Ω, 1 kW) and to another purposely designed electronic board, which encompasses an LV25-P voltage transducer and all the analog circuitry needed for signal conditioning: supply and load circuits for the transducer, an anti-aliasing filter for its output voltage and an op-amp connected to a 2.5V voltage reference to adapt the filtered signal to the input range of the ADC (0÷5V). Channel 2 of the ADC is used for acquiring the converter’s output voltage signal, while channel 1 is connected to an external 1 kΩ linear multi-turn potentiometer, for a fine tuning of the voltage set-point. Finally, a programmable TDK-Lambda GEN600-5.5 3.3 kW power supply is used to apply a constant voltage (350 V) to the input of the buck converter.

Figure 7 shows the main components of the experimental set-up, while fig. 8 shows a zoom on the electronic boards.

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Fig. 7. Main components of the experimental set-up. Fig. 8. A zoom on the electronic boards.

The performance of the implemented control system has been verified by acquiring the

waveform of the converter’s output voltage for a step variation of the set-point between 50 V and 250 V, generated by the 0.5 Hz square wave generator implemented inside the FPGA. This task has been accomplished by means of an Agilent MSO6104A 4 Gsamples/s scope. The system exhibits good closed-loop performance, with acceptable rise time and steady-state precision, as shown in fig. 9a,b. In addition, it can be noticed that the voltage ripple is slightly larger for random PWM than for deterministic PWM because of the extra low-frequency components added by RPWM, as demonstrated in [6]-[7].

-0.5 -0.25 0 0.25 0.5 0.75 1 1.25 1.5 1.75 20

0.5

1

1.5

2

2.5

3

3.5

outp

ut v

olta

ge [

10-2

V]

time [s]-0.5 -0.25 0 0.25 0.5 0.75 1 1.25 1.5 1.75 20

0.5

1

1.5

2

2.5

3

3.5

time [s]

outp

ut v

olta

ge [1

0-2 V

]

(a) (b)

Fig. 9. Response of the DC/DC converter to a step input voltage: (a) deterministic PWM; (b) random PWM. In order to verify the performance of the random PWM implementation, the same scope

allowed to acquire the waveform of two meaningful electric signals: the AC component of the generated PWM signal, referred to as d, and the ripple on the output voltage of the DC/DC converter, denoted by v. Then the power spectrum density (PSD) of each signal has been determined and plotted by means of a suitable script in the Matlab® environment, based on Welch’s method with a modified Hanning window [24]. The equivalent bandwidth of the window is 4.46 Hz, much smaller than the value (100 Hz) used for determining the spectra reported in [7]. Aiming to obtain a spectrum with an accuracy of 10%, extended up to 1 MHz in order to check a large part of the range related to conducted EMI, a sampling frequency of 2 MHz has been used and the length of the time history has been chosen to be 225 due to hardware limits.

Figures 10a÷d show the PSD of signals d and v, denoted by Sd and Sv respectively, when the duty cycle is set to 0.1, with deterministic (left) and random (right) modulation.

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Spectrum Sd for deterministic PWM shows the harmonic energy concentrated around the switching frequency (fs=25 kHz) and its multiples. As fig. 10c shows, random modulation is able to reduce the harmonics of the switching frequency consistently, by spreading their power content on the whole frequency range. The drawback is an increase in the amplitude of the low frequency components of the spectrum and a small increase of the background noise level. Furthermore, since RCD is a fixed switching frequency technique, the continuos part of the spectrum presents characteristic lobes. Spectrum of fig. 10c exhibits a reduction of the amplitude starting from the third harmonic. Harmonics of order 10·k are absent since they are masked by the background noise.

A greater reduction of the harmonic content is produced on the voltage spectrum. By comparing fig. 10b and fig. 10d it can be noticed that harmonics are absent starting from the 8th and that attenuations up to -23 dB are attained for harmonics of order 10 and 11. It is worth noting that, besides multiples of the switching frequency, fig. 10b,d show the presence of distinct peaks due to noise coming from the power supply, which cannot be reduced by means of random modulation techniques. This aspect will be addressed in the last part of this section.

0 100 200 300 400 500 600 700 800 900 1000-80

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0 100 200 300 400 500 600 700 800 900 1000-110

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Frequency [kHz]

Sv(f

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(b) (d)

Fig. 10. PSD of PWM switching function (top) and output voltage (bottom) with duty cycle equal to 0.1, without (left) and with (right) random PWM.

Similar comments can be made to fig. 11a÷d, which show the PSD of signals d and v

when the duty cycle is set to 0.8, with deterministic (left) and random (right) modulation. Fig. 11a, compared to fig. 10a, shows an increase of peak levels and the presence of

interharmonics at multiples of 2sf . Instead, the spectrum of fig. 11c presents lobes with a different width and shows a higher reduction of the harmonic content, compared to fig. 10c. This can be explained by observing that the implemented algorithm alters the position of

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the low pulse of the PWM signal, instead of the high pulse. Thus, when the duty cycle is higher there is more room to move the low pulse inside the switching period. On the contrary, if an algorithm is used which moves the high pulse, a lower duty cycle will correspond to a more effective harmonic reduction, as stated in [2] and demonstrated experimentally in [4],[10]. This behaviour allows to design the algorithm on the basis of the expected range for the duty cycle.

Harmonics of order 6, 12, 21, 28, 32, 37 and higher are absent in the spectrum of fig. 11c since they are masked by the background noise. Furthermore fig. 11d shows a severe reduction of the harmonic content of Sv, since harmonics are absent starting from the fourth, with a maximum attenuation of –23 dB.

0 100 200 300 400 500 600 700 800 900 1000-80

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0

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) [d

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(a) (c)

0 100 200 300 400 500 600 700 800 900 1000-110

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0 100 200 300 400 500 600 700 800 900 1000-110

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Frequency [kHz]

Sv(f

) [d

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(b) (d)

Fig. 11. PSD of PWM switching function (top) and output voltage (bottom) with duty cycle equal to 0.8, without (left) and with (right) random PWM.

In order to document the noise coming from the power supply, fig. 12a,b can be

examined. In particular, fig. 12a shows the PSD of the power supply’s output voltage, acquired while it is connected to the load directly, without the DC/DC converter interposed; fig. 12b, instead, shows the PSD of the DC/DC converter’s output voltage, acquired while it is connected to power supply and load, being driven by a signal with unity duty cycle.

The noise peaks which are present in the spectra of fig. 10c,d and fig. 11c,d are those whose amplitude is equal or greater than –106 dB, which is the background noise level of those spectra. Besides frequencies in the set [152.7, 305.4, 650.5, 698.9 kHz] which are highlighted in fig. 12b, additional peaks at fr=3.6 kHz and 2fr should be considered, i.e. the switching frequency of the power supply and its second harmonic. They are shown clearly in fig. 13, which represents a zoom of fig. 12b for frequencies up to 15 kHz. It’s worth noting that the small amplitude of the peak at 305.4 kHz in fig. 11d is not an effect of the random modulation, as this peak is small also in fig. 11c. As a final consideration, it can be

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observed that an additional peak at f0=6.24 kHz is present in the spectra of fig. 10b, 11b, 11d, which causes also interharmonics at ±k·f0 around some harmonics in fig. 10b and 11b.

0 100 200 300 400 500 600 700 800 900 1000-130

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Sv(f

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Frequency [kHz]

Sv(f

) [d

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152.7 kHz

305.4 kHz

698.9 kHz

650.5 kHz

(a) (b)

Fig. 12. (a) PSD of power supply’s output voltage; (b) PSD of DC/DC converter’s output voltage, driven with unity duty cycle.

0 5 10 15-130

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Frequency [kHz]

Sv(f

) [d

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7.2 kHz

10.8 kHz

Fig. 13. A zoom of fig. 12b for frequencies up to 15 kHz.

7. CONCLUSIONS

A real-time, modular and compact architecture has been proposed for the FPGA-based random PWM control of the output voltage of a buck DC/DC converter. The Random Center Displacement (RCD) technique has been discussed and a RCD controller algorithm has been proposed, integrated into a PID-driven digital feedback control system and tested using a commercial FPGA. The design has a modular approach so that some modules, implemented as VHDL components, can be reused in other applications. Furthermore, a major effort has been placed on the hardware optimization by working in fixed-point arithmetic and by choosing properly the signal width, so that the system exhibits low cost, high speed and low power consumption, which is desirable in embedded control applications.

The design has been successfully simulated, synthesized and tested for real-time performance on an experimental set-up devised around a starter board with an embedded Altera Cyclone III FPGA. Experimental tests have shown that it offers good closed-loop performance with acceptable rise time and steady-state precision, and that the voltage ripple is slightly larger for random PWM than for deterministic PWM, as expected.

Finally, an accurate power spectral density of the AC component of two meaningful electric signals (PWM signal and converter’s output voltage) has been presented and discussed, showing the validity of the implementation and the advantages of RPWM over

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deterministic PWM. Issues as noise coming from the power supply, which cannot be reduced by means of random modulation techniques, have been discussed as well.

References [1] A. M. Trzynadlowski, F. Blaabjerg, J. K. Pedersen, R. Lynn Kirlin, S. Legowski, “Random Pulse Width

Modulation Techniques for Converter-Fed Drive Systems-A Review”, IEEE Transactions on Industry Applications, vol. 30, no. 5, September / October 1994.

[2] M. M. Bech, “Analysis of Random Pulse-Width Modulation Techniques for Power Electronic Converters”, Ph.D. Thesis, Aalborg University, Institute of Energy Technology, 2000.

[3] S. Berto, S. Bolognani, M. Ceschia, A. Paccagnella, M. Zigliotto, “FPGA-Based Random PWM with Real-Time Dead Time Compensation”, Proc. of 34th Annual Power Electronics Specialist Conference (PESC 2003), vol. 2, pp. 513-518, June 2003.

[4] M. M. Bech, F. Blaabjerg, J. K. Pedersen, “Random Modulation Techniques with Fixed Switching Frequency for Three-Phase Power Converters”, Proc. of the 30th IEEE Power Electronics Specialists Conference, vol. 1, pp. 544-551, June 1999.

[5] A. M. Stanković, G. C. Verghese, D. J. Perreault, “Analysis and synthesis of randomized modulation schemes for power converters”, IEEE Transactions on Power Electronics, vol. 10, no. 6, pp. 680-693, November 1995.

[6] S. Y. R. Hui, Y. Shrivastava, S. Sathiakumar, K. K. Tse, H. S. H. Chung, “A Comparison of Nondeterministic and Deterministic Switching Methods for DC–DC Power Converters”, IEEE Transactions on Power Electronics, vol. 13, no. 6, November 1998.

[7] K. K. Tse, H. S. H. Chung, S. Y. R. Hui, H. C. So, “A Comparative Investigation on the Use of Random Modulation Schemes for DC/DC Converters”, IEEE Transactions on Industrial Electronics, vol. 47, no. 2, pp. 253-263, April 2000.

[8] T. Tanaka, T. Ninomiya, K. Harada, “Random-switching control in DC-to-DC converters”, Proc. of the 20th IEEE Power Electronics Specialists Conference, vol. 1, pp. 500-507, 1989.

[9] A. Wang, S. R. Sanders, “Random and Programmed Pulse-Width Modulation Techniques for DC-DC Converters”, IEEE International Symposium on Systems Engineering, pp. 589-592, 1990.

[10] M. M. Bech, F. Blaabjerg, J. K. Pedersen, A. M. Trzynadlowski, “Comparative Investigation of Random PWM Techniques with Variable Switching Frequency and Pulse Position for Inverter-Fed Induction Motors”, Proc. of 7th European Conference on Power Electronics and Applications, vol. 1, pp. 343-349, 1997.

[11] W. Wolf, Computers as Components: Principles of Embedded Computing System Design, San Francisco, Morgan Kaufman, 2001.

[12] Y. F. Chan, M. Moallem, W. Wang, “Design and implementation of modular FPGA-based PID controllers”, IEEE Transactions on Industrial Electronics, Vol. 54, no. 4. (2007), pp. 1898-1906.

[13] A. Fratta, G. Griffero, S. Nieddu, “Comparative analysis among DSP and FPGA-based control capabilities in PWM power converters,” Proceedings of the 30th Annual Conference of the IEEE Industrial Electronics Society (IECON ’04), pp. 257–262, Novemeber 2004.

[14] J. Holtz, “Pulsewidth modulation for electronic power conversion”, Proceedings of the IEEE, vol. 82, no. 8, August 1994.

[15] M. C. Di Piazza, G. Vitale, “Photovoltaic field emulation including dynamic and partial shadow conditions”, Applied Energy, vol. 87, issue 3, March 2010, pp. 814–823.

[16] N. Mohan, T. Underland, W. Robbins, Power Electronics. New York: Wiley, 1995. [17] Altera. Cyclone III FPGA Starter Board Reference Manual. October 2007.

http://www.altera.com/products/devkits/altera/kit-cyc3-starter.html [18] Altera. Introduction to the Quartus® II Software. Version 9.1.

http://www.altera.com/products/software/quartus-ii/web-edition/qts-we-index.html [19] W. S. Levine (editor), The Control Handbook, CRC Press-IEEE Press, 1996, Chapter 13: Discrete-time

equivalents to continuous-time systems, Authors: M. S. Santina, A. R. Stubberud, G. H. Hostetter. [20] VHDL Standard - IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis (1076.6-1999). [21] F. J. MacWilliams, N. J. A. Sloane, “Pseudo-Random Sequences and Arrays”, Proceedings of the IEEE,

vol. 64, no. 12, pp. 1715-1729, December 1976. [22] Nial Stewart Developments Ltd. HSMC General Purpose Interface Board (GPIB) User Guide.

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