bhadresh_patel_pd_trainee_engineer

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RESUME Bhadresh A. Patel B.E. (Electronics & Communication) Ahmedabad Institute of Technology, Ahmedabad E-MAIL ID: bhadreshpatel asic@ gmail.com PHONE NO: (M) +91 9148445872 CAREER OBJECTIVE To work hard with full determination and dedication to achieve organizational as well as personal goals. Looking for an ASIC Physical Design Engineer position with company in which my training can be used to help the business advance and meet goal where I can learn and grow. ACADEMICS CREDINTIALS Standard Board/University Year CGPA/% BE ECE GTU 2012-2016 6.4 H.S.C GSHEB 2011-2012 68.17% S.S.C GSHEB 2009-2010 74.00% PROJECTS: 1. eITRA, eInfochips Training Projects (Duration 6 Months) Linux: Learned about Linux operating system, directory structure, commands. Basic knowledge of Shell script, tcl scripting, Perl scripting. Verilog RTL coding o Developed a Verilog rtl code for parking lot occupancy counter. Basic understanding of DFT. Synthesis o Basic understanding of synthesis for chiptop RTL using constraint file for 90nm technology. o Tool: Synopsys Design Compiler STA o Performed STA analysis for chiptop netlist. o Technology: 90nm o Tool Used: Synopsys Prime Tool. PnR o Floor Planning: Performed a macro placement, IO placement, Standard cell placement, Define Blockage area.

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Page 1: Bhadresh_Patel_PD_Trainee_Engineer

RESUME

Bhadresh A. Patel B.E. (Electronics & Communication) Ahmedabad Institute of Technology, AhmedabadE-MAIL ID: bhadreshpatel asic@ gmail.com PHONE NO: (M) +91 9148445872

CAREER OBJECTIVE

To work hard with full determination and dedication to achieve organizational as well as personal goals. Looking for an ASIC Physical Design Engineer position with company in which my training can be used to help the business advance and meet goal where I can learn and grow.

ACADEMICS CREDINTIALS

Standard Board/University Year CGPA/%BE ECE GTU 2012-2016 6.4

H.S.C GSHEB 2011-2012 68.17%

S.S.C GSHEB 2009-2010 74.00% PROJECTS:

1. eITRA, eInfochips Training Projects (Duration 6 Months) Linux: Learned about Linux operating system, directory structure, commands. Basic knowledge of Shell script, tcl scripting, Perl scripting. Verilog RTL coding

o Developed a Verilog rtl code for parking lot occupancy counter. Basic understanding of DFT. Synthesis

o Basic understanding of synthesis for chiptop RTL using constraint file for 90nm technology.

o Tool: Synopsys Design Compiler STA

o Performed STA analysis for chiptop netlist.o Technology: 90nm o Tool Used: Synopsys Prime Tool.

PnRo Floor Planning: Performed a macro placement, IO placement, Standard cell

placement, Define Blockage area.o Power planning: Created Rings, Stripes, and Rails. Checked the IR drop and

EM.o Placement: Performed place_opt, generated conjunction report and applied

an optimization techniques.o Clock Tree Synthesized: Analyzed clock timing report for skew, latency,

setup and hold timings, Area and Power report and applied a clock optimization techniques.

o Routing: Performed routing steps. Analyzed conjunction report.

Page 2: Bhadresh_Patel_PD_Trainee_Engineer

o Tool used: IC Compiler. Physical Verification of netlist:

o Performed a Design Rule Check (DRC), Electronics Rule Check (ERC), IR drop, LVS check, Logical Equivalence Check (LEC).

o Tool used: IC Compiler.2. I-Car (Face detection using raspberry pi-camera) (SEM VII)

The project was to develop a face detector device to be use in car and other vehicles. Hardware used: pi-camera, raspberry pi b+ model, servo motor.

3. To  convert AC to DC, (SEM III)Developed a mini project to convert AC signal to DC signal using bridge rectifier to be used as a provide DC power supply to IC.

AREA OF INTEREST Digital Logic Design Programming in C Microprocessor CMOS

SEMINAR Linux Grep command Types of simulators Synopsys IC tool introduction and process Physical design flow

STRENGTHS

Flexibility and Adaptability Ability to work under sheer pressure. Positive attitude Dedication to my work Ability to Communicate with others effectively

PERSONAL DETAILS

Father’s Name - Aravindbhai Patel Date of Birth - 24/02/1994 Marital status - Single Hobbies - Drawing, Playing Cricket, Listening a music.

DECLARATIONI hereby solemnly declare that the above mentioned information is correct up to my knowledge and I bear the responsibility.

Bhadresh Patel