eFLASH Optimization in SOCsReliability Enhancement

12

B. GODARD 1 2

Encadrants :

JM. DAGA 2

L. TORRES 1

G. SASSATELLI 1

2

Thesis Context

Flash Memory Resources Optimization in SOCs Comparison between non-volatile memories technologies Applications needs Ways to optimize in term of

Performances, Power consumption, Density, Cost, Flexibility, …

Emerging field: Yield/Reliability Redundancy architectures for yield Error Correction techniques (ECC) for reliability

Today, mixed methodology to further enhance reliability / yield

3

Summary

eFLASH overview

Reliability issues

Enhancement methodology and architecture

Mathematical modeling and gain

Conclusions & Discussions

4

Summary

eFLASH overview

Reliability issues

Enhancement methodology and architecture

Mathematical modeling and gain

Conclusions & Discussions

5

Flash Memory Overview

$0

$4,000

$8,000

$12,000

$16,000

$20,000

$24,000

$28,000

1998 1999 2000 2001 2002 2003 2004 2005 2006 2007

Millio

ns o

f Do

llars

non-Flash MCU $M Flash MCU $M

Flash memory market is continuously growing

More and more memory in SOC (SIA roadmap : 94% area in 2014)

Technology shrinks

Reliability requirements are increasing (1ppm objective for automotive products)

CPU Core

Advanced Interrupt

Controller

Bridge

system bus

On-chip Peripherals

eSRAM

peripheral bus

External Bus

Interface

External Memories

External Peripherals

eFLASH

1. eFLASH overview

6

The Floating Gate Concept

Mode Select Gate

Control Gate

Drain

Erase (write 1)

VM VM 0

Program (write 0)

VM 0 VM

Read VDD Vsense 0

BN+

Select Gate (WL)

Control Gate

GND

Drain (BL)

~12 V

0V

VM0 V

VMVMVM

0V

BN+

Select Gate (WL)

Control Gate

GND

Drain (BL)

~12 V

0V

VM0 V

VMVMVM

0V

VM : High Voltage Programming (~14 to 17V) VCS

Programmed

VtP VtE

IDSQ=0 Q>0

Erased

Vsense

Read T

hreshold

Cell Cell

Flotox architecture

1. eFLASH overview

7

Flash Memory Architecture

An embedded flash memory is an Embedded Flash Controller (test, security, access mode,

additional features…) a Flash Memory Module

Flash

Memory Module

Embedded Flash

Controller

BUS

din

dout

rdbsyn

add

CTRL

TI

Synchronous Synchronous

or Asynchronous

Command interface

Program erase controller

Charge pump & regulators

Glue logic

IO Buffers

Program loads

SA

Column multiplexer

Flash Array

Row De c o d e r

Address latch & counter

Column decoder

Address Buffer

Address input

Data Pins

1. eFLASH overview

8

Flash Memory Module

Command interface

Program erase controller

Charge pump & regulators

Glue logic

IO Buffers

Program loads

SA

Column multiplexer

Flash Array

Row De c o d e r

Address latch & counter

Column decoder

Address Buffer

Address input

Data Pins

1. eFLASH overview

9

Summary

eFLASH overview

Reliability issues

Enhancement methodology and architecture

Mathematical modeling and gain

Conclusions & Discussions

10

Electronic Product Lifecycle

Techniques to improve Yield (Redundancy architecture) Reliability (Error Correcting Codes)

But… All redundancy not always used Weakest bits are not always detected during test

Time

Fai

lure

Rat

e λ(

t)

Infant Mortality

Wearout Steady State

Constant Failure Rate

Operating Time Fab. Time Obsolete

Yield Reliability

2. Reliability issues

11

Reliability Characteristic

Retention (>10 years without memory loss)

Problem of Erratic and tail bits : Bit whose Vt change after some hours (random p = 10-6)

Endurance (Nb. of write-erase performed before the first memory error)

Improve max endurance to target automotive products

Cycles

Vt

101 102 103 104 105 106

Vt windows

One bit fail margin fail the entire chip

2. Reliability issues

Vt

# Cell

Vt windows

Vt evolution of bits with time

12

Summary

eFLASH overview

Reliability issues

Enhancement methodology and architecture

Mathematical modeling and gain

Conclusions & Discussions

13

Mixed Approach For Reliability

Objective Propose a new design and methodology using ECC and/or

redundancy to improve the reliability.

Constraints Use the specificity of eFLASH

Page Program/Erase oriented memory Analog states

Minimize impact on application (timing, power consumption, area)

Hypothesis Only one error can occur at time

3. Enhancement Methodology and Architecture

14

Reliability Enhancement Techniques

Error Detection and localization Post Write/Erase Comparison Analog Level Checker On line detection with ECC

Fault Tolerance Mechanism Error Correction Redundancy Repair Refresh Analog States

User policy to limit the impact on application Repair on error Delayed repair Scrubbing method

3. Enhancement Methodology and Architecture

15

Redundancy Architecture

Principle Replace the faulty elements

of the main array with a fault free elements of redundancy

Objective Make the logical matrix array

fault free

Architecture Need to implement

additional pages and reconfiguration logic (CAM)

3. Enhancement Methodology and Architecture

16

ECC Architecture

Pa

rity

Parity Generator

Info

rma

tion

Coding

Memory Storage

Errors k p

Parity Generator

Decoding

LUT

k

p

k p

Detect

Locate

Correct

k Principle calculate and store a parity

check information

Objective Correct discrete random

memory failures

Encoder/Decoder Correct 1 error/word or Detect 2 errors/word

Architecture Need to extent memory array

to store parity Ex : 32 bits + 7 parity = 20%

overhead

3. Enhancement Methodology and Architecture

17

Analog Level Checker: Vt Analysis

A read is made with a Vread low and a Vread high, the results are compared to detect errors.

Not used in normal mode due to timing overhead. During scrubbing, cell with Vt in the forbidden zone are detected

Vt

# Cells

Vread

Erased Cells

ProgrammedCells

select transistor

Bitline

memory transistor

Vread

Forbidden

zone

3. Enhancement Methodology and Architecture

18

Example Of Reliability Policy

Timing Diagram

While there is redundancy Normal operation : on-line error detection and correction

If error on write/erase : problem of endurance If error on read : problem of retention Replace with row redundancy

Scrubbing : Error detection, Analog state analysis, If error or weak bits : problem of retention Replace with row redundancy

If no redundancy : on-line error detection and correction only

time

ScrubNormal

operation

3. Enhancement Methodology and Architecture

19

Reliability Logic Wrapper

ECC and Redundancy Reliability Logic Wrapper

3. Enhancement Methodology and Architecture

20

Summary

eFLASH overview

Reliability issues

Enhancement methodology and architecture

Mathematical modeling and gain

Conclusions & Discussions

21

The Former Example

100 %99 %0%Reliability Rate

(0ppm would mean 100%)

ECC used when there is no more redundancy row. The scheme

prevent from errors undetectable during test

One redundancy line does not serve and ECC capacity

correction begins to decrease

unnecessarily

Not efficientCommentary

100 % (ECC)99 % (ECC)0%On 2nd Rel. Error

100 % (Red.)100 % (ECC)0%On 1st Rel. Error

100 %100 % 100% Repair Rate

100 % (Red.)100 % (Red.)100 % (Red.)On 2nd Yield Error

100 % (Red.)100 % (Red.)100 % (Red.)On 1st Yield Error

Red. for Yield & Rel.

ECC for Rel.

Red. for Yield

ECC for Rel. Red. for YieldFor What ?

ECC + Red.ECC + Red.RedundancyArchitecture

100 words

1 word = 1 row

4. Mathematical Modeling and Gain

22

Reliability Evaluation

0 5 0 1 0 0 1 5 0 2 0 0 2 5 0 3 0 00

0 . 2

0 . 4

0 . 6

0 . 8

R t( )

R E C C t( )

R r e d t( )

R a r r a y t( )

t

1 Mbits Array

ECC

5 red. rows

Error Probability = 10-6

ECC + Red

ECC

Red

Nothing

Mean time to failure gain:

Time to failure gain to have 1 defective memory among 1000 (R=99.999%):

100%

80%

60%

40%

20%

0%

Rel

iab

ilit

y

Time (au)

%2 3.5+=+

E C C

R E DE C C

M T T F

M T T F

%5.1 2 9+=+

E C C

R E DE C C

T T F

T T F

4. Mathematical Modeling and Gain

99.999%

23

Summary

eFLASH overview

Reliability issues

Enhancement methodology and architecture

Mathematical modeling and gain

Conclusions & Discussions

24

Conclusions and Discussions

Topic identified : RELIABILITY Automotives objectives, reliability growing constraints. Architecture not optimized (separated use of ECC and redundancy).

New reliability enhancement methodology developed Combines 1 Error Correction Code and redundancy. Uses specificity of Flash : Analog Level Checker.

Other methodologies can be implemented Online correction and repair using error detection mechanism, analog level

checker and redundancy.

Future work Depending on the application needs, formalize the architecture and methodology

to use Evaluate cost / performance (area, timing, power consumption)

eFLASH Optimization in SOCsReliability Enhancement

12

B. GODARD 1 2

Encadrants :

JM. DAGA 2

L. TORRES 1

G. SASSATELLI 1

Architecture Performances

Examples 1Mbits = 32 bits x 32768 words, 1024 pages, 64 words/page Tread = 20ns, Tload = 20ns Twrite_page = 2ms, Twrite_fuse = 1ms

ECC Timing : Transparent for user, + 10% Tread (few ns) Area : Overhead +20%

Redundancy Area : Overhead < 3%

Repair Procedure Timing : Trepair = 10 ms to write 10 fuses + ~2 ms to write page

Scrubbing Timing : Tscrub = 1.31 ms to make Vt analysis

23rd IEEE VLSI Test Symposium May 1-5, 2005 – Palm Springs, CA, USA