basic eft emc guideline

TMFreescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc.

FTF-ENT-F0779

Basic EFT/EMC Guidelines

June, 2010

Michael SteffenSenior Field Applications Engineer

TMFreescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc. 22

How good is your susceptibility?


GOFSL

G – Ground and Power Planes O – Oscillator layout F – Filtering S – Software Techniques L – LUCKY!!!!!!!


Meet Michael

Freescale Field Apps Engineer 8-bit/Sensor Specialist EMC/EFT Specialist Appliance EMC Expert 12+ years Design Engineer 10+ Years in Appliance and Customer MCU applications EMC Global Swat Team Member Published Authored Several Application Notes Consulted/Troubleshot EMC designs for many Major appliance companies


Agenda

EMC OverviewStandards and Test MethodsSystem Design Best Practices

• Review Theory• Guidelines• Hardware Design Methodology• Customer Examples• Software Best Practices• References


EMC/EFT Overview


What is EMC?

Electromagnetic Compatibility (EMC) Definition• Ability of an electronic system/device to function satisfactorily in an

electromagnetic environment without introducing intolerable electromagnetic disturbances to anything in that environment

• Every system that generates, consumes, modifies or processes electrical power/signals generates electromagnetic emissions and is susceptible to electromagnetic disturbance

Presenter

Presentation Notes

Check out FCC Part 15 warning on any electronic piece of equipment


Basic EMC Categories

Components of an EMC issue• Source (a perpetrator)• Medium • Receiver (a victim)

Noisy component

Noisy component

Conducted Emissions

Conducted Susceptibility

Potentiallysusceptible component

Radiated Emissions

Radiated Susceptibility

Potentiallysusceptible component

Four basic EMC categories, combinations of:• Radiated (air)/Conducted (physical medium)• Emissions (out)/Susceptibility (in)


Freescale’s Efforts to Enable Customers to Meet EMC Standards

Incorporate design methods• Minimize emissions, strengthen immunity in supplied MCUs

Test EMC on MCUs• Capture data for customer communications• Insure certain minimum criteria achieved

Respond to EMC questions/issues from applications using Freescale’s MCUs Participate in EMC Standards committees

• Improve existing standards• Extend standards to Integrated Circuits

Communicate EMC basics and best practices


Specifications and Testing


IEC IC Conducted Transient Immunity EMC Measurement Methods

IEC 61000-4-4 Fast Transient Conducted Immunity

• True 61000-4-4 System Level Testing• FSL EFT• Langer EFT

IEC 61000-4-2 Powered ESD• Adapted to IC Level Tests

Powered ESDEFT, FSL Probe

EFT, Langer Probe

EFT, Mains Injection


Fast Transient Testing – IEC 61000-4-4 EFT

0

5

10

15

20

25

30

35

21 V

SS A

W60

21 V

SS

AC60

22 V

DD

AW

60

22 V

DD

AC

60

44 V

DD

AD A

W60

44 V

DD

AD

AC

60

45 V

SSAD

AW

60

45 V

SSA

D A

C60

54 V

REF

H A

W60

54 V

REF

H A

C60

55 V

REF

L A

W60

55 V

RE

FL A

C60

Pin Under Test

EFT

Gen

erat

or V

olta

ge (V

)

Result EResult DResult CResult BResult A


Electrical Fast Transient (EFT) Testing – IEC 61000-4-5 Surge Test

• Power System Switching transients (e.g. capacitor banks switching)• Load changes• Resonating circuits associated with switching devices such as thyristors• System Faults (e.g. shorts, arcing faults to ground)• Lightning strikes (direct, indirect or direct to earth)


Fast Transient Testing – IEC 61000-4-12 Ringwave

The ring wave is a typical oscillatory transient induced in low-voltagecables due to the switching of electrical networks and reactive loads, faults and insulation breakdown of power supply circuits or lightning.

Trise = 0.5uSOscillation Frequency = 100kHzGenerator Voltage to 4kV1-60 Transients / Minute


Other Conducted Susceptibility Test Methods

|

B

|w LB =

µo |4ΩR2 ∫

++++++++- - -- - -- - --

http://images.google.com/imgres?imgurl=http://chud.com/articles/content_images/111/oscilloscope-tektronix-2445B-7cs.jpg&imgrefurl=http://www.chud.com/articles/articles/13529/1/AWESOME-I-FUCKIN-BOUGHT-THAT/Page1.html&usg=__2weoYvz2n8ZLTiI7AsdMbmO6NRQ=&h=600&w=600&sz=92&hl=en&start=9&tbnid=Es63aavtFm0ZJM:&tbnh=135&tbnw=135&prev=/images?q=oscilloscope&gbv=2&hl=en


Langer Diagnostic Probe

Induced Voltage as Function of Area - Circular Loops

0

10

20

30

40

50

60

70

7.07

12.57

19.63

28.27

38.48

50.27

63.62

78.54

95.03

201.0

631

4.16

706.8

6

Test Loop Area (mm^2)

Indu

ced

Volta

ge 10% Output

30% Output

40% Output

50% Output

90% Output


Creative


Next Generation Fast Transient Test?


System Design and Best Practices


GOFSL



Theory

Electromagnetic theory is well understood The problem – not everyone understands it So … a quick review of Maxwell’s equations

wikipedia.org


Guidelines

Do not rely on design guidelines – Todd Hubing, Clemson UniversityUse common senseVisualize signal current pathsLocate antennas and crosstalk pathsBe aware of potential EMI sourcesAsk other engineers to review your designs


Hardware Techniques – Design Methodology

Goals• Attenuate transients to prevent performance

degradation or reliability issues• Maximize use of hardware techniques before using

software techniquesDesign for EMC should be considered from

the beginning of a projectDesign for EMC is a complex task

• Use a methodical strategy• Be prepared for many iterations• Employ experts if necessary

Design for EMC compliance• Do not limit design to maintain a cost target• The design can be cost-reduced later

Success requires attention to detail and close coordination with other disciplines

PCB Floorplan

PCB Power Distribution

PCB Decoupling & Filtering

Input Filtering & Protection

Iteration Complete

MCU Oscillator

Iteration Start

System Power & Signal Entry

System Connectors & Cable Routing

System & PCBPower Supply


Hardware Techniques – Design Methodology

Tools for application transient immunity• Block transient currents

The goal – limit transient currentsSeries impedancePhysical isolation

• Shunt transient currentsThe goal – limit transient voltages.Parallel conductancePhysical shielding

• Make IC insensitive to transientsThe goal – minimize voltage differences between any pins of the IC and the reference (typically VSS) during and shortly after a transient eventIdeally keep Δ(VDD-VSS) and Δ(VI/O-VSS) less than 8V. Using external Zener or TVS clamp may help. Keep Δ|VSS-VSSA| less than 0.3V

ResistorsInductorsFerritesCM chokes

CapacitorsVaristorsZener DiodesTVS Devices


Hardware Techniques – System Design

Power Entry Filtering• First opportunity to eliminate conducted

transients• Unfiltered power

Allows unimpeded access to the systemRequires complex solutions for PCB and cables

• Power entry filtering at point of entry Reduces complexity of system designPCB design and layout are less criticalCable routing is less criticalImproves radiated and conducted emissions performance

PCB1

PCB2

Conducted

Radiated

PCB1

PCB2

ConductedFilter

No Filter – Conducted immunity signal propagates to PCB1 and radiates to couple to PCB2 and interior cables.

Filtered – Conducted immunity signal suppressed. Clean power supplied to PCB1 and no internal radiation.


Hardware Techniques – PCB DesignPCB Power Distribution

• The basis for effective EMC design• Layout guidance

Ground (reference)– Prioritize ground routes over all other routes– Do not use wire jumpers and minimize layer transitions.– Where layer transitions occur, use multiple vias– Use planes (or wide traces)– Minimize impedance between VSS pin and clock source, decoupling, bypassing

and filtering components. Use a plane where possible.Power

– Route parallel to ground on same or adjacent layers– Use wide traces (or planes)

Data– Lowest priority for routing– Use wire jumpers and vias for connectivity

• Decouple regulated and filtered power routed off the PCB (to sensors, displays, etc.)


Hardware Techniques – PCB Design

Bypassing: • Definition - The reduction of HF current flow in a high impedance path by shunting

that path with a bypass component, typically a capacitor

• PurposePrevents unwanted communications between different components (or different power domains) that share the same power rail. This effect is called common-impedance coupling.Provides a local source of charge to limit voltage variations on the power and ground railsImproves noise margins and stability

• CriteriaThe capacitance must be sufficient to provide the needed transient current to the load (See AN2764 for needed calculations)The impedance between the bypass and the load must be very lowThe loop area of the layout must be as small as possibleCaps need to be located close to micro to be effective

0.1uF

VDD

VSS

MCU



Bypassing• Visual aid – make sure bypass capacitor is in-line with power supply lines

The supply lines will pass by the cap before entering the MCUWith the cap close to the MCU, the loop formed by the MCU and cap is minimizedSmall loops pick up (and generate) less noise

VDD

VSS

MCU0.1uF

MinimalLoop

Bypass capacitor is between supply and load – effective HF shunt

Good

VDD

VSS

MCU0.1uF

VDD

VSS

MCU0.1uF

Bypass capacitor is after load – MCU is HF shunt

IneffectiveA X Y



Decoupling• Definition – The isolation of two circuits on a common power supply to prevent

the transmission of noise between the two circuits using a combination of blocks, and optionally shunts, typically in the form of a low pass filter

• PurposePrevents unwanted communications between different components (or different power domains) that share the same power rail. This effect is called common-impedance coupling.Provides increased isolation over bypassingImproves noise margins and stability

• CriteriaAn n-element filter where at least one element is a blocking deviceThe insertion loss of the filter meets the requirement for isolation



Decoupling• Implementation

Place the decoupling circuit at the entry point of the power domain to be filteredDecoupling is not always used

– Decoupling is typically used as a last resort if bypassing fails to give the wanted power-supply isolation.

There is always some decoupling built into any circuit– Conductors act as decoupling inductors. Although short trace lengths are

desirable, the power lead being long can sometimes help improve decoupling.

• Examples:

VSS

VDD

UnfilteredDC Input

VSS_ISO

VDD_ISO

FilteredDC Output

VSS

VDD

VSS

VDD_ISO7805

Generic decoupling filter Voltage regulator

Note: Bulk cap needed on each side of decoupling element



Inputs • See recommendations in AN2764• Place filter cap as close to MCU as possible, referenced to a solid MCU

ground.

High Speed/Programming Pins – 10k pull up if suspected noise on this line, no caps

MCU

VDD

VSS

Input

100nF

1kΩ

MCU

VDD

VSS

RESET/IRQ

100nF

10kΩ



Floor Plan Example

• Identify element function and power domain• Group PCB elements by power domain• Decouple and bypass power domains• Filter inputs and outputs

Analog

MCUEMIFilter

Out

puts

PowerSupply

Sensors

Out

puts

Rel

ay

Rel

ay

Rel

ay

Inpu

ts

Inpu

ts



Route Ground and Power first• Power connections

Analog

MCU

EMIFilter

Outputs

PowerSupply BP

Inpu

ts

Sensors Inpu

ts

Digital DC Power Domain

AC Power Domain

Analog DC Power Domain

DF

DF

LPF

BPBP

OutputsLPF

Inputs

Rel

ay

Rel

ay

Rel

ay

DF: Decoupling filter [Typically L = 100uH-100mH, C = 1uF-100uF]BP: Bypass capacitor [Typically 0.1uF connected between power/ground pins]LPF: Low-pass filter [Typically R = 1kΩ, C = 100nF (10nF for fast signals)]



Then route I/O• I/O connections

Analog

MCU

EMIFilter

Outputs

PowerSupply BP

Inpu

ts

Sensors Inpu

ts

Digital DC Power Domain

AC Power Domain

Analog DC Power Domain

DF

DF

LPF

BPBP

OutputsLPF

Inputs

Rel

ay

Rel

ay

Rel

ay

DF: Decoupling filter [Typically L = 100uH-100mH, C = 1uF-100uF]BP: Bypass capacitor [Typically 0.1uF connected between power/ground pins]LPF: Low-pass filter [Typically R = 1kΩ, C = 100nF (10nF for fast signals)]



Floor Plan Example

Power supply and EMI filter

Analoginputs

MCU and Digital I/O

Relays

Filter components close to MCU

Isolation – series impedance



Clock Source Advantages Disadvantages

Ceramic Resonator Lower cost Sensitive to EMI, humidity and vibration. Drive circuit matching.

Crystal Low cost Sensitive to EMI, humidity and vibration. Drive circuit matching.

Crystal Oscillator ModuleInsensitive to EMI and humidity. No additional components or matching issues.

High cost. High power consumption. Large size. Sensitive to vibration.

RC Oscillator Lowest costSensitive to EMI, humidity and vibration. Poor temperature and supply voltage rejection. Poor freq control and accuracy.

Silicon Oscillator (INTERNAL OSCILLATOR)

Insensitive to EMI, humidity and vibration. Fast startup. Small size. No additional components or matching issues.

Temperature sensitivity generally worse than crystal and ceramic resonator. Some have high power consumption.

OscillatorEMC characteristics of clock sources



Oscillator• Configuration

Use higher frequency signal source (4MHz v. 32kHz crystal) for immunityUse high-gain oscillator option for immunityUse low power oscillator option for emissionsUse internal oscillator, if possible

• LayoutHighest layout priority after power distribution system and MCU decouplingImplementation must be controlled to prevent susceptibility

– Group components tightly– Locate next to oscillator pins– Use short traces– Surround with guard trace– Isolate from other I/O

Do not route functional currents using oscillator reference GND



Oscillator Example 1 from AN2764

VREFHVREFL

C2

Crystal

R0

R2

C1 R1

C1

R0

C5

C6

C7

R2C8

C3

C4

VDDOSC1OSC2VSS

IRQ

RESET

VSSA

VDD

A

XFC

Power

Ground

Ground trace

Power trace

Sensitive input trace

GPIO trace

Wire jumper

Thru-hole via

Wide power and ground tracesParallel power and ground traces

Bypass caps C2 and C3 in-line with power feed – makes loop area small

Note: C4 bypass is not in-line.In this case it provides a charge reservoir for the VREF supply.

Layer transition provides decoupling for analog supplies

No planes or signals under crystal network


Ground Planes

Find the Ground Plane


GND

VCC

Ineffective MCU VDD/VSS bypass Supply

Loop CurrentBypass Loop CurrentVSS-VDD Loop

Typical Example Power Routing

•Large planar loop•Impedance issues with: - Layer transitions - Changing line widths- Single vias


Better Power Routing

•Parallel routes•Fewer layer transitions•Could use more vias


Software Techniques

Overview• The structure and functionality of microcontroller software can have a

profound impact of transient immunity performance• Failure modes:

False Signal Detection – The MCU detects a change in an input signal that was induced by a transient or other noise. The MCU then operates on or responds to the signal as if it were real.Code Runaway – The MCU software execution flow is disrupted. The MCU begins to execute code out of sequence or from incorrect areas of memory.

• The impact on software is managed through defensive software design.• Software does not eliminate the transient or noise. It can only attempt

to control the MCU response to the transient or noise.• Long-term issues due to exposure to transients remain.


Defensive Software Contents

Digital Input PinsInterrupt PinsUnused PinsCritical I/O RegistersCPU Register TestsProgram FlowToken PassingFrequency of Interrupts (too few/too many)Code Runaway – WatchdogsCPU Clock Watchdog Reset Timeout TestCRC check on Flash IntegrityUnused Program Memory locationsRAM TestingUnused Interrupt Vectors


Digital Input PinsIn the majority of all MCUs, the digital input pins are accessed generally by a parallel read by the CPU via it’s data bus. This access is normally captured on the edge of the CPU system clock. Thus if a spurious glitch occurs at exactly the time of reading the actual digital port pin, then a false state can occur. To overcome this spurious error condition, the user can deploy a polling technique where the digital input pin is read several times within a short time period and the dominant average value is taken as the true level.In the majority of cases the CPU/System clock will work at a significantly higher frequency than the expected external input signals. If this is not the case and the external input signal can change multiple states within a CPU clock period, then hardware latching or sample and hold circuits would be required to ensure a state condition is not missed out.

Read_portA_bit0 ()Char True_read =0;for (char count = 6; count!=0 ; count--)

unfiltered_read = portaIf (unfiltered_read&&0x01) true_read++; /* mask off all bits except bit 0

;If (true_read > 2) return (1) ;

Else return(0);

Port x1

CPU Read

CPU Read

System clock

1 1 1Result (no polling)

1 0 1Result (polling)

! " !

! ! !

Polling


Interrupt PinsIn many MCUs, external pins have interrupt capability and in most cases will interrupt the CPU on a specific rising or falling edge. To avoid a spurious noise glitch being seen as a rogue interrupt, users should always read the input signal pin to confirm that the input signal has maintained it’s assertive state.

• For example, if the PA0 pin interrupts the CPU on a negative edge, the ISR first instruction should read the PA0 pin – and if clear, then execute the interrupts subroutine. If set, then take this as a rogue interrupt.

• Note: In most cases the ISR will take several CPU clocks cycles after the input event has occurred providing a delay. Depending on the environment and the system design, software delays also can be implemented to act a sort of de-bounce circuit.

For pins that have no read access, deploying a redundant digital input pin can provide this read after event mechanism.

Port x1

CPU access

System clock

ISRLower priority code(lpc) lpc lpc

Interrupt latency

Verify readIdentifies bogus interruptBack to main program

Verify pin state

In some cases the interrupt function may provide the option of edge and level sensitive. In most cases the hardware will still react to a rogue edge as the edge and level sensitivefeature really provides an additional interrupt if the input pin is held asserted after the ISR has completed.


Unused PinsIn some cases not all the input or I/O pins will be used in the MCU end application. Unused Input Only pins need to be tied to either VDD or VSS. A floating high impedance input pin will oscillate and provide an easier coupling path into the MCU circuits for noise. And additionally, they will consumer more current. (If MCU in Stop mode is consuming more current than expected max, this indicates a floating input pin or pins.)Unused I/O pins should be made outputs and drive a logic state out. Software can regularly update the Data and DDR to ensure the pin remains an output.Users of MCUs should also consider the package they are using of the particular MCU as multiple packages are often served with the same silicon die. And on smaller pinout versions, some input/output pins are not bonded out. Thus, the user must force these unused input/output pads to output a static level.For non-bonded input pins, the MCU manufacturer should deploy a pull-up or pull-down device to ensure these are not left floating. This might be programmable via a special control register.

Input only – Pull up or pull downNot used (NC) – Output lowNot bonded – Output low

PA7

PA6

NC


Critical I/O RegistersCritical I/O Registers such as

• Input/Output Data Ports• Data Direction registers• Clock/PLL Set-up registers• Peripheral Set-up registers• User defined RAM locations – key parameters

of the application codeAll registers–when you dig deep enough into the design–are basically flip flop latches that may be flipped by a spurious noise passing through the circuit.User software should regularly refresh the above critical registers within the main loop of the software to correct a possible flip of bit.For RAM locations where the variables are dynamic, then utilizing a CRC signature of the array of these locations can be saved and regularly checked and verified. MCUs with hardware CRC engines help provide a workable solutions. For MCUs with no hardware CRC engine, executing CRC in software likely will cost too much in execution time.Avoid updating registers on peripherals that are in mid operation (e.g. a transmitting SCI) or corruption/loss of data will occur.

Re-write – Safely


CPU Register Tests

In IEC 60730 it is recommended that the user software confirms that the CPU registers are working correctly. For stuck at faults then each of the CPU registers are written with 0x55 and 0xAA to verify there is no crosstalk between bits.A more stringent test on the register but slightly more time consuming is a walking of 1s through the register when cleared followed by walking 0s through all registers at 0xFF.

Stuck at CPU Register CheckWrite 0xAA, Read 0xAAWrite 0x55, Read 0x55

S12X CPU Registers

Write Complementary Data


Program Flow

Program flow of the various software functions is a key requirement to ensure System Integrity. Watchdog circuits provide hardware protection if program flow does not follow as expected. Generally, they should be deployed as the last-chance mechanism.A key measure to ensure correct Program flow is known as time-slot monitoring – the method of periodically checking the current status of where the program counter is and is it performing as expected.For example: Using a simple timer overflow interrupt set at ~100mS will interrupt the CPU and the TOF ISR will be executed. Within this ISR the user can use a form of Token passing to 1) check program flow and 2) check other interrupt usage.

Appl code Appl code Appl code Appl code Appl code

Time-slot monitoring – a periodic check on program code flow

CPU Access

Periodic interrupt

Program flow check Program flow check

Periodic Status Checks


Token PassingA simple form of token passing is to deploy a variable in RAM called COUNTBYTE and for each significant function, increment this COUNTBYTE by 1.With the knowledge of how long the program takes to execute these various functions, the COUNTBYTE can be read within the ISR and compared to previous captured value. If within certain range, it deems the program flow to run as expected. If outwith this range, the program is performing not as expected and mechanisms to reset or place the MCU in a safe mode can be made.Caution: Within each software function, it is not recommended to increment the COUNTBYTE by a certain value but actually set the COUNTBYTE to a fixed value. On real time embedded systems interrupts can occur at any random time and therefore are more difficult to monitor along with the program flow as described above. Thus, only the frequency of interrupts can be monitored then checked within the same periodic ISR routine.

F11 F12 F13 Checkflow

….If (COUNTBYTE < (previousCOUNTBYTE+2)) Error;If (COUNTBYTE > (previousCOUNTBYTE+6)) Error;/* prrogram flow OK */previousCOUNTBYTE = COUNTBYTE;…..

CO

UN

TBYTE=0x11;

CO

UN

TBYTE=0x12;

CO

UN

TBYTE=0x13;

Proceed only if conditions are as Expected


Code Runaway – Watchdogs

The above two examples describe methods to identify early warnings that the application is not performing as expected. In some cases interrupts could be masked and the program counter is corrupted which catches in a small, tight loop that does not allow the unmasking of the interrupts. At this point, the use of a watchdog is required to protect against this scenario. The majority of MCUs have on-board watchdogs that can be enabled to protect against this scenario. Additionally the user should test that the watchdog circuit times-out correctly and performs a reset before executing the code

Counter

Refreshmechanism

Clock Reset on overflow

CPU Access

basic watchdog

If CPU does not execute theunique refresh mechanism beforecounter times out then a reset tothe CPU and all peripherals occurs.


Watchdog Reset Timeout Test

Before executing any application code, the watchdog should be tested that it is functioning correctly.

Some MCUs have a System Reset Status Register that allows the user to determine the cause of the reset. On recognizing a Power on reset, the user can write a specific word (16- or 32-bits) to RAM location (wdog_test_flag). After this the watchdog is enabled (if not already) another timer is enabled, and then the software sits in a small loop which reads the other timer’s count value and stores it to another RAM location. Eventually the watchdog will time out and reset. The user code sees that the reset occurred due to a WDOG timeout (from the System Reset Status Register) so confirms if this is a test of the WDOG or a genuine WDOG reset by reading wdog_test_flag. If it is a WDOG test, it is certain that the WDOG has timed out and reset the MCU as expected, but comparison with the captured other timer count value must be ascertained if the time-out period is within the expected range. If this compares ok, then the wdoghas been tested and application code now can be executed.

Read other timer value Application code

Read Timer Counter value

Store in RAM

Detect POR (System Reset Reg.)Enable WDOG

Write to wdog_tst_flag in RAM

Detect WDOG reset (System Reset Reg)Quantify if WDOG test

Compare WDOG timeout with expected Timer Counter value in RAM

reset

CPU access

Test the Watchdog


CPU Clock

The CPU clock is generally sourced from:• Internal RC oscillator then multiplied (PLL/FLL) to higher frequency• External Crystal/Ceramic Resonator then PLL/FLL to higher frequency

Most peripherals are clocked by the same source as CPU Thus if CPU clock stops for a particular reason:

• No interrupts will be requested• No peripherals will be clocked• No software will be executing

If no CPU clock occurs in real time application then software cannot overcome this issue

Thus a watchdog circuit using an alternative clock source still will timeout and reset the key peripherals without CPU clock.

User watchdogs with independent clock source from CPU clock.

Clock Monitor Watchdog with Separate Clock


CRC Check on Flash Integrity

Verifying the memory is functioning correctly prior to executing application code is recommended. For non-volatile memory such as Flash or EEPROM, a CRC signature is a good approach in providing a high-diagnostic coverage.There are various different CRC signatures – a common one is CCITT-CRC16. This well understood polynomial equation is easily executed in both hardware and software. A software CRC engine will take around 700-1000 CPU cycles to calculate a modified CRC on the addition of 1 byte of data. A h/w CRC engine will take 1 CPU cycle.The approach: Once the application code is completed and working reliably with no changes anticipated, then a CRC signature is made of the total used memory array.Once this signature is completed, it is stored in another unused nvm space and referred to as the golden_signature.After reset the user code will execute a new CRC calculation on the total used memory array then compare the new calculated signature with the golden_signature. If it compares ok, the memory and arguably the addressing mechanism are working correctly.

CRC engine complying toCRC16-CCITT specification(x16 + x12 + x5 + 1 polynomial)

golden_signature

Better than Checksum

Note: In IEC 61508 CRC signature of NVM, memory is taken to be a more stringent measure than Error Code Correction (parity checking) in hardware. This is because the CRC signature is generally carried prior to executing application code, thus identifying a fault before running with wrong code/data.


Unused Program MemoryIf there are unused memory locations in the NVM arrays, fill these locations with instructions such as SWI (software interrupt). On a runaway condition when the program counter points to unused location, it will force an interrupt which can then put the MCU and the application into a safe state.If there is no Software Interrupt then by examining the assembly code for JUMP(extended address), instruction and the NOP instruction should be examined. With careful consideration fill the unused array with jump to a safe_location.

• For example: On the S08 CPU the JMP instruction is 0xCC, NOP is 0x9D. So if at address $9D9D, we place code that places the MCU in a safe condition –then fill the array with

• CC,9D,9D,CC,9D,9D, CC,9D,9D, CC,9D,9D, CC,9D,9D, CC,9D,9D, etc.

• Thus if the Program Counter fails in any location, it will either execute a JMP instruction to $9D9D or a NOP, followed by JMP $9D9D or NOP, NOP, JMP $9D9D.

In most CPUs there are instruction op-codes that will do minimal effect and allow the runaway program counter to go to a known safe place.Note: Avoid filling the arrays with NOPs as this will provide further randomness to how the MCU will perform (unless the top of the unused array falls into a usable array). If the program counter jumps to somewhere in the unused array it will execute all the NOP instructions to the top then execute possibly what is in the next address location (could be I/O register or an interrupt vector contents).

$9D9D JMP Safe_start

Unused Program SpaceAddr Code Instruction$E000 0x9D NOP$E001 0x9D NOP$E002 0xCC JMP$E003 0x9D$E004 0x9D$E005 0xCC…….

If PC jumps into anywhere in unused program space, it will execute a few NOP instructions then jump to a safe_start function.

• Block fill w/SWI• SWI ISR – force reset

• Jump to Safe_start• Block fill w/illegal opcode

• forces reset


Void interrupt ISR_spare()/* called from unused vector */Safe_mode();

Unused Interrupt Vectors

Unused interrupt vectors should be programmed to point to an individual ISR that will ensure the MCU is placed into a safe known state as most interrupts will require a clearing mechanism. No interrupt vector location should be left blank.

Void interrupt ISR_spare()/* called from unused vector */Safe_mode();

Void interrupt ISR_spare()/* called from unused vector */Safe_mode(); Each ISR Clears Respective Flag


Software Techniques

Digital or Analog Inputs• Boundary checking

Using the input capture function of a Timer module to measure the time duration of the signalThe captured value can be compared to the expected valueThe software can then react appropriatelyExample:

– Input signal specification requires a pulse width of 1ms to 10ms– Input capture measures an input pulse width of 50ns such as from an ESD

event. Input pulse is bad data.– Input capture measures an input pulse width of 5ms. Input pulse is good data.

Analog Inputs• For ADC inputs, actively monitor converted values or apply averaging.

For other inputs, options vary by module functionality.


Software Techniques

Integrated Protection Features• Enable all available built-in protection features• Initialization

Enable hardware protection during software initialization– Typically done by writing a configuration register– These configuration bits are often write once

Note: Write these bits even if the default states are not changed. This prevents accidentally disabling protection due to code runaway.Disable hardware functions that are not used

• Low Voltage Detect (LVD) circuitsResets the MCU in the event of sudden power lossCan be used to prevent code runawayMay not detect very fast transients due to slow response timeOperate at lower voltages than external voltage supervisor chips


Conclusions

Achieving transient immunity in low-cost applications can be difficult and time-consuming, particularly if not addressed early and often.

Employ a rigorous EMC design methodology. Obtain the needed EMC expertise. Leverage information from suppliers. Understand the limits of low cost. Save cost reduction for after EMC compliance is achieved.


References

Ronald B. Standler, Protection of Electronic Circuits from Overvoltages, John Wiley & Sons, 1989

Ken Kundert, “Power Supply Noise Reduction”, The Designer’s Guide (www.designers-guide.com), 2004

Larry D. Smith, “Decoupling Capacitor Calculations for CMOS Circuits”, Electrical Performance of Electrical Packages Conference, Monterey CA, November 1994

Clayton Paul, Introduction to Electromagnetic Compatibility, Wiley & Sons, 1992

Bernard Keiser, Principles of Electromagnetic Compatibility, Artech House, 1987

Howard Johnson, Martin Graham, High-Speed Digital Design, Prentice Hall, 1993

Ralph Morrison, Grounding and Shielding, John Wiley & Sons, 2007Freescale Semiconductor application note AN2764, “Improving the

Transient Immunity Performance of Microcontroller-Based Applications”, www.freescale.com, 2005

http://www.freescale.com/


High Speed Design Reading List

Right the First Time – A Practical Handbook on High Speed PCB and System Design – Volumes I & II – Lee W. Ritchey (Speeding Edge) –ISBN 0-9741936-0-7

High Speed Digital System Design – A handbook of Interconnect Theory and Practice – Hall, Hall and McCall (Wiley Interscience 2000) – ISBN 0-36090-2

High Speed Digital Design – A Handbook of Black Magic – Howard W. Johnson & Martin Graham (Prentice Hall) – ISBN 0-13-395724-1

High Speed Signal Propagation – Advanced Black Magic – Howard W. Johnson & Martin Graham – (Prentice Hall) – ISBN 0-13-084408-X

Signal Integrity Simplified – Eric Bogatin (Prentice Hall) – ISBN 0-13-066946-6

Signal Integrity Issues and Printed Circuit Design – Doug Brooks (Prentice Hall) – ISBN 0-13-141884-X


EMI Reading List

PCB Design for Real-World EMI Control – Bruce R. Archambeault (Kluwer Academic Publishers Group) – ISBN 1-4020-7130-2

Digital Design for Interference Specifications – A Practical Handbook for EMI Suppression – David L. Terrell & R. Kenneth Keenan (Newnes Publishing) – ISBN 0-7506-7282-X

Noise Reduction Techniques in Electronic Systems – Henry Ott (2nd Edition – John Wiley and Sons) – ISBN 0-471-85068-3

Electromagnetic Compatibility Engineering – Henry Ott (John Wiley and Sons) – ISBN 0-470-18930-6

Introduction to Electromagnetic Compatibility – Clayton R. Paul (John Wiley and Sons) – ISBN 0-471-54927-4

EMC for Product Engineers – Tim Williams (Newnes Publishing) –ISBN 0-7506-2466-3

Grounding & Shielding Techniques – Ralph Morrison (5th Edition -John Wiley & Sons) – ISBN 0-471-24518-6


GOFSL



Basic EMC/EFT Design Checklist – One PagerHardware and Layout Power and Ground Routing done first MCU VSS should be on ONE layer, no vias if possible, multiple vias if layer transitions Connect VSS, VSSAD, VREFL pins together Good Osc layout, Filter GND from VSS Bypass caps for supply right at MCU pins, make bigger if possible. (0.1uF to 1uF if possible) Reset and IRQ filtered with 0.1uF cap, 10k pull up at micro BDM line needs a 10k pull up and some series resistance if brought out to a connector Prevent over voltages on VDD (>8V) at micro; use a TVS or Zener at VDD, VSS of micro Prevent VSS differential (>0.3V) by connecting VSS pins together, good routing, limit vias, use continuous trace

(See first three bullets) Decoupling on board edge if PS is off board for temp sensor, motor, etc. Keep VDD and VSS at micro as parallel as possible for mutual inductance Input filter caps located close to micro and tied back to micro’s VSS and VDD rails Interlace DC signals with fast switching signals (clocks, door lock, charge pumps, A2D, EEPROM) Include BDM connections for possible diagnostics during noise testing i.e., Hotsync and Programming

Software Unused I/O – Configure as outputs driving low Unbonded I/O ports – Configure as outputs driving low Unused modules – Write control registers to turn off

Clocks, Order of Operation Set up system registers first: SOPT, SPMSC1, SPMSC2, SOPT2 registers (LVD, COP, low power) Set up the oscillator: 1) read and write trim value, 2) write ICGC2 register first (multiplier, divider, LOx reset),

3) write ICGC1 (clock and mode) and 4) wait for lock• Enable loss of clock reset (LOCRE=1)• Enable loss of lock interrupt (LOLRE=0); ICG interrupt should make sure it’s locked before returning

Set up I/O


Freescale Product Longevity Program

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Freescale has a longstanding track record of providing long-term production support for our products

Freescale offers a formal product longevity program for the market segments we serve

• For the automotive and medical segments, Freescale will make a broad range of program devices available for a minimum of 15 years

• For all other market segments in which Freescale participates, Freescale will make a broad range of devices available for a minimum of 10 years

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