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Robert L. Rhoades, Ph.D.CAMP Conference (Lake Placid, NY)August 10-12, 2009

Balancing Technical and Business Challenges in CMP R&D

Our Expertise, Our Services,Your Success

2

Outline

• Background and Business Climate for CMP

• STORM Development

• CMP Applications and Examples

• Conclusions


3

Balancing Act

COST Technology


4

Interconnects at Intel

Interconnect Technology

500 nmILD planarization, W plugs w etch back

130 nm3‐6 Cu Layers, PMD, W, STI

350 nmFour Al metal layers, W polish, PSG

180 nm STI, 6 Al Metal layers

250 nmSTI, Five Al metal layers, SiOF

65 nm4‐11 Cu LayersPMD, W, STI, OSG

90 nm3‐9 Cu Layers, PMD, W, STIOrganoSilicate Glass (OSG)

1000 nmTwo Al Metal layers, BPSG

CMP Evolution

Oxide PolishPre-Metal DielectricInterlevel Dielectric

STI PolishPoly PolishTungsten PolishCopper PolishBarrier PolishHigh k Gate

CMP Applications

Process, Applicatio

n, Equipment, &

Slurry Evolve, but n

ot as much on Pads

Source: Courtesy of Ken CadienFormer Intel fellow


5

Driving Forces Today

• Since 2005, consumer products have become primary industry driver.

• Short product life cycles.

• Consumers demand More for Less.

• Consumers demand More in Less Space.

• Contributing factors for Moore’s Law – device shrinks, multi-level stacks & larger wafers.

• Result = Fierce Competition

+ Control Unit Costs+ Develop Technology Fast+ Ramp Volume Quickly

Source: 2007 Industry Strategy Symposium – Hans Stork, CTO, Texas Instruments

Source: 2007 Industry Strategy Symposium – Steve Newberry, CEO, Lam Research Corporation


6

Competitive Advantage

Revenue Loss from Being Late to Market

Strategic Factors in the IC Industry, FSA Forum, June 05Dr. Handel Jones, Chairman & CEO – IBS, Inc.

Acceleration with CMP Outsourcing:Scenario 1: First time CMP implementation

Customer Internal Technology Integration Project:Ramp

CMP Implementation with Entrepix:Ramp

Scenario 2: CMP capacity expansionCustomer Internal Capacity Expansion Project:

Qualify Ramp

CMP Capacity Expansion with Entrepix:Qualify Ramp

Scenario 3: CMP burst or flex capacity absorptionCustomer Internal Capacity Expansion Project:

Qualify Ramp

CMP Capacity Expansion by IDM already qualified at Entrepix:Ramp

Scenario 4: CMP technology improvement or cost reductionCustomer Internal Capacity Expansion Project:

Ramp

CMP Capacity Expansion with Entrepix:Qualify Ramp

Proj

ect P

hase

s Customer Generating Revenue

TIME

Develop, Optimize & Qualify

Customer Generating Revenue


Equipment Purchase & Delivery Customer Gen. Rev.


Equipment Purchase & Delivery Design, Integrate, Optimize & Quality

Customer Gen. Rev.


Equipment Purchase & Delivery

Optimize & Qualify


7

Business Realities

• Time IS Money– Labor cost + cycles of learning + opportunity cost

• Competition in most markets is fierce

• Quality & reliability can not be compromised

• Each process module must be efficient


8

Business Response

Extend Equipment LifeKeep Depreciated FabsR&D ConsortiaInstall Less OvercapacityDelay Capital Expenditures

Preserve CapitalMinimizeManufacturing Costs

Accelerate DevelopmentWhile Reducing Costs

BenchmarkingYield EnhancementOptimize Unit ProcessesFocus on Efficiencies

Reduce Cycles of LearningExtend Proven TechnologiesLower % of Engineering Wafer StartsLeverage Outside Expertise


9

Numerous complex puzzles

Applications for CMP Continue to Expand

1995 - Qty ≤ 2CMOS

Glass (oxide)Tungsten

2001 - Qty ≤ 5CMOS

Glass (oxide)TungstenCopper

Shallow TrenchPolysilicon

CMOS New Apps Substrate/EpiGlass (oxide) Doped Oxides GaAs

Tungsten Nitrides GaNCopper NiFe & NiFeCo InP

Shallow Trench Noble Metals CdTe & HgCdTePolysilicon Al & Stainless Ge and SiGe

Low k Polymers SiCCap Ultra Low k Ultra Thin Wafers Diamond & DLC

Metal Gates Direct Wafer Bond Si & ReclaimGate Insulators Through Si Vias SOI

High k Dielectrics 3-D Packaging QuartzIr & Pt Electrodes MEMS Titanium

Magnetics NanodevicesIntegrated Optics

2009 - Qty ≥ 36

Each application of CMP requires an optimized process that meets

both performance and cost targets


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#1 Accelerate Time to Revenue#2 Reduce Cost and Risk

Comprehensive CMP Solution


11

CMP Metrics

Five key metrics for a CMP process

Removal Rate and Uniformity

Defectivity

Planarization(step height, dishing/erosion, surface roughness, etc.)

Process Stability(consistent performance from wafer-to-wafer)

Cost per Wafer


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CMP Development

• Zoom in on CMP process development

• Assumes fundamentals of pad/slurry research are already done by suppliers

• Test wafer availability and quality often impact timeline, validity of results, etc.

• Initial process DOE’s generally focus on removal rate and gross surface quality

• Optimization stages can be interchanged or executed in parallel

• Planarity can mean step height, dishing, erosion, roughness, etc. depending on the material and intended application

• Failure at any stage usually means backing up at least one stage to try again

Consumables Screening

Process DOE's

Optimize Uniformity

Optimize Planarity

Optimize Defectivity

Stability (marathon)

Release for Device Qualification

CMP Development Sequence

Generate Test Wafers

Repeatability (multiple runs)

Screening Tests

Optimization

Repeatability

Marathon


13

STORM

• Screening Tests

• Optimization

• Repeatability

• Marathon

STORMSTORM

A proven approachto successfullydeveloping newCMP processes


14

Intro to CMOS Example

• Project launched to develop a planarized integration for an existing facility running mostly 0.5um and larger devices which did not require CMP.

• Integration included 2 levels of oxide CMP (PMD and ILD) and 2 levels of tungsten CMP (contact and via1).

• Initial estimate was roughly 24 months to purchase, install, and qualify CMP equipment plus develop the integration and be ready for production ramp.

• By leveraging an outsource CMP provider, integration work was started almost immediately and executed in parallel with the equipment lead time.


15

Timeline Comparison

• Key aspects of predicted time savings:– Development could begin as soon as test wafers were ready.– Equipment purchase, lead time, and installation in parallel.– Faster cycles of learning, fewer wafers, lower cost compared to internal.

Initial Project Timeline for Tool Purchase and Internal Development

Install

Adjusted Project Timeline with CMP Outsource through Entrepix:

Install

3 mos 6 mos 9 mos 12 mos 15 mos 18 mos 21 mos 24 mos 27 mos 30 mos

Production Ramp

Development

Production RampQualification

Time

Proj

ect P

hase

s Equip. Purchase

Equip. Purchase

Timeframe Acceleration = 12+ months

Development

Volume Production Revenue Enabled

Qualification


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Timeline Detail

Polish processes developed: 4 (PMD, W Contact, ILD, W Via1)Total patterned wafers: < 125Total blanket test wafers: < 200Total CMP lab shifts: < 12

Detailed Timeline for CMP Process Module Development

Patt.

Waf

ers

Blan

ket W

frs

CM

P L

ab D

ays

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Task or Milestone DetailsPhase 1: PMD Planarization Duration ~6-8 wks X

Generate test wafers BPSG XCMP process - Initial characterization 12 25 2 XPolar evaluation of results XPMD 2nd round optimization 13 25 1 X

Phase 2: Tungsten Contacts Duration ~8 wks XMask layout and photo optimization XGenerate test wafers 3rd party tungsten CVD XCMP process - Initial characterization Incl. SEM X-sections 12 25 3 XPolar evaluation of results XContact 2nd round optimization 13 25 2 X

Phase 3: ILD1 Planarization Duration ~6 wks XGenerate test wafers XCMP process - Initial characterization 12 15 2 XPolar evaluation of results XILD 2nd round optimization 13 10 1 X

Phase 4: Tungsten Vias Duration ~6 wks XMask layout and photo optimization XGenerate test wafers 3rd party tungsten CVD XCMP process - Initial characterization 12 25 2 XPolar evaluation of results XVia 2nd round optimization 13 25 1 X

Prototype Run (Begin Qual Lots) Duration 4-6 wks XMask layout and photo optimization XVerification of entire process flow 25 25 4 XEvaluation of prototype devices In-line and EOL (ongoing)


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Issues Resolved

As might be expected, a few issues were encountered during the project. Examples are given below and further detail is provided in a few cases.

Technical dialogue between Entrepix and customer engineering team

Alignment marks (inconsistent contrast on wafers with CMP)

Changed PMD dielectric composition from TEOS to PSG or BPSG

High NMOS leakage and poor p-field inversion

Suggestions from Entrepix and Novellus helped solve issue in one cycle of learning (Traced to insufficient strip after contact etch)

Poor contact fill (seen on first contact lot)

Starting point suggestions followed by optimization on 1st and 2nd engineering lots

Ti/TiN liner and CVD W deposition thicknesses

Verbal description of effects confirmed with data from test structures – adjustments made in design rules

Pattern density effects

Technical inputs from Entrepix with confirmation on 1st engineering lot

Composition and thickness of ILD dielectric layer

How ResolvedIssue


18

Issue #1 – High Rc

Resolution involved optimizing post etch strip and was confirmed

on next product lot.

4485A001 80 W-PLUG 3.JPG

4485A001-09 NOTCH A1.JPG

Hollow contacts with high resistance on first lot.

Initial brainstorming between customer and outsource provider led to short list of likely causes.

Resolved with one round of optimization.

Hollow contact Improved contact


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Issue #2 - Leakage

0.01

0.10.03

10.3

103

10030

1000300

100003000

Res

ult

BPSG PSG TEOS

PMD glass composition

BPSGPSG

TEOS.01 .05.10 .25 .50 .75 .90.95 .99

-3 -2 -1 0 1 2 3

Normal Quantile

0

10

20

30

40

50

60

Res

ult

BPSG PSG TEOS

PMD glass composition

BPSGPSG

TEOS

.01 .05.10 .25 .50 .75 .90.95 .99

-3 -2 -1 0 1 2 3

Normal Quantile

The first integration lot showed unexpectedly high NMOS leakage and p-field inversion issues.

Technical brainstorming identified trapped charge in TEOS layer as a possible cause of the observed issue.

Split lot data confirms that changing to either BPSG or PSG for pre-metal dielectric resolves both issues.

NMOS leakage by PMD oxide

P-field inversion by PMD oxide


20

CMOS Summary

• By leveraging the capabilities of an outsource CMP provider, the project timeline for developing a 0.35 um integration in a fab was accelerated by roughly one year.

• Acceleration was driven by two primary factors.

– First, the team did not have to wait on internal CMP equipment to be purchased and installed, thus avoiding 6-9 months of delay.

– Second, several key cycles of learning were assisted by insightsand guidance from the external technical staff.

• Substantial benefits and time savings realized through effective utilization of CMP outsourcing.


21

MEMS over CMOS

Key Process Metrics & Constraints

n/a

2.8 um

6.5 um

Incoming Value

0.5

< 0.4 um

3.0 um

Post-CMP Target

3.02 umOxide film thickness

0.488Removal Rate (um/min)

0.2 umStep Height

ActualMetric

Critical Concerns:Thick oxide layer over CMOS

Final topography must be < 0.4um

Smooth – No sharp corners anywhere

Batch to batch consistency0

1000

2000

3000

4000

5000

6000

1 2 3 4 5 6 7 8 9 10 11 12

Run #

Rem

oval

Rat

e (A

ng/m

in)

Photos downloaded from web sites, including Sandia National Lab


22

Direct Wafer Bonding

Example #2: Inlaid Cu in TEOSIncoming topography >2.5 kA

Goal of <200 A total topography

POST-CMP TOPOGRAPHY ACHIEVED

70-90 Angstroms

Example #1: TEOS on XOxide surfaces tend to bond well

when polished to sufficiently low Ra

Incoming roughness driven by surface prep of underlying material

Sufficient oxide thickness must be deposited to remove at least 2x initial peak-to-valley roughness

Flat across

Feature

11187TEOS on AlN

37TEOS on Silicon

332

87

72

Incoming Ra (A)

7TEOS on SiC

8TEOS on Metal

7TEOS on Polysilicon

Post-CMPRa (A)Material Stack


23

3D Flash Example

• Scalability of the floating gate approach for NAND Flash appears to be coming to an end– Floating gate interference, inability to scale tunnel

oxide, and interpoly dielectric scaling fails– Issues likely insurmountable in range of 20 – 30 nm

• Some are proposing Charge Trap Flash (CTF)– TANOS– Bit-Cost Scalable (BiCS) Flash


24

Challenges with CTF

N+N+ N+N+

Vread-pass Vread-passVreadInversion Layer

ONO

To Bitline

• Vread-pass > Vtprog + margin• Vprog-pass > Vtprog + margin

• Apply to both lateral and vertical NAND CTF

Pass disturbs onselected string


25

Wish List for 3D

WISH LIST FOR 3D MONOLITHIC FLASH• Laterally scalable• Easily stackable• Reasonable program/erase voltages• High program bandwidth• Good endurance• Good retention• MLC capability• All at low cost


26

Schiltron Design

N+N+ N+N+

Vread-pass Vread-pass

VreadInversion Layer

ONO

To Bitline

1st Gate

2nd Gate

• Double-gate approach– Close electrostatic interaction for short channel control

and lateral scalability– Electrical shielding of memory charge from pass voltages

Off


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World’s Smallest DG-TFT

350 A channel thickness

48nm gatelength

CMP1

CMP2


28

String Structure

XTEM perpendicular to wordline gate direction

CMP1 CMP2


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Conclusions

• Efficient development of new products is required for any device manufacturer to remain competitive

• CMP process development can be done efficiently as a sequence of stages (STORM)– Screening Tests– Optimization– Repeatability– Marathon

• Creative approaches can enable all of the following:– Accelerate timelines– Preserve capital– Reduce cost and risk


30

Contact Info

Anyone desiring further information please contact:

Rob RhoadesChief Technology Officer

Tel: 602 426-8668Fax: 602 426-8678

[email protected]

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