azero-voltage-transitioninterleavedboostconverterand...

Hindawi Publishing CorporationAdvances in Power ElectronicsVolume 2011, Article ID 925618, 10 pagesdoi:10.1155/2011/925618

Research Article

A Zero-Voltage-Transition Interleaved Boost Converter andIts Application to PFC

Lucio dos Reis Barbosa

Electrical Engineering Department, State University of Londrina, P.O. Box 6001, 86051-990 Londrina, PR, Brazil

Correspondence should be addressed to Lucio dos Reis Barbosa, [email protected]

Received 30 June 2011; Revised 26 August 2011; Accepted 13 September 2011

Academic Editor: Jose Pomilio

Copyright © 2011 Lucio dos Reis Barbosa. This is an open access article distributed under the Creative Commons AttributionLicense, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properlycited.

An efficient power factor correction converter is presented. Two boost-topology switching cells are interleaved to minimize EMIwhile operating at lower switching frequency and soft switching to minimize losses. The result is a system with high conversionefficiency, able to operate in a pulse-width-modulation (PWM) way. Seven transition states of the ZVT converter in one switchingperiod are described. In order to illustrate the operational principle key, implementation details, including simulations, aredescribed. The validity of this converter is guaranteed by the obtained results.

1. Introduction

Reduced power factor and polluted utility voltage havebeen rising due to the increase of nonlinear loads use byresidential, commercial, and industrial customers. Nowadaysinternational regulation governing the amount of harmoniccurrent became mandatory.

Thus, the reduction of input current harmonics andhigh power factor operation is an important requirement forpower supplies. The topology usually employed in power fac-tor correction single-phase power supplies is composed by afront-end rectifier followed by a boost converter, as shown inFigure 1. In this topology, the boost converter in continuousconduction mode (CCM) with the average current controland pulse-width modulation (PWM) technique has been themost popular circuit [1–3].

High power density and fast transient response of thiscircuit can be achieved by increasing the switching fre-quency. However, the switching losses and electromagneticinterference noises will be occurred following increasing theswitching frequency. In order to improve the efficiency ofthe power factor correction (PFC) circuit, many efforts havebeen done on the soft-switching converter [4–11]. Unfor-tunately, switching losses in the approaches proposed in[6, 7] can be reduced only at the expense of much increased

current stresses of the main switch, which leads to a substan-tial increase in conduction loss.

To reduce the switching losses, initially raise the snub-bers. Example of these snubbers can be found in thereferences [12, 13] Later on appeared the quasiresonantconverters (QRCs) proposed in [14]. However, some oftheir characteristics such as load limitations and controldifficulties due to variable frequency operation restrict thepractical use of these converters. Quasi-resonant converters(PWM-QRC) [15] operate with fixed switching frequency;on the other hand they present all the other disadvantages ofthe QRC’s that limit their applications.

Nowadays there are many converters that do not presentthe limitations described above [16]. Although this converterpresents several advantages, its main switch presents currentand/or voltage stresses.

Most recent development in high-frequency converterconfiguration is a hybrid of resonant soft switching andpulse-width-modulation (PWM) control. This group of con-verters is called soft switching PWM converters, an exampleof these converters is presented in [17]. In the soft switchingPWM converters, the switches operate in resonant modeonly during switching transitions and then return to PWMoperation for the rest of a switching period.

2 Advances in Power Electronics

D

Vin

Lin

S1Co

Load

Figure 1: Power factor correction topology.

In [18] the soft-switching techniques allows operationwith much reduced switching losses and stresses enablinghigh switching frequency operation with high efficiency.

The concept of interleaving several switching cells is notnew and was originally used as a method for overcomingthe limitations of ordinary power conversion techniques anddevice technologies [19]. Recognition of the general meritsof interleaved conversion has prompted a diverse variety ofsubsequent investigations, as reflected in the literature.

In this paper, the interleaved power conversion refersto the strategic interconnection of two switching cells forwhich the conversion frequency is identical, but for which theinternal switching instants are sequentially phased over equalfractions of a switching period. This arrangement applied toPFC combined with the soft switching technique to lowerthe switching losses in the approach proposed in [18] canreduce the net ripple amplitude and raises the effectiveripple frequency of the overall converter without increasingswitching losses or main switches stresses.

The main goal of this system can therefore realize savingsin filtration and energy storage requirements, resultingin greatly improved power conversion densities withoutsacrificing efficiency.

The features of the proposed converter are discussed inthis paper, and the principle of operation, simulation, andexperimental results is presented to validate the proposedsolution.

2. Proposed Structure

A configuration of the proposed structure is shown inFigure 2. This converter is based on the interleaved boostconverter, integrated with the proposed soft switching aux-iliary circuit.

2.1. Circuit Description. As the proposed structure is derivedfrom the boost converter, there is one input inductor (LF1

and LF2) for each stage connected in parallel. The inputcurrent ripple is reduced by the parallel stages operating withdifferent phases. The diodes DA1 and DA2 are the outputdiodes and operate like the output diodes of the interleavedboost converter. The output filter and load are represented byCo and Ro.

In order to simplify the description and the explanationof the principle of operation of the proposed converter, filterinductance’s LF1 and LF2 are assumed large enough to beconsidered as ideal current sources. The voltage across Co

presents no ripple, all components are treated as being ideal,

S1

S2

LF2

DA1

DA2

DR2

Co Ro

VoLR2

SA2

DB1

DB2

Vi

iLR

−

−

−

+

++

ILF1

DR1

CR2

LR1

CR1

SA1

VCRIi

PBfuse

Figure 2: Proposed topology.

and the input current flows through freewheeling diodesDA1 and DA2 until switch SA1 or SA2 is turned on at timeto. According to its working cycle, operations modes aredescribed as follows.

2.2. Principle of Operation. The operation of the circuit willbe described considering the branch 1 (SA1 and S1), sincethe branch 2 (SA2 and S2) operates in the same way. Underthe assumption that the switching frequency (100 kHz) ismuch higher than the rectifier output frequency (120 Hz),the voltage Vi will not have a significant change. In this casethe development of the analysis will consider a DC inputvoltage, since the soft-switching strategy is not compromisedby the incoming AC line. Based on these assumptions, circuitoperations in one switching cycle can be divided into sevenstages. The seven dynamic equivalent circuits of the newboost converter during one switching period are shown inFigure 3 where the main switch S1 starts conducting at t = t2and turns off at the time interval t6, and the auxiliary switchSA1 starts at t = t0 and turns off at time interval t3. The idealrelevant waveform of the new interleaved boost is shown inFigure 4.

In this section, the analytical expressions describing theoperation of the proposed converter are presented. Thefollowing definitions are assumed:

α = ILF1

Vo

√LRCR

,

ωR(t) = 1√LRCR

,

Zo =√

LRCR

.

(1)

The resonant components are assumed to be with thesame values: LR1 = LR2 = LR and CR1 = CR2 = CR.

Stage 1 ([t0, t1], Figure 3(a)). Before t = t0, the main switchS1 maintains turn-off state, the input current ILF1 flowsthrough DA1,LF1,CF , and Ro. This stage begins when SA1

Advances in Power Electronics 3

LF1 LF1

LF1LF1

LF1

LF1

LF1

S1

S2

LF2

DA1

DA2

DR2

Co Ro

VoLR2

SA2

DB1

DB2

Vi

iLR

−

−

−

+

++

ILF1

DR1

CR2

LR1

CR1

SA1

VCRIi

S1

S2

LF2

DA1

DA2

DR2

Co Ro

VoLR2

SA2

DB1

DB2

Vi

iLR

−

−

−

+

++

ILF1

DR1

CR2

LR1

CR1

SA1

VCRIi

S1

S2

LF2

DA1

DA2

DR2

Co Ro

VoLR2

SA2

DB1

DB2

Vi

iLR

−

−

−

+

++

ILF1

DR1

CR2

LR1

CR1

SA1

VCRIi

S1

S2

LF2

DA1

DA2

DR2

Co Ro

VoLR2

SA2

DB1

DB2

Vi

iLR

−

−

−

+

++

ILF1

DR1

CR2

LR1

CR1

SA1

VCRIi

S1

S2

LF2

DA1

DA2

DR2

Co Ro

VoLR2

SA2

DB1

DB2

Vi

iLR

−

−

−

+

++

ILF1

DR1

CR2

LR1

CR1

SA1

VCRIi

S1

S2

LF2

DA1

DA2

DR2

Co Ro

VoLR2

SA2

DB1

DB2

Vi

iLR

−

−

−

+

++

ILF1

DR1

CR2

LR1

CR1

SA1

VCRIi

S1

S2

LF2

DA1

DA2

DR2

Co Ro

VoLR2

SA2

DB1

DB2

Vi

iLR

−

−

−

+

++

ILF1

DR1

CR2

LR1

CR1

SA1

VCRIi

(a) (b)

(c) (d)

(e) (f)

(g)

Figure 3: Topology modes.


S1

SA1

ILR

VCR

ISA1

VSA1

(Vo)

(Vo)

(Vo)

IS1

VS1

t0 t1 t2 t3 t4 t5 t6 t7(ILF1)

(ILF1)

(ILF1)

Figure 4: Ideal relevant waveforms of the topology.

turns on with ZCS at t = t0. The resonant inductor LR1

charges linearly due to output voltage Vo from zero to ILF1.The stage ends when the resonant current reaches ILF1 anddiode DA1 turns off with ZVS at t = t1. The resonant iLR(t)and vCR(t) can be, respectively, described as

iLR(t) = Vo

LRt,

vCR(t) = 0,

Δt1 = α

ωRt.

(2)

Stage 2 ([t1, t2], Figure 3(b)). In this stage, the current ILF1

remains flowing through auxiliary switch SA1. The remainingsemiconductors are in the off state. The resonant iLR(t) andvCR(t) can be, respectively, described as

iLR(t) = ILF1,

vCR(t) = 0,

Δt2 = t2 − t1.

(3)

In this time interval main switch S1 is turned on in a ZCSand ZVS way.

ILR

t1 t2

t0t6 t7

t5 t4

t3

Vo VCR

IL

Figure 5: State-space phase.

G

α

D = 0.7

D = 0.6

D = 0.5

D = 0.4D = 0.3

D = 0.2

4

3.5

3

2.5

2

1.5

1

0.5

054.543.532.521.51

Figure 6: Static gain curves.

Stage 3 ([t2, t3], Figure 3(c)). In this stage, the resonancebegins when SA1 turns off with ZVS at t = t2. The resonantroute proceeds by way of LR1,CR1, and DR1. The resonantcurrent iLR(t) decreases, and the resonant voltage vCR(t) alsodecreases via the resonance of LR1 and CR1. This state endswhen the voltage vCR(t) reaches output voltage Vo at t = t3.The resonant iLR(t) and vCR(t) can be, respectively, describedas

iLR(t) = ILF1 cos(ωRt),

vCR(t) = ZoILF1 sin(ωRt),

Δt3 = 1ωR

arcsin(

1α

).

(4)


I0

ILF1

ILF2

ii

DT T/2

DT T/2

DT T/2

DA2i

DA1i

iD

T DT T/2 T

DT T/2 T

DT T/2 T

T

T0 0

0

0

0

0

I0/2

I0/2

<I0/2

I0/2

I0/2

<I0/2

Figure 7: Dual Boost converter ripple waveforms.

T

ii

Iavg

t(s)

(A)

I(t)

Figure 8: Average current control.

At the end of this stage iLR is equal to

iLR(t3) = ILF1

α

√α2 − 1. (5)

Stage 4 ([t3, t4], Figure 3(d)). In this mode iLR(t) reduces tozero. This mode comes to an end at t4 when iLR(t) becomeszero. The expressions for iLR(t) and vCR(t) are

iLR(t) = −Vo

LRt +

ILF1

α

√α2 − 1,

vCR(t) = Vo,

Δt4 =√α2 − 1ωR

.

(6)

Stage 5 ([t4, t5], Figure 3(e)). The main switch is conducting,and the input current flows through the input inductor and

power switch. All diodes are blocked, and the input inductorstore energy. The equations that describe this mode are

iLR(t) = 0

vCR(t) = Vo

Δt5 = t5 − t4

(7)

Stage 6 ([t5, t6], Figure 3(f)). At the instant t5, switch S1

is turned off in a ZVS way, and the energy stored in theinput inductor LF1 is transferred to the output capacitor CF

through the diode DS1 and also to the resonant capacitor CR1.In this time interval, CR1 linearly discharges to zero voltage.The resonant iLR(t) and vCR(t) can be, respectively, describedas

iLR(t) = 0,

vCR(t) = Vo − ILF1

CRt,

Δt6 = 1αωR

.

(8)

Stage 7 ([t6, t7], Figure 3(g)). In this stage, diode DA1 con-duces the LF1 current. The duration of this stage is definedby switch modulation. At the end of this time interval,switch SA1 turns on, and the next operating cycle begins. Theresonant iLR(t) and vCR(t) can be, respectively, described as

iLR(t) = 0,

vCR(t) = 0,

Δt7 = t7 − t6.

(9)

The State-space phase of the converter can be representedby a diagram shown in Figure 5. It is only valid for α >1, physically, for low values of load current, the energystored in resonant inductor would not be sufficient to charge


∼

∼Power

conversion

Current

sensor

Vo

PWM

Current

regulator

K

Co

A

C

BVoltage

regulator

Iref

+

+

−

+−

−

VrefUC3854filter

Load

Vac

Low-pass

A · BC2

Figure 9: System realization with UC3854.

resonant capacitor to output voltage, which makes converterto perform as a hard-switched system.

The static gain, which represents the ratio between theoutput and the input voltages as function of the duty cycle,can be obtained by analyzing the waveforms of the inductorLF1 and observing the time intervals

t0 t1 : vLF1 = −(Vo −Vi),

t1 t5 : vLF1 = Vi,

t5 t6 : vLF1 = Vi − ILF1

CRt,

t6 t7 : vLF1 = −(Vo −Vi).

(10)

After the mathematical analyses, the expression of the staticgain can be obtained

G = Vo

Vi= 1

1−D − (1/TsωR)(−α + (1/2α)), (11)

where: Ts is switching period and D is duty cycle.The expression of the static gain is illustrated in Figure 6.

3. Results and Discussion

The benefits of interleaving can be understood intuitivelyusing a simple graphical analysis to show how the outputpower is shared between two boost switching cells connectedin parallel.

For simultaneous synchronous operation (wherein thecommutation instances of the two controlled switches areidentical), the circuit performance is equivalent to a singleboost converter with equal total energy storage and equaltotal semiconductor die area. The inductor and diode ripple

Drive

Drive

Drive

Drive

gate of SA1

Monostable 1

Monostable 2

Frequencydivider

UC3854

gate of S1

gate of SA2

gate of S2

Figure 10: Block diagram of control circuit.

current waveforms that result are shown in Figure 7 as solidones.

If these same converter cells are interleaved, such thatthe commutation instances of the second switch are delayedrelative to those of the first switch by half a switching period,the resultant ripple waveforms are those shown as dashedlines in Figure 7. Compared to the noninterleaved case withequal energy storage, the interleaved ripple waveforms havesmaller amplitudes and increased frequencies, reducing thefiltration requirements.

The rectifier is designed to operate in continuous-conduction mode (CCM). It was employed UC3854 as the


80

40

0

−1019.989 ms 19.992 ms 19.995 ms

U(2)

Time

U(S1)

I(S1)∗ 10

I(S1)∗ 10

(a)

80

40

0

−1019.989 ms 19.992 ms 19.995 ms

U(4)

Time

U(SA1)

I(SA1)∗ 10

I(SA1)∗ 10

(b)

80

40

0

−1019.989 ms 19.992 ms 19.995 ms

U(6)−U(2)

Time

I(LR1)∗ 15

I(LR1)∗ 15 U(CR1)

(c)

Figure 11: Simulation waveforms.

controller, which prescribes the shape and the frequencyof the input current due to its inherently synchronousfeedback loop. The synchronous signal is sensed from arectified sinusoidal waveform. This signal is accessible atthe output of the rectifier in the usual PFC boost converter[20]. Thus, a signal bridge rectifier is necessary to obtainthe desired synchronous signal and the rms input voltagefor the control IC. Hall effect sensor for detecting the inputcurrent is installed for the average current mode control. Thereference current is then generated by a multiplier/dividercombination of the synchronous feedback loop, outputvoltage feedback loop, and input voltage feed-forward loop.As the input voltage changes, which is the case in this PFCapplication, reference current monitors the input current inorder to obtain almost unity power factor. Figure 8 showsthe principle of the average current mode, used as a controlreference in this project.

The simplified scheme of the controller and the powerstage are shown in Figure 9.

The block diagram circuit to drive the four switchesusing the UC3854 PWM output (GTDrv Pin) is shown inFigure 10.

3.1. Simulation Results. The proposed converter was simu-lated using commercially available PSIM software. The maincircuit components were LF1 = LF2 = 300μH, CF = 680μF.The resonant components were LR1 = LR2 = 5μH and CR1 =CR2 = 3.9 nF. Figure 10 shows simulated waveforms obtainedwith the converter operating with input voltage Vi = 50 V,duty cycle D = 0.25, output load Ro = 10Ω, and switchingfrequency fs = 100 kHz.

It can be seen from Figures 11(a) and 11(b) that theconverter switches can operate with soft switching. Theauxiliary switch, during the turn-on period, operates withZCS as the resonant components delay the rise in switchcurrent and makes it fall to zero voltage during the turn-offperiod. It should be noted that the voltage across the mainswitch is zero during the turn-on and turn-off periods, whichis characteristic of this soft-switched converter.

Figure 11(c) shows the resonant voltage and currentwaveforms. It should also be noted that switches voltage andcurrent stresses are equivalent to conventional hard-switchedinterleaved converter.

3.2. Experimental Results. A prototype circuit was con-structed to verify the waveforms predicted above. The values


Tek stop: 50 MS/s 3763 Acqs

T

21

Ch1 Ch1100 V 1 V M 1 μs 6 VCh2

VS1 (100 V/div)IS1 (2 A/div)

(a)

6 Acqs

4 V

Tek stop: 50 MS/s

T

T21

Ch1 Ch1100 V 1 V M 1 μsCh2

VSA1 (100 V/div)

VSA1 (2 A/div)

(b)

301 AcqsTek : 50 kS/s

100 V/divVin

Iac

4 A/div

5 ms/div

5 V 5 ms100 V

T

Ch1 Ch1Ch2

Hold

2

(c)

Figure 12: Experimental waveforms.

of the components used experimentally are the same asthose specified in the simulation. The used switches were theMOSFET IRF840, and the diodes were HFA15TB60.

The specifications considered for implementation andtest of the proposed converter are

input voltage: Vi = 127 Vrms,

output voltage: Vo = 200 V,

output power: Po = 0.8 kW,

switching frequency: fs = 100 kHz.

The experimental waveforms obtained in laboratory areshown from Figures 12(a)–12(c) and were acquired usinga THS720 Tektronix oscilloscope and a Tm 502A Tektronixcurrent gauge.

Figure 12(a) shows the main switch voltage and currentwaveforms. As it is observed, this switch operates underzero voltage and current during the turn-on period and zerovoltage during the turn-off period.

Figure 12(b) shows the waveforms of voltage and currentin the auxiliary switch. As seen in this photograph, it operateswith ZCS during the turn-on period and ZVS during theturn-off period.

Figure 12(c) shows the input voltage and current wave-forms. This result shows that the obtained power factor issuitable for international standards.

The discrepancy between theoretical and practical valuesis due to parasitic oscillations, which were not considered inthe data acquisition.

Advances in Power Electronics 9η

(%)

Po (Kw)

ZVT converter

Hard converter

100908070605040302010

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Figure 13: Curve of efficiency versus output power.

The nominal power factor exceeds 0.98, and the efficiencyof the power circuit reached at nominal load is equal to 96%,as shown in Figure 13.

These values were obtained using a Yokogawa WT230Digital Power Meter. To provide a comparative analysis aboutthe efficiency levels achieved with the laboratory prototype,a converter without the proposed soft-commutation cell wasalso built in the laboratory using the same layout and thesame components. Thus, in this situation, one can concludethat significant efficiency improvements can be achieved withthe application of the proposed soft commutation cell, asdepicted in Figure 13.

4. Conclusion

In this paper an improved ZVT interleaved boost PFCconverter is presented. An auxiliary circuit for interleavedboost PFC converter is analyzed. The proposed topology wassimulated via PSIM software, and an experimental prototypewas implemented. As seen from the results, the main switchesare turned on and turned off under ZVS conditions. Also, theauxiliary switch and the other diodes used in the auxiliarycircuit are turned on and/or off with ZVS and/or ZCSconditions.

The simulation and experimental results show that thetotal switching losses of the interleaved topology are reducedby applying the proposed auxiliary circuit. It can be also seenthat the power factor correction is achieved.

Acknowledgment

The author gratefully acknowledges the support provided byCNPq.

References

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[2] M. Kazerani, P. Ziogas, and G. Joos, “Programmable inputpower factor correction methods for single phase diode

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[7] S. Gataric, D. Boroyevich, and F. Lee, “Soft-switched single-switch three-phase rectifier with power factor correction,”in Proceedings of the 9th Annual Applied Power ElectronicsConference and Exposition (APEC ’94), pp. 738–744, Orlando,Fla, USA, 1994.

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[16] L. Barbosa, E. Coelho, L. Freitas, J. Vieira, and V. Farias,“PWM soft-switched converters with a single active switch,”IEEJ Transactions on Industry Applications, vol. 117, no. 11, pp.1305–1310, 1997.

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