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Authors: Tong Li, Dan Baumberger, David A. Koufaty, and Scott Hahn [Systems Technology Lab, Intel Corporation] Source: 2007 ACM/IEEE conference on Supercomputing Efficient Operating System Scheduling for Performance- Asymmetric Multi-core Architecture

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Outline Introduction Scheduling For Performance-Asymmetric Architecture Evaluation Conclusion 2

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Introduction 3 Over the next decade, we expect to see processors with tens and even hundreds of cores on a chip. Resent research advocates the performance- asymmetric multi-core architectures. core1 core3 core4 core2 same instruction set different performance characteristics Deliver higher performance at lower cost

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Introduction (cont.) 4 OS schedulers traditionally assume homogeneous hardware and do not directly work well on asymmetric architectures. This paper presents AMPS (Asymmetric Multi- Processor Scheduler) that efficiently supports both SMP- and NUMA-style performance-asymmetric architectures.

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Outline Introduction Scheduling For Performance-Asymmetric Architecture Evaluation Conclusion 5

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Scheduling For Performance- Asymmetric Architecture 6 Run-queue models: Distributed run-queue model Centralized run-queue model Scheduling policies: Thread-dependent policies Thread-independent policies

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Scheduling For Performance- Asymmetric Architecture (cont.) 7 Optimization metrics: Performance Fairness Repeatability Three components of AMPS: 1. Asymmetric-aware load balancing 2. Faster-core-first scheduling 3. NUMA-aware migration

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Asymmetric-Aware Load Balancing 8 AMPS approximate core computing power using core frequencies. Quantifying core computing power Define a cores scaled computing power as P. Let the core with lowest frequency have P=1. Let the core have F times higher frequency have P=FS, where S is a scaling factor and S