auo 036 ic data

Doc. Version 0.5

Total Page 25

Date 2006/11/30

Product Specification

6.5" COLOR TFT-LCD MODULE

MODEL NAME: C065VL01 V0

<>Draft Version

< >Preliminary Specification

< >Final Specification

© 2006 AU Optronics

All Rights Reserved

DO NOT COPY

Note: The content of this specification is subject to change

Version 0.5

Page: 2/25

Record of Revision

Version Revise Date Page Content

0.0 2006/02/10 First draft.

0.1 2006/06/01 5 D-1-a updated connector type, pin number & pin assignment

9 D-3-c updated LED voltage, current and life time

13 E updated response time

16 G updated drawing

18 Added typical application circuit and power on/off sequence

0.2 2006/07/21 5 Revise connector type, pin number & pin assignment

14 Revise Viewing angle typical value in Optical characteristics

17 Update outline drawing

19 Revise application note

21 Revise power on/off sequence

0.3 2006/09/06 10 Revise LED backlight driving voltage

0.4 2006/10/03 10 Revise AVDD & VGH typical value

19-24 Update Application Notes contents

0.5 2006/11/30 10 Revise AVDD values

25 Add important note for customer system design

Version 0.5

Page: 3/25

Contents

A. Summary......................................................................................................................... 4

B. Features .......................................................................................................................... 4

C. Physical Specifications .................................................................................................... 4

D. Electrical Specifications................................................................................................... 5

1. Pin Assignment ........................................................................................................ 5

2. Absolute Maximum Ratings...................................................................................... 9

3. Electrical Characteristics ........................................................................................ 10

E. Optical specifications..................................................................................................... 14

F. Reliability Test Items...................................................................................................... 16

G. Outline Dimension ......................................................................................................... 17

H. Packing Form ................................................................................................................ 18

I. Application Notes .......................................................................................................... 19

1. Typical Application Circuit....................................................................................... 19

2. Power On/Off Sequence ........................................................................................ 21

Version 0.5

Page: 4/25

A. Summary

C065VL01 is an LTPS (Low Temperature Poly-Silicon) type TFT (Thin Film Transistor)

LCD (Liquid crystal Display). This model is composed of a TFT-LCD panel, a driver IC, a FPC

(flexible printed circuit), and a backlight unit.

B. Features

6.5” display size in 16:9 aspect ratio

800RGBx480(WVGA) resolution for wide view format

550nits high brightness with high power LED backlight

300:1 high contrast

Wide viewing angle technology, best at 6 o’clock direction

Parallel RGB I/F of 6-bit color depth

Power supply: 3.3V for panel and 13.2V for LED

C. Physical Specifications

NO. Item Unit Specification Remark

1 Display Resolution dot 800RGB(H)×480(V)

2 Active Area mm 143.40(H)×79.2(V)

3 Screen Size inch 6.5(Diagonal)

4 Pixel Pitch mm 0.05975×RGB(H)×0.165(V)

5 Color Configuration -- R. G. B. Stripe Note 1

6 Color Depth -- 262K Colors Note 2

7 Overall Dimension mm 157.2(H) × 89.2(V) × 5.3(T) Note 3

8 Weight g 120±5%

9 Panel surface treatment -- AG(25% haze) & with SWV film

10 Display Mode -- Normally White

11 Backlight Unit -- High Power LED’s

Note 1: Below figure shows the dot stripe arrangement.

Version 0.5

Page: 5/25

Note 2: The 262K color display depends on 6-bit data signal input.

Note 3: Not including the backlight cable. Refer to Section G, “Outline Dimension” for

further information.

D. Electrical Specifications

1. Pin Assignment

a. TFT-LCD panel driving section

Connector type: FH16-80S-0.3SH or compatible

Pin no Symbol I/O Description Remark

1 VGH P Power for LCD

2 DIO2 I/O Start pulse signal

3 AVDD P Analog power for source driver

4 CHNSL1 I Control signal, please set to ‘1’

5 CHNSL0 I Control signal, please set to ‘1’

6 VCC P Digital power for source driver

7 POL I Output data polarity control signal

8 REV I Data inversion control signal output for source driver

9 LINV I Polarity control signal

10 MUX2 I Source driver control signal

R G B R G B

R G B R G B

R G B

……………………………

….

……………………………

….

……

……

…

……

……

( 1 2 3….……… ………..…………….2398 2399 2400)

( 1…

……

……

……

……

..480)

Version 0.5

Page: 6/25



13 GAMA I Source driver control signal ,please set to ‘1’

14 LD2 I Source driver control signal

15 LD1 I Source driver control signal

16 OP1 I Output buffer driving capacity control signal

17 OP0 I Output buffer driving capacity control signal

18 MODE I Control signal , please set to ‘1’

19 GND P Digital ground

20 B5 I Blue data

21 B4 I Blue data

22 B3 I Blue data

23 B2 I Blue data

24 B1 I Blue data

25 B0 I Blue data


27 AGND P Analog ground

28 V14 P Gamma reference voltage














42 AVDD P Analog power for source driver


44 G5 I Green data

45 G4 I Green data

46 G3 I Green data

Version 0.5

Page: 7/25

47 G2 I Green data

48 G1 I Green data

49 G0 I Green data


51 R5 I Red data

52 R4 I Red data

53 R3 I Red data

54 R2 I Red data

55 R1 I Red data

56 R0 I Red data


58 PRSEL1 I Source driver control signal , please set to ‘0’

59 PRSEL0 I Source driver control signal , please set to ‘1’

60 SHL I Source driver horizontal shift direction control

61 CLK I Output data clock for source driver

62 EDGSL I Source driver control signal

63 RSTB I Reset pin, low active

64 VCC P Digital power for source driver

65 AGND P Analog ground

66 DIO1 I/O Start pulse signal

67 SW6 I Control signal






73 VGL P Power for LCD

74 VGH P Power for LCD

75 CK I Control signal

76 XCK I Control signal

77 VST I Control signal

78 NC not connected

79 NC not connected

80 VCOM I Common electrode voltage

Version 0.5

Page: 8/25

I: Input pin; O: Output pin; P: Power pin

Note1: For pin sequence arrangement, please refer to the figure as below:

Pin 80 Pin 1

Version 0.5

Page: 9/25

b. Block Diagram

c. Backlight driving section

Connector type: JST PHR-2 or compatible

No. Symbol I/O Description Remark

1 GND - Ground for backlight unit --

2 HI I Power supply for backlight unit (High voltage) --

2. Absolute Maximum Ratings

Product Specification Items Symbol

Min. Typ. Max. Unit

VCC -0.3 4 V

AVDD -0.5 13.5 V

VGH -0.5 17 V

VGL -17 0.5 V

Power Voltage

VGH-VGL -0.5 26.5 V

Vin -0.3 VCC+0.3 V Input Signal Voltage

VCOM - - - V

Operating Temperature Topa -30 85 ˚C

Storage Temperature Tstg -40 95 ˚C

Version 0.5

Page: 10/25

3. Electrical Characteristics

a. Typical operating conditions

Product Specification Items Symbol

Min. Typ. Max. Unit

VCC 3.0 3.3 3.6 V

AVDD 8 10.5 12 V

VGH 10 13.5 15 V

VGL -5 -7 -9 V

Power Voltage

VCOM 0.35*AVDD 0.5*AVDD 0.65*AVDD V

VIH 0.7*VCC — VCC V Input H/L level Voltage

VIL 0 — 0.3VCC V

Note 1: All value should be measured under the condition of GND=AVss=0V

Note 2: The panel is designed to prevent the current leakage for the best display performance.

If shorter discharge time is desired when system power off, then extra discharge

circuit may be required at customer’s side.

b. Current Consumption

Parameter Symbol Condition Min. Typ. Max. Unit

IGH VGH=12V TBD uA

IGL VGL=-7V TBD uA

ICC VCC=3.3V TBD mA

Current

For

Driver IDD AVDD=10V TBD mA

c. LED Backlight driving condition

Parameter Symbol Condition Min. Typ. Max. Unit

Voltage Vf Note 1 16.5 TBD Vrms

Current If Note 1 150 mA

LED life time Note 2 10000 - Hrs

Note 1: Panel surface temperature should be kept less than content of “D.2. Absolute

maximum ratings”.

Note 2: The ”LED life time” is defined as the module brightness decrease to 50% original

brightness at Ta=25, If=150mA

d. AC Timing Conditions

Characteristics (VCC=3V, AVDD=10V, AVSS=GND=0V, TA=25)

Version 0.5

Page: 11/25

Parameter Symbol Min. Typ. Max. Unit Conditions

CLK frequency Fclk=1/Tclk - - 45 MHz EDGSL=”0”

CLK frequency Fclk=1/Tclk - - 22.5 MHz EDGSL=”1”

CLK pulse width Tcw 6 - - ns

Data set-up time Tsu 4 - - ns X1 ~ X5, REV and

DIO1/2 to CLK

Data hold time Thd 2 - - ns

Propagation delay of DIO1/2

high to low level Tphl 6 10 15 ns CL=25pF

Propagation delay of DIO1/2

low to high level Tplh 6 10 15 ns CL=25pF

Time that the last data to LD1 Tld1 1 - - Tclk

LD1 pulse width Twld1 2 - - Tclk

Time that LD1 to DIO1/2 Tlds 5 - - Tclk

Time that LD1 to LD2 Tld2 2 - - Tclk

LD2 pulse width Twld2 1 - - Tclk

MUX/LINV/POL setup time Tsu2 6 - - ns

MUX/LINV/POL hold time Thd2 6 - - ns

Output stable time Tst - - - us Refer to LD2 timing

chart

e. Timing Diagrams

Timing Diagram 1 ( CHNSL=”1”, others setting = Default )

<< EDGSL= ”0”, Default >>

Tcph

Tsu

Tplh

Thd

Last dataFirst data Second data

Tphl

Tsu Thd TcwTcw

1 2

70% 70%

70% 70% 70%

70%

70% 30%

70% 70%30%

Dio1/2

CLK

Dio1/2

(input)

Data,

REV

800799

>Thd

70%

70%

>Tsu

Version 0.5

Page: 12/25

<< EDGSL= ”1”>>

Tcph

Tsu

Tplh

Thd

Tphl

Tsu Thd TcwTcw

1 2

70% 70%

70% 70% 70%

70%

70% 30%

70% 70%30%

Dio1/2

CLK

Dio1/2

(input)

Data,

REV

40039970%

----Firstdata

-- -- -- --Lastdata

Tsu Thd

dataSecond

30%

>Thd >Tsu

Timing Diagram 2

LD1 Timing Chart

CLK

LD1

DIO1/2

(Input)

LD2

70%

70%

70%

70%

Last data

30%

Tld1 Twld1

Tlds

Tld2

Remark: During source output pre-charging are no relationship (Tld2) of the LD1 and LD2.

LD2 Timing Chart

Version 0.5

Page: 13/25

LD2

MUX0 / MUX1 / MUX2LINV / POL

S1 ~ S400

Tsu2 Thd2

70%30%

70% 70%

30% 30%

6-bit accuracy

Tst

70%

30%

Hi-Z Hi-Z

Twld2

6-bit accuracy

Version 0.5

Page: 14/25

E. Optical specifications

Item Symbol Condition Min. Typ. Max. Unit Remark

Response time Rise

Fall

Tr

Tf θ=0°

-

-

10

15

-

-

ms

ms Note 3,5

Contrast ratio CR

At optimized

Viewing

angle

200 300 - - Note 4, 5

Viewing angle

Top

Bottom

Left

Right

CR10

-

-

-

-

40

60

55

55

-

-

-

-

deg. Note 5

Brightness YL θ=0° 450 550 - - Note 1, 2,

6,7

x θ=0° - 0.33 - - White chromaticity

y θ=0° - 0.33 - -

Note 1, 2,

6,7

Note 1: Ambient temperature =25±3˚C, Humidity=45～85﹪RH, and LED current If = 150 mA.

To be measured in the dark room under 10 Lux.

Note 2:To be measured on the center area of panel with a viewing cone of 1° by Topcon

luminance meter BM-7, after 15 minutes operation.

Note 3: Definition of response time:

The response time is defined as the time interval between the 10% and 90% of

amplitudes. The output signals of photo detector are measured when the input

signals are changed from “black” to “white”(falling time) and from “white” to

“black”(rising time).

Sig

na

l(Re

lativ

e v

alu

e)

"Black"

Tr Tf

"White""White"

0%10%

90%100%

Note 4. Definition of contrast ratio:

Contrast ratio is calculated with the following formula.

Photo detector output when LCD is at “White” state

Photo detector output when LCD is at “Black” state

Version 0.5

Page: 15/25

Contrast ratio (CR)=

Note 5. Black reference voltage data =V1 or V4

White reference voltage data =V2 or V3

(For definition of V1, V2, V3 & V4, please refer to section I.1)

The 100% transmission is defined as the transmission of LCD panel when all the

input terminals of module are electrically opened.

Note 6. Brightness and White Chromaticity are measured at the display center.

Note 7. For definition of viewing angle please refer to figure as below.

Version 0.5

Page: 16/25

F. Reliability Test Items

No. Test items Conditions Remark

1 High temperature storage Ta= 95 240Hrs

2 Low temperature storage Ta= -40 240Hrs

3 High temperature operation Ta= 85 240Hrs

4 Low temperature operation Ta= -30 240Hrs

5 High temperature and high

humidity Ta= 60˚C, 90% RH 240Hrs Operation

6 Heat shock -30˚C ~85˚C /100 cycles 1Hrs/cycle Non-operation

7 Electrostatic discharge ±200V,200pF(0Ω)

once for each terminal Non-operation

Frequency range 8~33.3Hz

Stoke 1.3mm

Sweep 2.9G,

33.3~400Hz

Cycle 15min.

8 Vibration

2 hours for each direction of X, Z

4 hours for Y direction

JIS D1601,A10

Condition A

9 Mechanical shock 100G, 6ms, ±X,±Y,±Z

3 times for each direction

10 Vibration (with carton)

Random vibration:

0.015G2/Hz from 5~200Hz

–6dB/Octave from 200~500Hz

IEC 68-34

11 Drop (with carton) Height: 60cm

1 corner, 3 edges, 6 surfaces

Note 1: Ta: Ambient temperature.

Note 2: In the standard conditions, no display function NG is allowed. All the cosmetic

specification is judged before the reliability stress.

Version 0.5

Page: 17/25

G. Outline Dimension

A-A

14

3.4m

m*7

9.2m

m

Version 0.5

Page: 18/25

H. Packing Form

I.

TAPE CREPED PAPERFILM PROTECT

Version 0.5

Page: 19/25

J. Application Notes

1. Typical Application Circuit

Q1MCH3209

2

13

CVGH

VCOM_DC_ADJ

DVCC

C642.2uF-1206

1 2

B5

R?10k

12

VEEO

LD2

R35OPEN

12

R360

12

SH

L

VGL

SW

1

R34

8.66k

12

G4

SW

4

33

PR13

18

27

36

45

AUO-036Y1

(TQFP120)

1 2 3 4 5 6 7 8 9 10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

605958575655545352515049484746454443424140393837363534333231

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

919293949596979899

100101102103104105106107108109110111112113114115116117118119120

DV

CC

XS

TB

PX

CS

XC

KS

DI

MX

SL

PS

L0

PS

L1

TS

IN1

DG

ND

XR

ST

IMO

DV

SY

NC

HS

YN

CD

ET

SIN

2T

SIN

3C

LK

DG

ND

BI7

BI6

BI5

BI4

BI3

BI2

BI1

BI0

GI7

GI6

DG

ND

DGNDBO3BO4BO5LD1LD2

MUX0MUX1MUX2REVPOL

DIO2DVCCDGNDTSIN4

RI0RI1RI2RI3RI4RI5RI6RI7GI0GI1GI2GI3GI4GI5

DVCC

DG

ND

SW

1S

W2

SW

3S

W4

SW

5S

W6

TS

OU

T1

DIO

1D

GN

DD

CL

KS

HL

DV

CC

DG

ND

RO

0R

O1

RO

2R

O3

RO

4R

O5

GO

0G

O1

GO

2G

O3

GO

4G

O5

BO

0B

O1

BO

2D

VC

C

DVCCVCKXVCKVSTD2UU2DVGLVGHCVGHCNCPVEEIVEEOVDDIVDDOAVDDFBAVDDCOMINVCOMAGNDTSOUT2FBCAPAVCCAGNDPVGHNCDVCCDRVDGND

33

PR181

82

73

64

5

CAP

R5

R76

33

1 2

AVDD

SW

6

VDDO

VDDI

33

PR191 82 73 64 5

VEEO

PS

L0

AG

ND

_P

WM

VDDO

PSL0

VEEI

DRV

VGH

VCC

C37

1nF

C610.1uF

B1

R1

33

PR221 82 73 64 5

C65

2.2

uF

12

CK

G0

33

PR16

18

27

36

45

AVDDFB

DVCC

VCC

DC

LK

VCC

R2888.7K

12

B2

VST

L74.7uH

XCK

DIO2

DIO

1

R23

10K

12

AVCC

LD1

B3

PSL1

PVGH

G1

T-CON setting

XSTBP

AVDDFB

MUX0

VCC

33

PR15

18

27

36

45

DVCC

VEEO

VEEI

C580.1uF

C590.1uF

REV

B0

33

PR17

18

27

36

45

B4

33

PR14

18

27

36

45

C600.1uF

AVDDFB

G5

XS

TB

P

SB07

D3

G3

R4

VGH

C620.1uF

G2

C350.1uF

12

VGH

COMIN

CVGH

PS

L1

VDDI

SW

3

R30560

R3710k

12

C3610uF

MUX2

FB

MXSL

C69

10nF

12

AVDDCOMIN

VCC

C6

81

uF1

2

C66

2.2

uF

12

MX

SL

C22OPEN

C3410uF

R33OPEN

12

AVCC

R0

R3210k

12

DRV

SW

5

R38OPEN

12

R3

POL

G

S

DQ2

CPH3414-N MOS

1

2

3

AVDDFB

FB

R22

100K

13

2

C67

0.1

uF

12

SW

2

C21OPEN

12

C570.1uF

R?OPEN

12

C630.1nF

12

VCOM

CAP

VDDI

MUX1

33

PR211 82 73 64 5

R2

PVGH

33

PR201 82 73 64 5

VGL

VDDI

C560.1uF

AVDD

U4

EL5220C

1234

8765

OUTA-INA+INAVS-

VS+OUTB

-INB+INB

AUO-036 Circuit design

Version 0.5

Page: 20/25

V7

C41

0.1uF

1 2

V14

V10

R55

2.7K

1 2

V11

R45

820

1 2

R46

0

1 2

R52

0

1 2

R38

2.2K

1 2

R35

820

1 2

V1

3

R61

1K

1 2

R51

2.7K

1 2

C46

0.1uF

1 2

R56

56

1 2

R42

100

1 2

R47

15K

1 2

V1

C49

0.1uF

1 2

V2

V9

C51

0.1uF

1 2

V7

C40

0.1uF

1 2

R49

820

1 2

C38

0.1uF

1 2

R60

0

1 2

AVDD

C48

0.1uF

1 2

L8

BEAD

R54

100

1 2

C42

0.1uF

1 2

R36

0

1 2

V12

R57

5.1K

1 2

R43

2.7K

1 2

R44

0

1 2

R41

1.5K

1 2

R40

56

1 2

V5

C50

0.1uF

1 2

R58

2.2K

1 2

R50

0

1 2

C43

0.1uF

1 2

C39

0.1uF

1 2

R37

5.1K

1 2

C44

0.1uF

1 2

R48

0

1 2

V13

C47

0.1uF

1 2

V6V4

R62

0

1 2

C45

0.1uF

1 2

R53

1.5K

1 2

V3

R39

2.7K

1 2

AGND

V8

R59

820

1 2

Gamma Circuit

AVDD

C55C-1206-4.7uF-25V

12

AGND

G3

LD1

REV

VCC

R8010k

12

C74C-1206-4.7uF-25V

12

EDGSLCHNSL0

SHL

R8410k

12

SW1

VCC

SW2

GND

G4

C52C-1206-4.7uF-25V

12

VCC

LD2

R85OPEN

12CHNSL1

R8110k

12

AVDD

R4

AGND

SW3

GND

XCK

R2

R86OPEN

12

V13

VCC

GND

B1

AVDD

NC

LINVOP0

VCC

R940

12

VCC

R3

R93OPEN

12

GAMA

R83OPEN

12

MUX1

G1

VCCVCC

Panel setting

VCC

SW5

R7810k

12

VST

MUX2

GAMA PRSEL1

MUX0

V6

V4

GND

R82OPEN

12

R910

12

C54C-1206-4.7uF-25V

12 EDGSL

NC

DIO2

R7910k

12

R920

12

VCC

CHNSL1

G0

V3

R?OPEN

12

V11

C53C-1206-4.7uF-25V

12

VGH

V7

B3

V8

OP0

V10

R90OPEN

12

R?0

12

DIO1

V9

OP1

B4

B0VCC

V14

V5

AGND

B2

VGL

SW4

POL

GND

R87OPEN

12

L9

Chip Bead

1 2

PRSEL0

G2

DCLK

V2

PRSEL1

R1

PRSEL0

B5

R5GND

R7710k

12

VGH

VGH

R89OPEN

12

R88OPEN

12

MODE

CON1FH16-80S-0.3SH(05) 80pin 0.3mm

123456789

1011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980

82

81

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980

82

81

V1

G5

VGLVCOM

LINV

VCC

RSTB

OP1

SW6

CHNSL0

CK

MODE

VCC

V12

R0

VCOM

Panel Setting

Version 0.5

Page: 21/25

2. Power On/Off Sequence

l

Version 0.5

Page: 22/25

Note1: The using of standby mode signal XSTBP, please refer to AUO-036Y1 spec. P28.

Note2: Panel reset signal RSTB and ASIC reset signal XSTBP, please follow the power on/off

sequence.

Note3: Input mode selection signal IMOD

IMOD=”Low” : DE mode, please set VSYNC and HSYNC to “high”.

IMOD=”high” : HSYNC/VSYNC mode, please set DE to “low”.

Version 0.5

Page: 23/25

AUO-036 Package (TQFP120)

Pin Signal Pin Signal Pin Signal Pin Signal Pin Signal Pin Signal

1 DVCC 21 BI6 41 RI4 61 DVCC 81 DGND 101 CP

2 XSTBP 22 BI5 42 RI3 62 BO2 82 DIO1 102 VEEI

3 XCS 23 BI4 43 RI2 63 BO1 83 TSOUT1 103 VEEO

4 XCK 24 BI3 44 RI1 64 BO0 84 SW6 104 VDDI

5 SDI 25 BI2 45 RI0 65 GO5 85 SW5 105 VDDO

6 MXSL 26 BI1 46 TSIN4 66 GO4 86 SW4 106 AVDDFB

7 PSL0 27 BI0 47 DGND 67 GO3 87 SW3 107 AVDD

8 PSL1 28 GI7 48 DVCC 68 GO2 88 SW2 108 COMIN

9 TSIN1 29 GI6 49 DIO2 69 GO1 89 SW1 109 VCOM

10 DGND 30 DGND 50 POL 70 GO0 90 DGND 110 AGND

11 XRST 31 DVCC 51 REV 71 RO5 91 DVCC 111 TSOUT2

12 IMOD 32 GI5 52 MUX2 72 RO4 92 VCK 112 FB

13 VSYNC 33 GI4 53 MUX1 73 RO3 93 XVCK 113 CAP

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14 HSYNC 34 GI3 54 MUX0 74 RO2 94 VST 114 AVCC

15 DE 35 GI2 55 LD2 75 RO1 95 D2U 115 AGND

16 TSIN2 36 GI1 56 LD1 76 RO0 96 U2D 116 PVGH

17 TSIN3 37 GI0 57 BO5 77 DGND 97 VGL 117 NC

18 CLK 38 RI7 58 BO4 78 DVCC 98 VGH 118 DVCC

19 DGND 39 RI6 59 BO3 79 SHL 99 CVGH 119 DRV

20 BI7 40 RI5 60 DGND 80 DCLK 100 CN 120 DGND

AUO-036 Pinout

Recommended register setting

Register DataRegister DataRegister DataRegister Data NoteNoteNoteNote

Reg NO.Reg NO.Reg NO.Reg NO. Reg NameReg NameReg NameReg Name D7D7D7D7 D6D6D6D6 D5D5D5D5 D4D4D4D4 D3D3D3D3 D2D2D2D2 D1D1D1D1 D0D0D0D0

0000 VDD_ADJ X X X 0 1 1 1 1 VDD=11v

1111 VEE_ADJ X X X X 0 1 0 0 (Default)

2222 COMDC 1 0 0 0 0 0 0 0 (Default)

3333 VPOSITION 0 0 1 0 0 0 0 0 (Default)

4444 HPOSITION 1 0 1 0 0 0 0 0

5555 PANEL X 1 1 0 0 0 0 1

6666 FUNCTION X X X 1 1 1 0 1

128128128128 BLANK(1) 0 1 1 1 0 0 0 0 (Default)

129129129129 PREC(1) 0 0 0 0 1 0 0 0 (Default)

130130130130 SWITCH(1) 0 0 0 1 1 1 1 1 (Default)

131131131131 INT(1) 0 0 0 1 1 0 0 0 (Default)

132132132132 BLANK(2) 1 0 0 0 0 1 0 0 (Default)

133133133133 PREC(2) 0 0 0 0 1 1 0 0 (Default)

134134134134 SWITCH(2) 0 0 1 0 0 1 0 1 (Default)

135135135135 INT(2) 0 0 0 1 1 1 0 0 (Default)

136136136136 BLANK(3) 1 0 0 1 0 1 1 0 (Default)

137137137137 PREC(3) 0 0 0 1 1 0 0 1 (Default)

138138138138 SWITCH(3) 0 0 1 0 1 0 0 0 (Default)

139139139139 INT(3) 0 0 0 1 1 1 1 0 (Default)

Important Note

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1. In customer system, the initial state of the pixel clock output (DCLK pin of AUO-036) must

be set to Low.

2. Please do not cut off the pixel clock during system operation.

auo 036 ic data

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