atsamha1gxxa data sheet - microchip...

ATSAMHAXGXXA Low-Power Automotive SiP Product with 32-bit ARM®

Cortex® M0+ Processor and LIN SBC

Introduction

The SAMHA0/1 is a low-power automotive system-in-package (SiP) product series using the 32-bit ARM®

Cortex® M0+ processor featuring 48 pins with up to 64KB of Flash, up to 2KB of read-while-write dataflash, and up to 8KB of SRAM. The SAM HA1 devices operate at a maximum frequency of 48MHz andreach 2.46 Coremark/MHz. They also include a LIN system basis chip (SBC) with a fully integrated LINtransceiver designed in compliance with the LIN specifications 2.0, 2.1, 2.2, 2.2A and SAEJ2602-2, and a3.3V/85mA voltage regulator.

Features

Microcontroller

• Processor– ARM Cortex-M0+ CPU running at up to 48MHz

• Single-cycle hardware multiplier• Micro Trace Buffer (MTB)

• Memories– 16/32/64KB in-system self-programmable Flash– 0.5/1/2KB Read-While-Write (RWW) Flash section– 4/4/8KB SRAM memory

• System– Power-on Reset (POR) and brown-out detection (BOD)– Internal and external clock options with 48MHz Digital Frequency Locked Loop (DFLL48M)

and 48MHz to 96MHz Fractional Digital Phase Locked Loop (FDPLL96M)– External Interrupt Controller (EIC)– Up to 14 external interrupts– One non-maskable interrupt– Two-Pin Serial Wire Debug (SWD) programming, test and debugging interface

• Low Power– Idle and Standby sleep modes– SleepWalking peripherals

• Peripherals– 8-Channel Direct Memory Access Controller (DMAC)– 12-Channel Event System– Up to five 16-bit Timer/Counters (TC), configurable as either:

© 2017 Microchip Technology Inc. Datasheet DS20005841A-page 1

• One 16-bit TC with compare/capture channels• One 8-bit TC with compare/capture channels• One 32-bit TC with compare/capture channels, by using two TCs• Among other uses, the additional TC can be used for internal scheduling and has no

compare outputs connected.– Three 16-bit Timer/Counters for Control (TCC), with extended functions:

• Up to four compare channels with optional complementary output• Generation of synchronized pulse width modulation (PWM) pattern across port pins• Deterministic fault protection, fast decay and configurable dead-time between

complementary output– Dithering for enhancing resolution with up to 5 bit and reduce quantization error– 32-bit Real Time Counter (RTC) with clock/calendar function– Watchdog Timer (WDT)– CRC-32 generator– Up to five Serial Communication Interfaces (SERCOM), each configurable to operate as either:

• USART with full-duplex and single-wire half-duplex configuration• I2C up to 3.4MHz (only available on specific SERCOMs, see I/O Multiplexing and

Considerations chapter for details)• SPI

– One 12-bit, 350ksps Analog-to-Digital Converter (ADC) with 13 channels• Differential and single-ended input• 1/2x to 16x programmable gain stage• Automatic offset and gain error compensation• Oversampling and decimation in hardware to support 13-, 14-, 15- or 16-bit resolution

– 10-bit, 350ksps Digital-to-Analog Converter (DAC)– One Analog Comparator (AC) with window compare function– Peripheral Touch Controller (PTC)

Note: The PTC is not available on SAMHA0 devices

• Up to 90-Channel capacitive touch and proximity sensing• I/O

– Up to 32 programmable I/O pins• Packages

– 48-pin VQFN

LIN SBC(1)

• Up to 40V Supply Voltage• Operating Voltage VS=5V to 28V• Supply Current

– Typically 9μA supply current during Sleep mode– Typically 47μA supply current in Silent mode– Very low current consumption at low supply voltages (2V < VS < 5.5V): typically 130μA

• Linear Low-Drop Voltage Regulator, 85mA Current Capability– MLC(2) capacitor with 0Ω ESR– Normal, Fail-safe and Silent modes– VCC=3.3V±2%

ATSAMHAXGXXA


– Sleep mode: VCC is switched off• VCC undervoltage detection with open drain reset output (NRES, 4ms reset time)• Voltage Regulator is Short-Circuit and Overtemperature Protected• LIN Physical Layer in Compliance with LIN 2.0, 2.1, 2.2, 2.2A and SAEJ2602-2• Wake-Up Capability Via LIN Bus (100μs dominant)• Wake-Up Source Recognition• TXD Time-Out Timer• Bus pin is Overtemperature and Short-Circuit Protected vs. GND and Battery• Advanced EMC and ESD Performance• Fulfills the OEM “Hardware Requirements for LIN in Automotive Applications Rev.1.3”• Interference and Damage Protection Cccording to ISO7637

Note: 1. LIN SBC: LIN system basis chip including LIN transceiver and voltage regulator2. Multilayer ceramic

ATSAMHAXGXXA


Table of Contents

Introduction......................................................................................................................1

Features.......................................................................................................................... 1

1. Description...............................................................................................................12

2. Configuration Summary...........................................................................................14

3. LIN System Basis Chip (LIN-SBC) Block................................................................ 163.1. Features..................................................................................................................................... 163.2. Description................................................................................................................................. 163.3. Pin Description........................................................................................................................... 173.4. Functional Description................................................................................................................19

4. Block Diagram......................................................................................................... 26

5. Pinout...................................................................................................................... 285.1. SAM HA-G - VQFN48................................................................................................................ 28

6. Signal Descriptions List........................................................................................... 29

7. I/O Multiplexing and Considerations........................................................................317.1. Multiplexed Signals.................................................................................................................... 317.2. Other Functions..........................................................................................................................32

8. Power Supply and Start-Up Considerations............................................................ 348.1. Power Domain Overview............................................................................................................348.2. Power Supply Considerations.................................................................................................... 348.3. Power-Up................................................................................................................................... 368.4. Power-On Reset and Brown-Out Detector.................................................................................36

9. Product Mapping..................................................................................................... 38

10. Automotive Quality Grade....................................................................................... 39

11. Data Retention.........................................................................................................40

12. Memories.................................................................................................................4112.1. Embedded Memories................................................................................................................. 4112.2. Physical Memory Map................................................................................................................4112.3. NVM Calibration and Auxiliary Space........................................................................................ 42

13. Processor And Architecture.....................................................................................4513.1. Cortex M0+ Processor............................................................................................................... 4513.2. Nested Vector Interrupt Controller..............................................................................................4613.3. Micro Trace Buffer......................................................................................................................48

ATSAMHAXGXXA


13.4. High-Speed Bus System............................................................................................................ 4913.5. AHB-APB Bridge........................................................................................................................ 5113.6. PAC - Peripheral Access Controller........................................................................................... 52

14. Peripherals Configuration Summary........................................................................66

15. DSU - Device Service Unit...................................................................................... 6815.1. Overview.................................................................................................................................... 6815.2. Features..................................................................................................................................... 6815.3. Block Diagram............................................................................................................................6915.4. Signal Description...................................................................................................................... 6915.5. Product Dependencies...............................................................................................................6915.6. Debug Operation........................................................................................................................7015.7. Chip Erase..................................................................................................................................7215.8. Programming..............................................................................................................................7315.9. Intellectual Property Protection.................................................................................................. 7315.10. Device Identification...................................................................................................................7515.11. Functional Description................................................................................................................7615.12. Register Summary..................................................................................................................... 8115.13. Register Description...................................................................................................................83

16. Clock System.........................................................................................................10716.1. Clock Distribution..................................................................................................................... 10716.2. Synchronous and Asynchronous Clocks..................................................................................10816.3. Register Synchronization......................................................................................................... 10816.4. Enabling a Peripheral............................................................................................................... 11316.5. Disabling a Peripheral.............................................................................................................. 11316.6. On-demand, Clock Requests................................................................................................... 11316.7. Power Consumption vs. Speed................................................................................................ 11416.8. Clocks after Reset.................................................................................................................... 114

17. GCLK - Generic Clock Controller...........................................................................11517.1. Overview...................................................................................................................................11517.2. Features................................................................................................................................... 11517.3. Block Diagram.......................................................................................................................... 11517.4. Signal Description.....................................................................................................................11617.5. Product Dependencies............................................................................................................. 11617.6. Functional Description.............................................................................................................. 11717.7. Register Summary....................................................................................................................12217.8. Register Description.................................................................................................................123

18. PM – Power Manager............................................................................................13718.1. Overview.................................................................................................................................. 13718.2. Features................................................................................................................................... 13718.3. Block Diagram..........................................................................................................................13818.4. Signal Description.................................................................................................................... 13818.5. Product Dependencies.............................................................................................................13818.6. Functional Description..............................................................................................................140

ATSAMHAXGXXA


18.7. Register Summary....................................................................................................................14818.8. Register Description.................................................................................................................148

19. SYSCTRL – System Controller............................................................................. 16919.1. Overview.................................................................................................................................. 16919.2. Features................................................................................................................................... 16919.3. Block Diagram..........................................................................................................................17119.4. Signal Description.................................................................................................................... 17119.5. Product Dependencies.............................................................................................................17119.6. Functional Description..............................................................................................................17319.7. Register Summary....................................................................................................................18919.8. Register Description.................................................................................................................191

20. WDT – Watchdog Timer........................................................................................ 23420.1. Overview.................................................................................................................................. 23420.2. Features................................................................................................................................... 23420.3. Block Diagram..........................................................................................................................23520.4. Signal Description.................................................................................................................... 23520.5. Product Dependencies.............................................................................................................23520.6. Functional Description..............................................................................................................23620.7. Register Summary....................................................................................................................24120.8. Register Description.................................................................................................................241

21. RTC – Real-Time Counter.....................................................................................25321.1. Overview.................................................................................................................................. 25321.2. Features................................................................................................................................... 25321.3. Block Diagram..........................................................................................................................25421.4. Signal Description.................................................................................................................... 25421.5. Product Dependencies.............................................................................................................25421.6. Functional Description..............................................................................................................25621.7. Register Summary....................................................................................................................26221.8. Register Description.................................................................................................................264

22. DMAC – Direct Memory Access Controller........................................................... 29722.1. Overview.................................................................................................................................. 29722.2. Features................................................................................................................................... 29722.3. Block Diagram..........................................................................................................................29922.4. Signal Description.................................................................................................................... 29922.5. Product Dependencies.............................................................................................................29922.6. Functional Description..............................................................................................................30022.7. Register Summary....................................................................................................................32122.8. Register Description.................................................................................................................32222.9. Register Summary - SRAM......................................................................................................35322.10. Register Description - SRAM................................................................................................... 353

23. EIC – External Interrupt Controller........................................................................ 36123.1. Overview.................................................................................................................................. 36123.2. Features................................................................................................................................... 361

ATSAMHAXGXXA


23.3. Block Diagram..........................................................................................................................36123.4. Signal Description.................................................................................................................... 36223.5. Product Dependencies.............................................................................................................36223.6. Functional Description..............................................................................................................36323.7. Register Summary....................................................................................................................36723.8. Register Description.................................................................................................................368

24. NVMCTRL – Nonvolatile Memory Controller.........................................................37924.1. Overview.................................................................................................................................. 37924.2. Features................................................................................................................................... 37924.3. Block Diagram..........................................................................................................................37924.4. Signal Description.................................................................................................................... 38024.5. Product Dependencies.............................................................................................................38024.6. Functional Description..............................................................................................................38124.7. Register Summary....................................................................................................................38824.8. Register Description.................................................................................................................388

25. PORT - I/O Pin Controller......................................................................................40225.1. Overview.................................................................................................................................. 40225.2. Features................................................................................................................................... 40225.3. Block Diagram..........................................................................................................................40325.4. Signal Description.................................................................................................................... 40325.5. Product Dependencies.............................................................................................................40325.6. Functional Description..............................................................................................................40625.7. Register Summary....................................................................................................................41225.8. PORT Pin Groups and Register Repetition..............................................................................41425.9. Register Description.................................................................................................................414

26. EVSYS – Event System........................................................................................ 43526.1. Overview.................................................................................................................................. 43526.2. Features................................................................................................................................... 43526.3. Block Diagram..........................................................................................................................43526.4. Signal Description.................................................................................................................... 43626.5. Product Dependencies.............................................................................................................43626.6. Functional Description..............................................................................................................43726.7. Register Summary....................................................................................................................44226.8. Register Description.................................................................................................................443

27. SERCOM – Serial Communication Interface.........................................................45627.1. Overview.................................................................................................................................. 45627.2. Features................................................................................................................................... 45627.3. Block Diagram..........................................................................................................................45727.4. Signal Description.................................................................................................................... 45727.5. Product Dependencies.............................................................................................................45727.6. Functional Description..............................................................................................................459

28. SERCOM USART..................................................................................................46528.1. Overview.................................................................................................................................. 465

ATSAMHAXGXXA


28.2. USART Features...................................................................................................................... 46528.3. Block Diagram..........................................................................................................................46628.4. Signal Description.................................................................................................................... 46628.5. Product Dependencies.............................................................................................................46628.6. Functional Description..............................................................................................................46828.7. Register Summary....................................................................................................................48028.8. Register Description.................................................................................................................481

29. SERCOM SPI – SERCOM Serial Peripheral Interface..........................................50429.1. Overview.................................................................................................................................. 50429.2. Features................................................................................................................................... 50429.3. Block Diagram..........................................................................................................................50529.4. Signal Description.................................................................................................................... 50529.5. Product Dependencies.............................................................................................................50529.6. Functional Description..............................................................................................................50729.7. Register Summary....................................................................................................................51629.8. Register Description.................................................................................................................517

30. SERCOM I2C – Inter-Integrated Circuit.................................................................53730.1. Overview.................................................................................................................................. 53730.2. Features................................................................................................................................... 53730.3. Block Diagram..........................................................................................................................53830.4. Signal Description.................................................................................................................... 53830.5. Product Dependencies.............................................................................................................53830.6. Functional Description..............................................................................................................54030.7. Register Summary - I2C Slave.................................................................................................55930.8. Register Description - I2C Slave...............................................................................................55930.9. Register Summary - I2C Master...............................................................................................57730.10. Register Description - I2C Master............................................................................................ 578

31. TC – Timer/Counter...............................................................................................59931.1. Overview.................................................................................................................................. 59931.2. Features................................................................................................................................... 59931.3. Block Diagram..........................................................................................................................60031.4. Signal Description.................................................................................................................... 60031.5. Product Dependencies.............................................................................................................60131.6. Functional Description..............................................................................................................60231.7. Register Summary....................................................................................................................61431.8. Register Description.................................................................................................................617

32. TCC – Timer/Counter for Control Applications...................................................... 64132.1. Overview.................................................................................................................................. 64132.2. Features................................................................................................................................... 64132.3. Block Diagram..........................................................................................................................64232.4. Signal Description.................................................................................................................... 64332.5. Product Dependencies.............................................................................................................64332.6. Functional Description..............................................................................................................64532.7. Register Summary....................................................................................................................677

ATSAMHAXGXXA


32.8. Register Description.................................................................................................................679

33. ADC – Analog-to-Digital Converter........................................................................72533.1. Overview.................................................................................................................................. 72533.2. Features................................................................................................................................... 72533.3. Block Diagram..........................................................................................................................72633.4. Signal Description.................................................................................................................... 72633.5. Product Dependencies.............................................................................................................72733.6. Functional Description..............................................................................................................72833.7. Register Summary....................................................................................................................73733.8. Register Description.................................................................................................................738

34. AC – Analog Comparators.....................................................................................76334.1. Overview.................................................................................................................................. 76334.2. Features................................................................................................................................... 76334.3. Block Diagram..........................................................................................................................76434.4. Signal Description.................................................................................................................... 76434.5. Product Dependencies.............................................................................................................76434.6. Functional Description..............................................................................................................76634.7. Register Summary....................................................................................................................77634.8. Register Description.................................................................................................................776

35. DAC – Digital-to-Analog Converter........................................................................79335.1. Overview.................................................................................................................................. 79335.2. Features................................................................................................................................... 79335.3. Block Diagram..........................................................................................................................79335.4. Signal Description.................................................................................................................... 79335.5. Product Dependencies.............................................................................................................79335.6. Functional Description..............................................................................................................79535.7. Register Summary....................................................................................................................79935.8. Register Description.................................................................................................................799

36. PTC - Peripheral Touch Controller.........................................................................81036.1. Overview.................................................................................................................................. 81036.2. Features................................................................................................................................... 81036.3. Block Diagram.......................................................................................................................... 81136.4. Signal Description.................................................................................................................... 81236.5. System Dependencies............................................................................................................. 81236.6. Functional Description..............................................................................................................813

37. Electrical Characteristics....................................................................................... 81537.1. Disclaimer.................................................................................................................................81537.2. Absolute Maximum Ratings......................................................................................................81537.3. LIN System Basis Chip (LIN-SBC) Block................................................................................. 81737.4. General Operating Ratings.......................................................................................................82337.5. Thermal Considerations........................................................................................................... 82437.6. Supply Characteristics..............................................................................................................82537.7. Maximum Clock Frequencies...................................................................................................825

ATSAMHAXGXXA


37.8. Power Consumption.................................................................................................................82737.9. Peripheral Power Consumption................................................................................................82937.10. HA1_I/O Pin Characteristics.................................................................................................... 83137.11. Analog Characteristics............................................................................................................. 83537.12. NVM Characteristics................................................................................................................ 84437.13. Oscillators Characteristics........................................................................................................84437.14. PTC Typical Characteristics.....................................................................................................85337.15. Timing Characteristics..............................................................................................................855

38. Schematic Checklist.............................................................................................. 86038.1. Introduction...............................................................................................................................86038.2. Power Supply........................................................................................................................... 86038.3. External Analog Reference Connections................................................................................. 86138.4. External Reset Circuit...............................................................................................................86238.5. Clocks and Crystal Oscillators..................................................................................................86338.6. Unused or Unconnected Pins...................................................................................................86738.7. Programming and Debug Ports................................................................................................867

39. Typical Application Diagram.................................................................................. 871

40. Errata.....................................................................................................................87240.1. Die Revision F..........................................................................................................................872

41. Conventions...........................................................................................................87541.1. Numerical Notation...................................................................................................................87541.2. Memory Size and Type.............................................................................................................87541.3. Frequency and Time.................................................................................................................87541.4. Registers and Bits.................................................................................................................... 876

42. Acronyms and Abbreviations.................................................................................877

43. Datasheet Revision History................................................................................... 88043.1. Revision A - 12/2017................................................................................................................880

44. Packaging Information...........................................................................................88244.1. Package Marking Information...................................................................................................882

The Microchip Web Site.............................................................................................. 886

Customer Change Notification Service........................................................................886

Customer Support....................................................................................................... 886

Product Identification System......................................................................................887

Microchip Devices Code Protection Feature............................................................... 888

Legal Notice.................................................................................................................888

ATSAMHAXGXXA


Trademarks................................................................................................................. 889

Quality Management System Certified by DNV...........................................................889

Worldwide Sales and Service......................................................................................890

ATSAMHAXGXXA


1. DescriptionThe SAMHA0/1 is a low-power automotive system-in-package (SiP) product series using the 32-bit ARM®

Cortex® M0+ processor featuring 48 pins with up to 64KB of Flash, up to 2KB of read-while-write dataflash, and up to 8KB of SRAM. The SAMHA0/1 device operates at a maximum frequency of 48MHz andreach 2.46 Coremark/MHz. They also include a LIN system basis chip (SBC) with a fully integrated LINtransceiver designed in compliance with the LIN specifications 2.0, 2.1, 2.2, 2.2A and SAEJ2602-2, and a3.3V/85mA voltage regulator.

Combining a microcontroller, a LIN transceiver, and a voltage regulator makes it possible to developsimple but powerful slave nodes in LIN bus systems. Sleep mode and silent mode guarantee minimizedcurrent consumption even in the event of a floating or a short-circuited LIN bus.

The series is qualified in compliance with AEC Q-100 (–40 to +105°C Tcase).

All devices in the product series include intelligent and flexible peripherals, the Event System forinterperipheral signaling, and support for capacitive touch button, slider and wheel user interfaces.

The SAMHA0/1 provides the following features: In-system programmable Flash, 8-channel direct memoryaccess (DMA) controller, 12-channel Event System, programmable interrupt controller, 32 programmableI/O pins, 32-bit real-time clock and calendar, up to five 16-bit Timer/Counters (TC) and three 24-bit Timer/Counters for Control (TCC), where each TC can be configured to perform frequency and waveformgeneration, accurate program execution timing or input capture with time and frequency measurement ofdigital signals. The TCs can operate in 8- or 16-bit mode, selected TCs can be cascaded to form a 32-bitTC, and three timer/counters have extended functions optimized for motor, lighting and other controlapplications.

The series provides up to five Serial Communication Modules (SERCOM) that each can be configured toact as an USART, UART, SPI, I2C up to 3.4MHz, and LIN slave; up to 13-channel 12-bit ADC withprogrammable gain and optional oversampling and decimation supporting up to 16-bit resolution, one 10-bit 350ksps DAC, two analog comparators with window mode, Peripheral Touch Controller supportingbuttons, sliders, wheels and proximity sensing; programmable Watchdog Timer, brown-out detector andpower-on reset and two-pin Serial Wire Debug (SWD) program and debug interface.

All devices have accurate and low-power external and internal oscillators. All oscillators can be used as asource for the system clock. Different clock domains can be independently configured to run at differentfrequencies, enabling power saving by running each peripheral at its optimal clock frequency, and thusmaintaining a high CPU frequency while reducing power consumption.

The SAMHA0/1 devices offer different Sleep modes according to the needs of the application. The LINSBC offers Sleep and Silent mode and can shut down the voltage regulator to achieve very low powerconsumption. The microcontroller has two software-selectable sleep modes, Idle and Standby. In Idlemode the CPU is stopped while all other functions can be kept running. In Standby, all clocks andfunctions are stopped except those selected to continue running. The device supports SleepWalking.SleepWalking allows peripherals to wake up from sleep based on predefined conditions, allowing theCPU to wake up only when needed, e.g., when a threshold is crossed or a result is ready. The PeripheralEvent System supports synchronous and asynchronous events, allowing peripherals to receive, respondto and send events even in Standby mode.

The Flash program memory can be reprogrammed in-system through the SWD interface. The sameinterface can be used for nonintrusive on-chip debug of application code. A boot loader running in thedevice can use any communication interface to download and upgrade the application program in theFlash memory.

ATSAMHAXGXXADescription


The SAMHA0/1 microcontrollers are supported with a full suite of program and system developmenttools, including C compilers, macro assemblers, program debugger/simulators, programmers andevaluation kits.

ATSAMHAXGXXADescription


2. Configuration SummarySAMHA0/1

Pins 48

General Purpose I/O-pins (GPIOs) 32

Flash 64/32/16KB

Data Flash (read-while-write) 2KB/1KB/512B

SRAM 8/4/4KB

Timer Counter (TC) instances 4+1

Waveform output channels per TC instance 2/0

Timer Counter for Control (TCC) instances 3

Waveform output channels per TCC 8/4/2

DMA channels 8

Serial Communication Interface (SERCOM) instances 5

Analog-to-Digital Converter (ADC) channels 13

Analog Comparators (AC) 1

Digital-to-Analog Converter (DAC) channels 1

Real-Time Counter (RTC) Yes

RTC alarms 1

RTC compare values One 32-bit value or

two 16-bit values

External Interrupt lines 14

Peripheral Touch Controller (PTC) X and Y linesNote: Is not available on SAMHA0 devices

10x9

Maximum CPU frequency 48MHz

Packages QFN

Oscillators 32.768kHz crystal oscillator (XOSC32K)

0.4-32MHz crystal oscillator (XOSC)

32.768kHz internal oscillator (OSC32K)

8MHz high-accuracy internal oscillator (OSC8M)

48MHz Digital Frequency Locked Loop (DFLL48M)

96MHz Fractional Digital Phased Locked Loop(FDPLL96M)

ATSAMHAXGXXAConfiguration Summary


SAMHA0/1

Event System channels 12

SW Debug Interface Yes

Watchdog Timer (WDT) Yes

ATSAMHAXGXXAConfiguration Summary


3. LIN System Basis Chip (LIN-SBC) Block

3.1 Features• Supply voltage up to 40V• Operating voltage VS = 5V to 28V• Supply current

– Sleep mode: typically 9μA– Silent mode: typically 47μA– Very low current consumption at low supply voltages (2V < VS < 5.5V):

typically 130μA• Linear low-drop voltage regulator, 85mA current capability:

– MLC (multi-layer ceramic) capacitor with 0Ω ESR– Normal, fail-safe, and silent mode

• ATA663231: VCC = 3.3V ±2%– Sleep mode: VCC is switched off

• VCC undervoltage detection with open drain reset output (NRES, 4ms reset time)• Voltage regulator is short-circuit and over-temperature protected• LIN physical layer according to LIN 2.0, 2.1, 2.2, 2.2A and SAEJ2602-2• Wake-up capability via LIN bus (100μs dominant)• TXD time-out timer• Bus pin is over-temperature and short-circuit protected versus GND and battery• Advanced EMC and ESD performance• Fulfills the OEM “Hardware Requirements for LIN in Automotive Applications Rev.1.3”• Interference and damage protection according to ISO7637• Qualified according to AEC-Q100

Note: LIN SBC: LIN system basis chip including LIN transceiver and voltage regulator.

3.2 DescriptionThe system basis chip is a fully integrated LIN transceiver, designed according to the LIN specification2.0, 2.1, 2.2, 2.2A and SAEJ2602-2, with a low-drop voltage regulator (3.3V/85mA). The combination ofvoltage regulator and bus transceiver makes it possible to develop simple but powerful slave nodes in LINbus systems. It is designed to handle the low-speed data communication in vehicles (for example, inconvenience electronics). Improved slope control at the LIN driver ensures secure data communicationup to 20Kbaud. The bus output is designed to withstand high voltage. Sleep mode and silent modeguarantee minimized current consumption even in the case of a floating or a short-circuited LIN bus.

ATSAMHAXGXXALIN System Basis Chip (LIN-SBC) Block


Figure 3-1. Block Diagram LIN Transceiver with Integrated Voltage Regulator (SBC)

GND

EN

TXD

RXD

VCC

NRES

Short-circuit andovertemperatureprotection

Voltage regulator

Normal/Silent/Fail-safe Mode

3.3V

Controlunit

Normal andFail-safe

Mode

RF-filterLIN

VS

TXDTime-out

timer

Slew rate control

Undervoltage reset

SleepmodeVCC

switchedoff

Wake-up bus timer

ATA663231

Receiver

VCC

-

+

VCC

VCC

3.3 Pin Description

3.3.1 Supply Pin (VS)LIN operating voltage is VS = 5V to 28V. Undervoltage detection is implemented to disable transmission ifVS falls below typ. 4.5V, thereby avoiding false bus messages. After switching on VS, the IC starts in fail-safe mode and the voltage regulator is switched on.

The supply current in sleep mode is typically 9μA and 47μA in silent mode.

3.3.2 Ground Pin (GND)The IC does not affect the LIN bus in the event of GND disconnection. It is able to handle a ground shiftof up to 11.5% of VS.

3.3.3 Voltage Regulator Output Pin (VCC)The internal 3.3V voltage regulator is capable of driving loads up to 85mA, supplying the microcontrollerand other ICs on the PCB and is protected against overload by means of current limitation andovertemperature shutdown. Furthermore, the output voltage is monitored and causes a reset signal at theNRES output pin if it drops below a defined threshold VVCC_th_uv_down.

3.3.4 Undervoltage Reset Output (NRES)If the VCC voltage falls below the undervoltage detection threshold VCC_th_uv_down, NRES switches to lowafter tres_f. The NRES stays low even if VCC = 0V because NRES is internally driven from the VS voltage.If VS voltage ramps down, NRES stays low until VS < 1.5V and then becomes highly impedant.

The implemented undervoltage delay keeps NRES low for tReset = 4ms after VCC reaches its nominalvalue.



3.3.5 Bus Pin (LIN)A low-side driver with internal current limitation and thermal shutdown as well as an internal pull-upresistor according to LIN specification 2.x is implemented. The voltage range is from –27V to +40V. Thispin exhibits no reverse current from the LIN bus to VS, even in the event of a GND shift or VBatdisconnection. The LIN receiver thresholds comply with the LIN protocol specification.

The fall time (from recessive to dominant) and the rise time (from dominant to recessive) are slope-controlled.

During a short circuit at LIN to VBat, the output limits the output current to IBUS_LIM. Due to the powerdissipation, the chip temperature exceeds TLINoff and the LIN output is switched off. The chip cools downand after a hysteresis of Thys, switches the output on again. RXD stays on high because LIN is high. TheVCC regulator works independently during LIN overtemperature switch-off.

During a short circuit from LIN to GND the IC can be switched into sleep or silent mode and even in thiscase the current consumption is lower than 100μA in sleep mode and lower than 120μA in silent mode. Ifthe short-circuit disappears, the IC starts with a remote wake-up.

The reverse current is < 2μA at pin LIN during loss of VBat. This is optimal behavior for bus systemswhere some slave nodes are supplied from battery or ignition.

3.3.6 Input/Output (TXD)In normal mode the TXD pin is the microcontroller interface for controlling the state of the LIN output.TXD must be pulled to ground in order to drive the LIN bus low. If TXD is high or unconnected (internalpull-up resistor), the LIN output transistor is turned off and the bus is in the recessive state. If the TXD pinstays at GND level while switching into normal mode, it must be pulled to high level longer than 10μsbefore the LIN driver can be activated. This feature prevents the bus line from being accidentally driven todominant state after normal mode has been activated (also in case of a short circuit at TXD to GND).During fail-safe mode, this pin is used as output and signals the fail-safe source.

The TXD input has an internal pull-up resistor.

An internal timer prevents the bus line from being driven permanently in the dominant state. If TXD isforced to low longer than tdom > 20ms, the LIN bus driver is switched to the recessive state. Nevertheless,when switching to sleep mode, the actual level at the TXD pin is relevant.

To reactivate the LIN bus driver, switch TXD to high (> 10μs).

3.3.7 Output Pin (RXD)In normal mode this pin reports the state of the LIN bus to the microcontroller. LIN high (recessive state)is indicated by a high level at RXD; LIN low (dominant state) is indicated by a low level at RXD.

The output is a push-pull stage switching between VCC and GND. The AC characteristics are measuredby an external load capacitor of 20pF.

In silent mode the RXD output switches to high.

3.3.8 Enable Input Pin (EN)The enable input pin controls the operating mode of the device. If EN is high, the circuit is in normalmode, with transmission paths from TXD to LIN and from LIN to RXD both active. The VCC voltageregulator operates with 3.3V/85mA output capability.

If EN is switched to low while TXD is still high, the device is forced to silent mode. No data transmission isthen possible, and current consumption is reduced to IVSsilent typ. 47μA. The VCC regulator retains its fullfunctionality.



If EN is switched to low while TXD is low, the device is forced to sleep mode. No data transmission ispossible, and the voltage regulator is switched off.

The EN pin provides a pull-down resistor to force the transceiver into recessive mode if EN isdisconnected.

3.4 Functional Description

3.4.1 Physical Layer CompatibilityBecause the LIN physical layer is independent of higher LIN layers (e.g., LIN protocol layer), all nodeswith a LIN physical layer according to revision 2.x can be mixed with LIN physical layer nodes based onearlier versions (i.e., LIN 1.0, LIN 1.1, LIN 1.2, LIN 1.3) without any restrictions.

3.4.2 Operating ModesFigure 3-2. SBC Operating Modes

a: VS > VVS_th_U_F_up (2.4V)b: VS < VVS_th_U_down (1.9V)c: Bus wake-up event (LIN)

e: VS < VVS_th_N_F_down (3.9V)f: VS > VVS_th_F_N_up (4.9V)

d: VCC < VVCC_th_uv_down (2.4V/4.2V)

EN = 1

EN = 0

Go to sleepcommand

Go to silentcommand

EN = 0TXD = 0

b c & f

EN = 0TXD = 0

EN = 0TXD = 1

EN = 1& f

TXD = 1

d, e b

a

b

& f

Fail-safe Mode

Normal ModeSleep Mode

Unpowered Mode

All circuitry OFF

Silent Mode

c & f, d

EN = 1& f

& f & d& f

VCC: ON 3.3VVCC monitor activeCommunication: OFFWake-up SignallingUndervoltage Signalling

VCC: 3.3VVCC monitor activeCommunication: ON

VCC: OFFCommunication: OFF

VCC: 3.3VVCC monitor activeCommunication: OFF

Table 3-1. SBC Operating Modes

Operating Mode Transceiver VCC LIN TXD RXD

Fail-safe OFF 3.3V RecessiveSignaling fail-safe sources (see Table Signaling in Fail-

safe Mode)

Normal ON 3.3V TXD-dependent Follows data transmission

Silent OFF 3.3V Recessive High High

Sleep/Unpowered OFF 0V Recessive Low Low



Related LinksFail-Safe Mode

3.4.2.1 Normal ModeThis is the normal transmitting and receiving mode of the LIN Interface, in accordance with LINspecification 2.x.

The VCC voltage regulator operates with 3.3V output voltage, with a low tolerance of ±2% and amaximum output current of 85mA. If an undervoltage condition occurs, NRES is switched to low and theIC changes its state to fail-safe mode.

3.4.2.2 Silent ModeA falling edge at EN while TXD is high switches the IC into silent mode. The TXD signal has to be logichigh during the mode select window. The transmission path is disabled in silent mode. The voltageregulator is active. The overall supply current from VBat is a combination of the IVSsilent = 47μA plus theVCC regulator output current IVCC.

Figure 3-3. Switching to Silent Mode

Delay time silent modetd_silent = maximum 20µs

Mode select window

LIN switches directly to recessive mode

td = 3.2µs

LIN

VCC

NRES

TXD

EN

Normal Mode Silent Mode

In silent mode the internal slave termination between the LIN pin and VS pin is disabled to minimize thecurrent consumption in case the pin LIN is short-circuited to GND. Only a weak pull-up current (typically10μA) between the LIN pin and VS pin is present. Silent mode can be activated independently from thecurrent level on pin LIN.

If an undervoltage condition occurs, NRES is switched to low and the SBC changes its state to fail-safemode.

3.4.2.3 Sleep ModeA falling edge at EN while TXD is low switches the IC into sleep mode. The TXD signal has to be logiclow during the mode select window (see the following figure).



Figure 3-4. Switching to Sleep Mode

Delay time sleep modetd_sleep = maximum 20µs

LIN switches directly to recessive mode

td = 3.2µs

LIN

VCC

NRES

TXD

EN

Sleep ModeNormal Mode

Mode select window

In order to avoid any influence to the LIN pin when switching into sleep mode it is possible to switch theEN up to 3.2μs earlier to low than the TXD. The easiest and best way to do this is by having two fallingedges at TXD and EN at the same time.

In sleep mode the transmission path is disabled. Supply current from VBat is typically IVSsleep = 9μA. TheVCC regulator is switched off; NRES and RXD are low. The internal slave termination between the LIN pinand VS pin is disabled to minimize the current consumption in case the LIN pin is short-circuited to GND.Only a weak pull-up current (typically 10μA) between the LIN pin and the VS pin is present. The sleepmode can be activated independently from the current level on the LIN pin. Voltage below the LIN pre-wake detection VLINL at the LIN pin activates the internal LIN receiver and starts the wake-up detectiontimer.

If the TXD pin is short-circuited to GND, it is possible to switch to sleep mode via EN after t > tdom.

3.4.2.4 Fail-Safe ModeThe device automatically switches to fail-safe mode at system power-up. The voltage regulator isswitched on. The NRES output remains low for tres = 4ms and causes the microcontroller to be reset. LINcommunication is switched off. The IC stays in this mode until EN is switched to high. The IC thenchanges to normal mode. A low at NRES switches the IC into fail-safe mode directly. During fail-safemode the TXD pin is an output and, together with the RXD output pin, signals the fail-safe source.

If the device enters fail-safe mode coming from the normal mode (EN=1) due to an VS undervoltagecondition (VS < VVS_th_N_F_down), it is possible to switch into sleep or silent mode by a falling edge at the EN input.With this feature the current consumption can be further reduced.

A wake-up event from either silent or sleep mode is signalled to the microcontroller using the RXD pinand the TXD pin. A VS undervoltage condition is also signalled at these two pins. The coding is shown inthe table below.

A wake-up event switches the IC to fail-safe mode.



Table 3-2. Signaling in Fail-Safe Mode

Fail-Safe Sources TXD RXD

LIN wake-up (LIN pin) Low Low

VSth (battery) undervoltage detection(VS < 3.9V) High Low

3.4.3 Wake-Up Scenarios from Silent Mode or Sleep Mode

3.4.3.1 Remote Wake-up via LIN Bus

Remote Wake-up from Silent ModeA remote wake-up from silent mode is only possible if TXD is high. A voltage less than the LIN pre-wakedetection VLINL at the LIN pin activates the internal LIN receiver and starts the wake-up detection timer.A falling edge at the LIN pin followed by a dominant bus level maintained for a certain period of time(> tbus) and the following rising edge at pin LIN result in a remote wake-up request. The device switchesfrom silent mode to fail-safe mode, the VCC voltage regulator remains activated and the internal LINslave termination resistor is switched on. The remote wake-up request is indicated by a low level at theRXD pin and TXD pin (strong pull-down at TXD). EN high can be used to switch directly to normal mode.

Figure 3-5. LIN Wake-Up from Silent Mode

Undervoltage detection active

Silent mode 3.3V Fail-safe mode 3.3V Normal mode

Low

Fail-safe Mode Normal Mode

EN High

High

NRES

EN

VCC

RXD

LIN bus

Bus wake-up filtering timetbus

HighTXD HighLow (strong pull-down)

Remote Wake-up from Sleep ModeA falling edge at the LIN pin followed by a dominant bus level maintained for a certain period of time (>tbus) and a following rising edge at the LIN pin result in a remote wake-up request, causing the device toswitch from sleep mode to fail-safe mode.

The VCC regulator is activated, and the internal LIN slave termination resistor is switched on. The remotewake-up request is indicated by a low level at RXD and TXD (strong pull-down at TXD) (see Figure 1-6).



EN high can be used to switch directly from sleep/silent mode to fail-safe mode. If EN is still high afterVCC ramp-up and undervoltage reset time, the IC switches to normal mode.

Figure 3-6. LIN Wake-Up from Sleep Mode

tVCC

Off stateOn state

Low

Fail-safe Mode Normal Mode

EN High

Microcontrollerstart-up time delay

Resettime

Low

LowNRES

EN

VCC

RXD

LIN bus

Bus wake-up filtering timetbus

HighTXD Low (strong pull-down)

High

High

3.4.3.2 Wake-Up Source RecognitionThe device can distinguish between different wake-up sources. The wake-up source can be read on theTXD and RXD pin in fail-safe mode. These flags are immediately reset if the microcontroller sets the ENpin to high and the IC is in normal mode.

Table 3-3. Signaling in Fail-safe Mode

Fail-Safe Sources TXD RXD

LIN wake-up (LIN pin) Low Low

VSth (battery) undervoltage detection(VS < 3.9V) High Low

3.4.4 Behavior under Low Supply Voltage ConditionAfter the battery voltage has been connected to the application circuit, the voltage at the VS pin increasesaccording to the block capacitor used in the application . If VVS is higher than the minimum VS operationthreshold VVS_th_U_F_up, the IC mode changes from unpowered mode to fail-safe mode. As soon as VVSexceeds the undervoltage threshold VVS_th_F_N_up, the LIN transceiver can be activated.

The VCC output voltage reaches its nominal value after tVCC. This parameter depends on the externallyapplied VCC capacitor and the load. The NRES output is low for the reset time delay treset. No modechange is possible during this time treset.

The behavior of VCC, NRES and VS is shown in the following diagrams (ramp-up and ramp-down):



Figure 3-7. VCC and NRES versus VS (Ramp-up) for 3.3V

V (V

)

VS (V)

0.00.51.01.52.02.53.03.54.04.55.05.56.06.57.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0

VS

VCC NRES

Figure 3-8. VCC and NRES versus VS (Ramp-down) for 3.3VV

(V)

VS (V)

0.00.51.01.52.02.53.03.54.04.55.05.56.06.57.0

0.00.51.01.52.02.53.03.54.04.55.05.56.06.57.0

VS

VCCNRES

Please note that the upper graphs are only valid if the VS ramp-up and ramp-down times are muchslower than the VCC ramp-up time tVcc and the NRES delay time treset.

If during sleep mode the voltage level of VVS drops below the undervoltage detection thresholdVVS_th_N_F_down (typ. 4.3V), the operation mode is not changed and no wake-up is possible. Only if thesupply voltage on pin VS drops below the VS operation threshold VVS_th_U_down (typ. 2.05V), does the ICswitch to unpowered mode.

If during silent mode the VCC voltage drops below the VCC undervoltage threshold VVCC_th_uv_down the ICswitches into fail-safe mode. If the supply voltage on pin VS drops below the VS operation thresholdVVS_th_U_down (typ. 2.05V), does the IC switch to unpowered mode.

If during normal mode the voltage level on the VS pin drops below the VS undervoltage detectionthreshold VVS_th_N_F_down (typ. 4.3V), the IC switches to fail-safe mode. This means the LIN transceiver isdisabled in order to avoid malfunctions or false bus messages. The voltage regulator remains active.

In this undervoltage situation it is possible to switch the device into sleep mode or silent mode by a fallingedge at the EN input. For this feature, switching into these two current saving modes is alwaysguaranteed, allowing current consumption to be reduced even further. When the VCC voltage dropsbelow the VCC undervoltage threshold VVCC_th_uv_down (typ. 2.6V) the IC switches into fail-safe mode.

The current consumption of the SBC in silent mode or in fail-safe mode and the voltage regulator isalways below 170μA, even when the supply voltage VS is lower than the regulator’s nominal outputvoltage VCC.



3.4.5 Voltage RegulatorFigure 3-9. Voltage Regulator: Supply Voltage Ramp-Up and Ramp-Down

VSV

12V

3.3V2.9V

3.3V

t

VCC

tVCCtReset

2.4V

tres_fNRES

t

VVS_th_N_f_down

The voltage regulator needs an external capacitor for compensation and to smooth the disturbances fromthe microcontroller. It is recommended to use an MLC capacitor with a minimum capacitance of 1.8μFtogether with a 100nF ceramic capacitor. Depending on the application, the values of these capacitorscan be modified by the customer.

During a short circuit at VCC, the output limits the output current to IVCClim. Because of undervoltage,NRES switches to low and sends a reset to the microcontroller. If the chip temperature exceeds the valueTVCCoff, the VCC output switches off. The chip cools down and, after a hysteresis of Thys, switches theoutput on again.

When the IC is being soldered onto the PCB it is mandatory to connect the heat slug with a wide GNDplate on the printed board to get a good heat sink.

The main power dissipation of the IC is created from the VCC output current IVCC, which is needed forthe application. “Power Dissipation: Safe Operating Area: Regulator’s Output Current IVCC versus SupplyVoltage VS” is shown in the figure below.

Figure 3-10. Power Dissipation: Safe Operating Area: Regulator’s Output Current IVCC versusSupply Voltage VS at Different Ambient Temperatures (48-pin version, Rthja = 54K/W assumed)

0.09

0.08

0.07

0.06

0.05

0.04

0.03

0.02

0.01

05 76 8 10 11 12 13 14 15 16 17 189

Max

I VC

C (A

)

VVS (V)

Ta = 65°C

Ta = 75°C

Ta = 85°C



4. Block Diagram

CORTEX-M0+ Processor

Fmax 48MHz

Device Service

Unit

Mem

ory

Trac

e Bu

ffer

POR

T

Even

t Sys

tem

POR

T

64/32/16KB NVM 2KB/1KB/512B

RWW Flash Section

NVM Controller

Serial Wire

Peripheral Access Controller

Peripheral Access Controller Peripheral

Access Controller

High Speed Bus Matrix

System Controller

I/O Bus

Power Manager

DMA Control Unit

Undervoltage Reset

VREG

5 x SERCOM

AHB-APB Bridge B

S

M M M

M EN

NRES

VCC

VS

LIN

S S

S S

AHB-APB Bridge A

AHB-APB Bridge C

Cache

VREF

OSC32K

OSC8M

DFLL48M

FDPLL96M

Clock Controller

Sleep Controller

Generic Clock Controller

Real Time Counter

Watchdog Timer

External Interrupt Controller

Reset Controller

BOD33

XOSC32K

XOSC

XIN32

RXDTXD

PAD0 PAD1 PAD2PAD3

WO0 WO1

WO0 WO1

WOn(2)

AIN[19..0]

VREFA

VREFB

VOUT

VREFP

X[15..0]

Y[15..0]

XOUT32

XIN

XOUT

RESETN

SWCLK

SWDIO

DMA

4+1 x Timer/Counter

DMA

DMA

DMA

3 x Timer/Counter for Control

13-channel 12-bit ADC 350KSPS

2 Analog Comparators

DMA

10-bit DAC

Peripheral Touch

Controller

GCLK_IO[7..0]

EXTINT[15..0]

NMI

8/4/4KB SRAM

SRAM Controller

LIN TRX

AIN[3..0]

1. Some products have different number of SERCOM instances, Timer/Counter instances, PTCsignals and ADC signals. Refer to the Configuration Summary for details.

2. The three TCC instances have different configurations, including the number of Waveform Output(WO) lines. Refer to the TCC Configuration for details.

ATSAMHAXGXXABlock Diagram


Related LinksConfiguration SummaryTCC Configurations

ATSAMHAXGXXABlock Diagram


5. Pinout

5.1 SAM HA-G - VQFN48

PA00 1PA01 2PA02 3PA03 4

GNDANA 5VDDANA 6

PB06 7PB07 8PA04 9PA05 10PA06 11PA07 12

PA08

13

PA09

14

PA10

15

PA11

16

PB10

17

PB11

18

GN

D_L

IN

19LI

N

20VS

21

GN

D

22PA

14

23PA

15

24

PA16 25PA17 26PA18 27PA19 28PB16 29PB17 30PA20 31PA21 32VCC 33GND 34GND 35VDDIO 36

PB22

37

EN

38PA

27

39R

ESET

N

40PA

28

41G

ND

42

VDD

CO

RE

43VD

DIN

44

PA30

45

PA31

46

NR

ES

47PB

03

48

Digital PinAnalog PinOscillator PinGroundInput SupplyRegulated Output SupplyReset PinSBC Pin

ATSAMHAXGXXAPinout


6. Signal Descriptions ListThe following table gives details on signal names classified by peripheral.

Signal Name Function Type Active Level

Analog Comparators - AC

AIN[3:0] AC Analog Inputs Analog

CMP[:0] AC Comparator Outputs Digital

Analog Digital Converter - ADC

AIN[19:0] ADC Analog Inputs Analog

VREFA ADC Voltage External Reference A Analog

VREFB ADC Voltage External Reference B Analog

Digital Analog Converter - DAC

VOUT DAC Voltage output Analog

VREFA DAC Voltage External Reference Analog

External Interrupt Controller

EXTINT[15:0] External Interrupts Input

NMI External Non-Maskable Interrupt Input

Generic Clock Generator - GCLK

GCLK_IO[7:0] Generic Clock (source clock or generic clock generatoroutput)

I/O

Power Manager - PM

RESETN Reset Input Low

Serial Communication Interface - SERCOMx

PAD[3:0] SERCOM I/O Pads I/O

System Control - SYSCTRL

XIN Crystal Input Analog/ Digital

XIN32 32kHz Crystal Input Analog/ Digital

XOUT Crystal Output Analog

XOUT32 32kHz Crystal Output Analog

Timer Counter - TCx

WO[1:0] Waveform Outputs Output

Timer Counter - TCCx

WO[1:0] Waveform Outputs Output

ATSAMHAXGXXASignal Descriptions List


Signal Name Function Type Active Level

Peripheral Touch Controller - PTCNote: Is not available on SAMHA0 devices

X[15:0] PTC Input Analog

Y[15:0] PTC Input Analog

General Purpose I/O - PORT

PA25 - PA00 Parallel I/O Controller I/O Port A I/O



PB17 - PB00 Parallel I/O Controller I/O Port B I/O



ATSAMHAXGXXASignal Descriptions List


7. I/O Multiplexing and Considerations

7.1 Multiplexed SignalsBy default each pin is controlled by the PORT as a general purpose I/O and alternatively can be assignedto one of the peripheral functions A, B, C, D, E, F, G or H. To enable a peripheral function on a pin, theperipheral multiplexer enable bit in the pin configuration register corresponding to that pin(PINCFGn.PMUXEN, n = 0-31) in the PORT must be written to “1”. The selection of peripheral function Ato H is done by writing to the peripheral multiplexing odd and even bits in the peripheral multiplexingregister (PMUXn.PMUXE/O) in the PORT.

This table describes the peripheral signals multiplexed to the PORT I/O pins.

Table 7-1. PORT Function MultiplexingPin I/O Pin Supply Type A B C D E F G H

48-pin EIC REF ADC AC PTC DAC SERCOM SERCOM-ALT

TC

/TCC

TCC COM AC/

GCLK

1 PA00 VDDANA E00 SERCOM1/PAD[0]

TCC2/WO[0]

2 PA01 VDDANA E01 SERCOM1/PAD[1]

TCC2/WO[1]

3 PA02 VDDANA E02 AIN[0] Y[0] VOUT

4 PA03 VDDANA E03 ADC/VREFADAC/

VREFP

AIN[1] Y[1]

7 PB06 VDDANA E06 AIN[14] Y[12]

8 PB07 VDDANA E07 AIN[15] Y[13]

9 PA04 VDDANA E04 ADCVREFP

AIN[4] AIN[0] Y[2] SERCOM0/PAD[0]

TCC0/WO[0]

10 PA05 VDDANA E05 AIN[15] AIN[1] Y[3] SERCOM0/PAD[1]

TCC0/WO[1]


TCC0/WO[0]


TCC0/WO[1]

13 PA08 VDDIO I2C NMI AIN[6] X[0] SERCOM0/PAD[0]

SERCOM2/PAD[0]

TCC0/WO[0] TCC1/WO[2]

14 PA09 VDDIO I2C E09 AIN[17] X[1] SERCOM0/PAD[1]

SERCOM2/PAD[1]


15 PA10 VDDIO E10 AIN[18] X[2] SERCOM0/PAD[2]

SERCOM2/PAD[2]

TCC1/WO[0] TCCO/WO[2]

GCLK_IO[4]

16 PA11 VDDIO E11 AIN[19] X[3] SERCOM0/PAD[3]

SERCOM2/PAD[3]


GCLK_IO[5]

17 PB10 VDDIO E10 SERCOM4/PAD[2]


GCLK_IO[4]



GCLK_IO[5]

23 PA14 VDDIO E14 SERCOM2/PAD[2]

SERCOM4/PAD[2]

TC3/WO[0] TCC0/WO[4]

GCLK_IO[0]


SERCOM4/PAD[3]


GCLK_IO[1]

25 PA16 VDDIO I2C E00 X[4] SERCOM1/PAD[0]

SERCOM3/PAD[0]


GCLK_IO[2]

26 PA17 VDDIO I2C E01 X[5] SERCOM1/PAD[1]

SERCOM3/PAD[1]


GCLK_IO[3]

27 PA18 VDDIO E02 X[6] SERCOM1/PAD[2]

SERCOM3/PAD[0]


AC/CMP[0]

ATSAMHAXGXXAI/O Multiplexing and Considerations


Pin I/O Pin Supply Type A B C D E F G H

48-pin EIC REF ADC AC PTC DAC SERCOM SERCOM-ALT

TC

/TCC

TCC COM AC/

GCLK


SERCOM3/PAD[3]


AC/CMP[1]

29 PB16 VDDIO I2C E00 SERCOM5/PAD[0]


GCLK_IO[2]

30 PB17 VDDIO I2C E01 SERCOM5/PAD[1]


GCLK_IO[3]


SERCOM3/PAD[0]


GCLK_IO[4]


SERCOM3/PAD[3]


GCLK_IO[5]


TC7/WO[0] GCLK_IO[0]






TCC1/WO[0] SWD CLK GCLK_IO[0]


TCC1/WO[1] SWDIO

48 PB03 VDDANA E03 AIN[11] Y[09] SERCOM5/PAD[1]

TC6/WO[1]

Note: It is recommended to enable a pull-up on PA24 and PA25 through input GPIO mode. The aim is toavoid an eventually extract power consumption (< 1 mA) due to a not stable level on pad.

Note: PTC is not available on SAMHA0 devices

Table 7-2. Internal Connections 48-pin

SBC Pin Microcontroller Pin MUX Function

TXD PB30 SERCOM[5]-PAD[0], Mux: D

RXD PB23 SERCOM[5]-PAD[3], Mux: D

7.2 Other Functions

7.2.1 Oscillator PinoutThe oscillators are not mapped to the normal PORT functions and their multiplexing are controlled byregisters in the System Controller (SYSCTRL).

Table 7-3. Oscillator Pinout

Oscillator Supply Signal I/O pin

XOSC VDDIO XIN PA14

XOUT PA15

XOSC32K VDDANA XIN32 PA00

XOUT32 PA01

7.2.2 Serial Wire Debug Interface PinoutOnly the SWCLK pin is mapped to the normal PORT functions. A debugger cold-plugging or hot-pluggingdetection will automatically switch the SWDIO port to the SWDIO function.



Table 7-4. Serial Wire Debug Interface Pinout

Signal Supply I/O pin

SWCLK VDDIO PA30

SWDIO VDDIO PA31

7.2.3 SERCOM I2C PinsTable 7-5. SERCOM Pins Supporting I2C

Device Pins Supporting I2C Hs mode

SAMHA0/1G PA08, PA09, PA16, PA17, PB16, PB17

7.2.4 GPIO ClustersTable 7-6. GPIO Clusters

PACKAGE CLUSTER GPIO SUPPLIES PINSCONNECTED TO THECLUSTER

48pins 1 PA31 PA30 VDDIN pin44/GNDpin42

2 PA27 PB22 VDDIN pin44/GNDpin42 and VDDIOpin36/GND pin35

3,4 PA11 PA10 PA09 PA21 PA20 PA20 PA19 PA15 PA17 PA16 PA15 PA14 PA08 PB11 PB10 VDDIO pin36/GNDpin35

5 PA07 PA06 PA05 PA04 PB17 PB16 PB06 PB07 VDDANA pin6/GNDANA pin5

6 PA03 PA02 PA01 PA00 PB03 VDDANA pin6/GNDANA pin5

7.2.5 TCC ConfigurationsThe SAMHA0/1 has three instances of the Timer/Counter for Control applications (TCC) peripheral, ,TCC[2:0]. The following table lists the features for each TCC instance.

Table 7-7. TCC Configuration Summary

TCC# Channels(CC_NUM)

WaveformOutput

(WO_NUM)

Countersize

Fault Dithering Outputmatrix

Dead TimeInsertion

(DTI)

SWAP Patterngeneration

0 4 8 24-bit Yes Yes Yes Yes Yes Yes

1 2 4 24-bit Yes Yes Yes

2 2 2 16-bit Yes

Note: The number of CC registers (CC_NUM) for each TCC corresponds to the number of compare/capture channels, so that a TCC can have more Waveform Outputs (WO_NUM) than CC registers.



8. Power Supply and Start-Up Considerations

8.1 Power Domain Overview

VOLTAGEREGULATOR

VDD

IN

VDD

CO

RE

GN

DADC

AC

DAC

PTC

XOSC32K

OSC32K

VDD

ANA

GN

DAN

A

PA[7:2]

PB[9:0]

PA[1:0]

Digital Logic(CPU, peripherals)

DFLL48M

VDD

IO

OSC8M

XOSC

OSCULP32K

PA[31:16]

PB[31:10]

PA[15:14]

BOD33

POR

PA[13:8]BOD12

FDPLL96M

8.2 Power Supply Considerations

8.2.1 Power SuppliesThe device has several different power supply pins:

• VDDIO: Powers I/O lines, OSC8M and XOSC. Voltage is 2.7V to 3.63V.• VDDIN: Powers I/O lines and the internal regulator. Voltage is 2.7V to 3.63V.• VDDANA: Powers I/O lines and the ADC, AC, DAC, PTC, OSCULP32K, OSC32K, XOSC32K.

Voltage is 2.7V to 3.63V.• VDDCORE: Internal regulated voltage output. Powers the core, memories, peripherals, FDPLL96M,

and DFLL48M. Voltage is 1.2V.

The same voltage must be applied to both VDDIN, VDDIO and VDDANA. This common voltage isreferred to as VDD in the datasheet.

The ground pins, GND, are common to VDDCORE, VDDIO and VDDIN. The ground pin for VDDANA isGNDANA.

ATSAMHAXGXXAPower Supply and Start-Up Considerations


For decoupling recommendations for the different power supplies. Refer to Schematic Checklist fordetails.

8.2.2 Voltage RegulatorThe voltage regulator has two different modes:

• Normal mode: To be used when the CPU and peripherals are running• Low Power (LP) mode: To be used when the regulator draws small static current. It can be used in

standby mode

8.2.3 Typical Powering SchematicsThe device uses a single main supply with a range of 2.7V - 3.63V.

The following figure shows the recommended power supply connection.

Figure 8-1. Power Supply Connection

(2.7V — 3.63V)Main Supply VDDIO

VDDANA

VDDIN

VDDCORE

GND

GNDANA

DEVICE

8.2.4 Power-Up Sequence

8.2.4.1 Minimum Rise RateThe integrated Power-on Reset (POR) circuitry monitoring the VDDANA power supply requires aminimum rise rate. Refer to the Electrical Characteristics for details.

Related LinksElectrical Characteristics

8.2.4.2 Maximum Rise RateThe rise rate of the power supply must not exceed the values described in Electrical Characteristics.Refer to the Electrical Characteristics for details.

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ATSAMHAXGXXAPower Supply and Start-Up Considerations


Electrical Characteristics

8.3 Power-UpThis section summarizes the power-up sequence of the device. The behavior after power-up is controlledby the Power Manager. Refer to PM – Power Manager for details.

Related LinksPM – Power Manager

8.3.1 Starting of ClocksAfter power-up, the device is set to its initial state and kept in reset, until the power has stabilizedthroughout the device. Once the power has stabilized, the device will use a 1MHz clock. This clock isderived from the 8MHz Internal Oscillator (OSC8M), which is divided by eight and used as a clock sourcefor generic clock generator 0. Generic clock generator 0 is the main clock for the Power Manager (PM).

Some synchronous system clocks are active, allowing software execution.

Refer to the “Clock Mask Register” section in PM – Power Manager for the list of default peripheral clocksrunning. Synchronous system clocks that are running are by default not divided and receive a 1MHz clockthrough generic clock generator 0. Other generic clocks are disabled except GCLK_WDT, which is usedby the Watchdog Timer (WDT).

atsamha1gxxa data sheet - microchip...

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