Assoc. Prof. Dr. Uda HashimSchool of Microelectronic EngineeringNorthern Malaysia university College of Engineering (KUKUM)Kangar, 01000 Perlis MALAYSIAEmail: uda@unimap.edu.my

Yesterday’s believe …….. Big is good !!!

Pyramid

Great Wall of China

Taj Mahal

Colloseum

Kuala Lumpur Twin Tower

POLITICIAN’S BELIEVE …HIGH IS SUCCESS

Today’s believe …….. Minute is better !!!

SemiconductorPatterned growth of Carbon Nanotubes for FED application

Nanolithography - “ONLY ONE”

1 μm

NANO IS UNIQUE …….. !!!

Cell-repair nanorobot repairing damaged cell in blood stream

NANO IS PRETTY …….. !!!

Nanostructures of ZnO synthesized under controlled conditions by thermal evaporation of solid powders

NANO IS AMAZING …….. !!!

Nano-gear for NEMs application

Nanotechnology is not new

• The Romans in the 10th century AD used nanoparticles of Au and Ag as colored pigments in stained glass and ceramics.

• Carbon black used in tyres and fumed silica in polymer are in nanosize.

Fig. 1 (a) Lycurgus Cup, Roman Era (4th Century A.D). It appears green in reflected light and red in transmitted light. It contains gold and silver particles of approximately 70 nm (b) and in the ratio 1:14. The special color effect is due to these nanocrystals [3].http://www.thebritishmuseum.ac.uk/science/lycurguscup/sr-lycugus-p1.html

GOALS OF IC MANUFACTURING

• OLYMPIC MOTO: – Higher– Faster– Stronger

• Semiconductor Industry Motto:– Smaller– Cheaper– Faster

Driving Force For The Manufacturer

To Make The Device Smaller and Smaller ….

Business

Moore’s Law - Drivers

• Increased transistor density – lower cost per transistor

• Faster switching speeds – more processing operations per second

• Greater complexity with no increase in power consumption

• Higher reliability

Technology Definition

Modern Definition

A technology node is define as being ½ theminimum pitch of the first layer of metal for a DRAM.

Modern Definition – Technology Node

Technology node is define as ½ pitch metal line-one dimension.(Based on Design specs and normally refer to DRAM)

For 90 nm node, the minimum metal line-one pitch is 180 nm and the gate length is 50 nm.

ITRS 2005

Technology Node and Gate Width

Why Smaller ?

Why this trend is so important?

– Smaller = faster– Smaller = more functionality– Smaller = cheaper– Smaller = Better

(In order to maintain the trend of faster, smaller, cheaper microchips,

the transistor gate lengths must continue to become smaller)

From IC to Computer

65 nm Device

The Path to “Smaller”

• Lithography– Print ever smaller features in photoresist– Minimum features resolution ~ (nλ/NA)

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The Path to “Cheaper”

• More Chips Per wafer– Bigger Wafer ~ 300 mm Fabs– Smaller Die-size

• More Good Chips Per Wafer ~ High Yield– SPC– FA to find defect causes– Better metrology– Automation

Scaling

350 nm

250 nm

180 nm

130 nm

90 nm

65 nm

45 nm

Technology is scaling 0.7X and doublesThe number of die on a wafer

300mm Si Wafer - 45nm Process

Path To “Faster”

• Clock-speed ~ 3 GHz

• Scaling Devices Features & Increase ID (mA/um)

(We want ID of Drive-Transistor to be as Big as Possible)

Chip Speed

• Digital Circuits – only 2 states ~ “0 & 1”

• In ICs we use voltages to represent them

• Swimming pool analogy– Empty – Don’t dive-in– Full – OK to jump– What about as pool fills?

• How long to wait before jumping in?

• Liftguard = clock signal on chip

Chip Speed – Swimming Pool Analogy

• Assume we want to fill & empty the pool quickly

• What determine fill time?– Pool Size (small Pool) CL

– Hose Diameter (Big) ID, R

– Water Pressure (high) VDD

VD

D

R

CL

I

D

Scaling The Transistor (MOSFET)

K = µC

ID = K (W/2L) (Vg – VT)2

C = єox/Tox

Carrier Mobility(holes or electrons) Capacitance Gate Oxide Thickness

Transistor length

Threshold Voltage

Transistor Width

Saturation Current

We want ID tobe HIGH

K valueGate Voltage

Scaling The MOSFET

• This means, for BIG ID, we want:

– Short L– Thin Gate Oxide Layer

– High Vg

– Wide W

– High Mobility (µn >µp)

MOS Field Effect Transistor - MOSFET

n+ n+

L

W

Problems of Scaling The MOSFET

• There are Technology Limits to Further Shrinking of MOSFET Device Feature Sizes

• The power Problem

Technology Limitation

• More Moore’s

• Approaching a “Red Brick Wall”

Moore’s Law - Barriers

• Many obstacles will need to be overcome if Moore’s Law is to continue for much longer.

• These include:– Physical limitations– Technological limitations– Design limitations– Economic limitations

• Looking at each of these in turn ….

Physical limitations

• Gate oxide thickness– Gate leakage current– Hot carrier effects– Situation improved using high-k dielectrics

• Stochastic variations in silicon doping– Random distribution of dopant impurities

• Sub-threshold leakage currents– Transistor channel cannot be fully switched off– Novel device structures - tri-gate MOSFET

Technological Limitations

• Contamination-free clean rooms• Lithography

– As dimensions shrink into the nanometre range it will be necessary to use Extreme UV (EUV) radiation to transfer patterns onto the silicon wafer surface (λ ~ 13.5nm)

– Preserving nanometre alignment accuracy across an area the size of a dinner plate (D = 300mm / 12”) presents certain challenges!

Design Limitations

• In the past, most of the delay experienced by signals propagating through the chip was due to the transistors themselves.

• At the nanoscale delays due to the interconnecting wires are the dominant factor – designers must take this into account.

• Testing is a huge problem – how do you locate a fault embedded in a billion transistor chip?

Economics

• The cost of building a state-of-the-art silicon processing facility has reached astronomical proportions

• Intel’s latest 65nm facility in Arizona was opened in November 2005 at a cost of $2bn.

• This level of investment has to be repeated every couple of years to keep on track with Moore’s Law.

Cost of Building a Fab Line

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What About the Future?

• In spite of the difficulties mentioned earlier, most people in the industry think that Moore’s Law will hold for about another 10 years (c 2015).

• By then, transistor dimensions will have shrunk to 22nm. Further improvements will demand some very innovative ideas!

Alternative Technologies

• To continue to make progress beyond current device technology, MOSFET Device technology must be changed by more than just SCALING.New MaterialsNew MOSFET Device StructuresNew Non-MOSFET Devices

New Materials

• Metal Gate Electrode• High-k Gate Dielectric• Low-k interconnect• SOI (or Bulk)• Strained-Silicon Strategy

n+ n+L

W

Gate

50 nm

Gate Oxide

New MOSFET Device Structures

• Advanced Lithography System – For precise and nano structure formation

• New Source-Drain Engineering Structure

New Non-MOSFET Devices

• Novel materials – e.g. III-V compounds such as Indium Antimonide (high electron mobility)

• Spin electronics (spintronics)

• Single-electron transistor

• Molecular electronics

• Carbon nanotubes

Power Dissipation Problem – Unsolved Issue

Power Components

Psw = N f ESW

Pp = I(V,T) x V

No of Gate

Frequency

Gate Energy Current Voltage

Power = Switching Power + Passive Power

Gate Switching Energy

• Energy required to switch between states:

Esw ~ CV2

– C is gate capacitance– V is supply voltage

• To minimise Esw:– Use smaller geometry devices - reduces C– Use smaller voltage swings - reduces V2

• Fundamental Limit to Esw is kT ~ 10-21 J

Computation as a Physical Process

In Any Given Technology, Logic Devices Will:

• Have a Certain Physical Size

• Take a Certain Time to Change State

• Dissipate Energy in Changing State

(These Represent the Unit Cost for a Computation - They Set the Scale Factor on the Size, Speed and

Power Requirements of a Computing system)

CMOS Inverters

P

N

VDD

0V

A

P

N

Y

Switch-Level RC Model

R

SN

VDD

0V

SP

R

3Cg

R

SN

SP

R

‘1’‘0’

‘1’

Switch-Level RC Model

R

SN

VDD

0V

SP

R

3Cg

R

SN

SP

R

‘0’‘1’

‘0’

Switch-Level RC Model

R

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0V

SP

R

3Cg

R

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‘1’‘0’

‘1’

Switch-Level RC Model

R

SN

VDD

0V

SP

R

3Cg

R

SN

SP

R

‘0’‘1’

‘0’

τ 3RCg

Power Dissipation

R

SN

VDD

0V

SP

R

3Cg

R

SN

SP

R

‘0’‘1’

‘0’

Components of Passive Power

• Major Components

Source leakage current – sub threshold off-state current

Gate current – tunneling current thru gate dielectric

Well current – band-to-band tunneling current to well

State of the Art Technology

• 65nm process technology– Minimum feature size = 65nm– Transistor gate width = 50nm– Gate oxide thickness = 1nm

• Gate capacitance C = 0.2fF (1fF = 10-15F)

• If supply voltage V = 1V, ESW = 0.2fJ per gate

State of the Art Technology

• Switching the gate on and off at a frequency of 1GHz (1Gigahertz = 109 Hertz or cycles per second) leads to the capacitance being charged and discharged at this rate.

• The energy expended per gate per second is equivalent to the power consumption of the gate

PD = ESW f

• So PD = 0.2fJ x 1GHz = 0.2W per gate

Chip Power Dissipation

• How many gates can we have simultaneously operating at this sort of frequency?

• For a chip containing N gates then the total power dissipated at switching frequency f is

PD = N ESW f

• If N = 500,000,000, PD = 100W if all the gates are switching on and off at the same time!

Power Dissipation and Scaling

• As the technology scales to smaller and smaller geometries the power density (in Watts per unit area) increases.

• Reducing the supply voltage V has helped to combat this by lowering ESW (recall that ESW V2)

• However, there are limits to how far the supply voltage can be reduced ….

Faster, faster, faster ……!

Until recently chip makers were committed to squeezing the last ounce of speed out of the technology. Clock speeds increased with each new technology generation.

As problems with power dissipation have increased, so alternative strategies have been developed.

Architectural Innovations

• Fortunately there are large sections of a chip that may be lying idle for much of the time – not actively processing information.

• By switching off these non-functioning parts of the chip it is possible to significantly reduce the power consumption. This can be achieved using ‘sleep transistors’.

• Chip designers are also looking at the use of multiple processor cores operating at slower clock speeds.

Conclusions

• Evolutionary progress in silicon planar technology has underpinned the revolution in computing, communications and IT for the past 40 years.

• Moore’s Law seems likely to continue to hold for the foreseeable future (c 10 years)

• Beyond that, a host of limitations – physical, economic, technological – will demand that innovative new solutions will have to be found.