ASIC Physical Design Using SynopsysINTRODUCTION

Very-Large-Scale-Integration (VLSI) of digital systems is the foundation of electronic applications that are used in everyday life. These applications vary from specialized parts to Application-Specific Integrated Circuits (ASIC), as well as Systems-On-Chips (SoCs). The designs of these systems are so complex that manual design would not be feasible. The only way to design and fabricate such complex designs is to use computers to automate portions of the design process. The focus of this article is on the numerous aspects of the physical design process and how those aspects are automated using computer-aided design (CAD) tools by Synopsys®.

As we all know that number of transistors on a chip has evolved from Large scale Integration to Very Large Scale Integration.This succession is continuing at Moore’s Law pace and as a result of that ,now what we see is the Intel Core i5 processor with billions on transistor on a single chip.

Therefore the problem and focus of this paper is clear: How does one create a complex electronic design consisting of millions of transistors? The solution is to automate the design process using computer-aided design (CAD) tools. These tools are necessary for complex designing of VLSI integrated circuits in which manual design is not possible. CAD tools provide several advantages such as the ability to evaluate complex conditions in which solving one problem creates other problems.

The solution of using CAD tools to create complex electronic designs falls under an industry category: Electronic Design Automation (EDA).There are several companies, such as Cadence® Design Systems, Magma® Design Automation Inc, and Synopsys®, who specialize in EDA software and CAD tools. Based in Mountain View, California, Synopsys® is a leading provider of EDA software used to design complex ASICs, FPGAs, and SoCs from concept to product.                        

Fig 1. Physical Design combined with Layout Verification are part of the final steps in the VLSI design flow of a system

This fig shows the generic design flow involved in VLSI design. The design flow is divided in the two parts

1. Front End Design: Front-end design includes most of the steps in the flow prior to physical design. (system specification and functional design)

2. Back End Design: Starting with physical design and beyond is considered the back-end of the design flow. EDA software in the form of CAD tools plays a vital role in all stages of the VLSI design flow. Therefore it is advantageous  that the output created at one stage of the flow will be able to become the input to the next stage. However, the EDA software and tools do not have to be from the same vendor. If one vendor has a better tool for Functional Verification, but another vendor’s tool is better for Logic Design, then a set of common input and output standards will allow the different tools to communicate with each other. The EDA industry has such common standards so that different tools from different vendors can be used during chip design.

A. Overview (Synopsys Astro)

The physical design stage of the VLSI design flow is also known as the “place and route” stage. This is based upon the idea of physically placing the circuits, which form logic gates and represent a particular design, in such a way that the circuits can be fabricated. This is followed by connecting the logic with routing (metal). The logic is connected in such a way as to form the function that was designed prior to physical design. For example, if the output of NAND logic is connected to the input of INVERTER logic, then the design has been routed to create AND logic.

Synopsys® software for the physical design process is called Astro™. The overall goal of this tool/software is to combine the inputs of a gate-level netlist, standard cell library, along with timing constraints to create and placed and routed layout. This layout can then be fabricated, tested, and implemented into the overall system that the chip was designed for. The first of the main inputs into Astro™ is the gate-level netlist, which can be in the form of Verilog or VHDL.

Netlist: netlist is nothing but the representation of your design circuit in terms of standard cells and the nets defining the connections between the input and output ports of these cells. See a small netlist example below: module dummy_design ( i0, i1, i2, out); input [1:0] i0; input i1; input i2; output o; wire net1, net2, net3; AND2X2 u0 ( a.(i0[0]), .b(i1), .o(net1) ); AND2X2 u1 ( .a(net1), .b(i2), .o(net3) ); NOR3X5 u2 ( .a(i0[1]), .b(net2), .c(i1), .o(net3) ); MUX2X4 u3 ( .d0(net1), .d1(net3), .s(i2), .o(out); endmodule This netlist is produced during logical synthesis (prior to the combination of functional design and logic design), which takes place prior to the physical design stage as indicated by Fig 1.

RTL: The RTL (Register Transfer Level) code is a description of the architecture or function of the design in terms of data flow between registers.

Abstract And Layout view

 The second of the main inputs into Astro™ is a standard cell library.The representation in the library is that of the physical shapes that will be fabricated.

Standard cells: These are small size circuit which performs basic digital functions like inverter, buffer, NOR, NAND XOR, AND, OR, ADDER, MUX, AOI, OAI, LATCH, FLIP-FLOP etc.

•Contains both Layout and Abstract views–Layout (CEL) contains drawn mask layers required for fabrication–Abstract (FRAM) contains only minimal data needed for Astro™–Timing information•Cell Delay / Pin Capacitance •Common height for placement purposes

The third of the main inputs into Astro™ are the design constraints. These constraints are derived from the system specifications and implementation of the design being created. Common constrains among the most of the design includes

•Common constraints in electronic designs are–Clock Speed/Frequency–Input / Output Delays associated with I/O signals–Multicycle Paths–False Paths

Now that the origin of the three main inputs to Astro™, gate-level netlist, standard cell library, and design constraints, are realized, what does Astro™ do? An overview of Astro™, since it is a place and route tool, is to say that it does exactly what was previously stated in the generic VLSI design flow: the tool places and routes.

what does Astro do?????

this can be better understood from the following fig.

What Does Astro Do???

What Does Astro Do???

–B.Concept Of Place And Route•Location of all standard cells is automatically chosen by the tool during placement (Based upon routing and timing)•Pins are physically connected during routing (Based upon timing).The tool then places the standard cells automatically based upon the timing of the design, which is given by the design constraints.

Place And Route

Placement Cells

Abutted and Non Abutted Cells

 

•Standard cells are placed in “placement rows”

•Cells in a timing-critical path are placed close together to reduce routing related delays (Timing Driven)•Placement rows can be abutting or non-abutting

These placement rows can either be abutted or non-abutted rows. As shown by Fig. 5, one drawback to non-abutted rows is increase in area due to the gap between standard cell placement rows. If the rows were abutted, then the cells on the top row would need to be flipped so that the VDD lines would merge as opposed to VSS shorting with VDD if they are not flipped. The most common approach is to implement abutted rows to reduce area as well as increase the metal size of the VDD or VSS connections.Routing•Connecting between metal layers requires one or more “vias”•Metal Layers have preferred routing directions–Metal 1 (Blue) Horizontal–Metal 2 (Yellow) Vertical–Metal 3 (Red) Horizontal

Design SetupBefore a design can be placed and routed within Astro™, the environment for the design needs to be created. The goal of the design setup stage in the physical design flow is to prepare the design for floorplanning.

As shown in the figure, the first step is to create a design library. Without a design library, the physical design process using Astro™ will not work. This library contains all of the logical and physical data that Astro™ will need. One of the inputs to the design library which will make the library technology specific is the technology file.Techfile:  Techfile in Synopsys internal format contains technology related data to represent layers and routing rules. Technology related data will contain definition of various grids, layers and routing rules (width and spacing atleast). It also contains basic RC estimation values (on per um basis). This is a text file and usually provided by foundry.The next step is to attach reference libraries to the design library. These reference libraries contain the standard cells, macro cells, pad cells, and/or reusable IP core cells that are being implemented into the design.The next step is to read the gate-level netlist into the library. This gate-level netlist is produced during the logic synthesis stage that was discussed earlier.Since most designs are complex enough to require logical hierarchy, the design needs to be flattened or made non-hierarchical in order to work for Astro™. This step is called expanding the netlist because each level of hierarchy in the design is expanded or flattened until the only representation is the leaf cells. During this process, Astro™ is able to validate that all leaf.

This starting cell will be the beginning point for place and route in Astro™. The directory structure is seen in UNIX or Linux for a design library named “design_lib_orca” as shown in figThe CEL directory is the where the starting cell and all subsequent cells are stored for place and route.

This leads to the next step which is referred to as binding the netlist to the cell. During this step, the expanded netlist is bound to a specific graphical cell view. This allows Astro™ to merge the logical and physical representations of the design.Once the netlist is bound to the starting cell and the hierarchy preserved in the design the library, the design setup stage is completed and the design is ready for the floorplanning stage.Design Flow1. FloorplanFloorplanning can be considered layout design done at the chip level.

•Layout design done at the chip level–Defining layout hierarchy–Estimation of required design area••A blueprint showing the placement of major components in the design (non-standard cell)–Inputs / Output (I/O)–RAMs / ROMs/–Reusable Intellectual Property (IP) macros••Approaches to Floorplanning (Automatic or Manual)                                                                                            –Constructive                                                                                            –Iterative                                                                                            –Knowledge-BasedGuidelines for a Good Floorplan•Floorplan of design:

–Core area defined with large macros placed–Periphery area defined with I/O macros placed

–Power and Ground Grid (Rings and Straps) established•Utilization:–The percentage of the core that is used by placed standard cells and macros–Goal of 100%, typically 80-85%Defining the Power/Ground Grid and Blockages

•Purpose of Grid is to take the VDD and VSS received from the I/O area and distribute it over the core area•Blockages can also be added in the floorplan to prohibit standards cells from being placed in those areas2.Timing Driven Placement

Timing-driven placement of a design is the process of placing all standard cells onto rows in the core area using the timing constraints as the guidelines as to where to place cells. Timing Driven Placement places critical path cells close together to reduce net RC. Prior to routing, RC are based .timing-driven placement will attempt to place cells within the critical timing paths close together to reduce wiring resistance and capacitance.•Astro™ needs constraints to understand the timing intentions–Arrival time of inputs

–Required arrival time at outputs–Clock period•Constraints come from the Logic Synthesis tool–SDC (Synopsys Design Constraints) formatThe optimizations done during placement use the cell delays of the functions being implemented and the net delays are calculated using virtual or best estimate routes envisioned by the placer. Once the design has been placed and the timing constraints met based upon virtual routes, the focus of physical design then shifts to the clock network of the system.3.Clock Tree Synthesis

All registers or flip-flops within a design have a clock input. These clock inputs are all driven or connected to a single clock source I/O in the pad area as shown in Fig.

Depending on the number of registers in the design, this clock net can have several hundred to several thousand connections. Since each register connected to clock is expected to function upon receiving a clock signal, it is important that the clock signal arrive at the inputs to the registers at the same time. If not, then data will be transferred through some registers more quickly than others depending upon the arrival of the clock. This can result in the possibility of incorrect data being shifted or clocked throughout the design. If the clock network is allowed to originate from one source and connect to all registers distributed throughout the core area, then problemswill occur associated with the signal transition time and capacitance due to the length of the net and the many connections (load) to it. Known as skew, if the clock reaches some registers before others, data transfer problems will be the result as well as overall timing objectives not being achieved.

Clock Tree Topologies

•Clock source is connected to center of the network

•Networks are distributed in a H or X shape until clock pin of register is driven by a local buffer

Astro™ has the ability to handle the single clock source problem using a variation of the previously discussed topologies through clock tree synthesis.

After Clock Tree Synthesis

•A clock (buffer) tree is built to balance the output loads and minimize the clock skew

•

•A delay line can be added to the network to meet the minimum insertion delay (clock balancing)

4.Routing

Routing is a fundamental step in the place and route process.The basic goal of routing is to create metal shapes that meet the requirements of a fabrication process. These metal shapes then become the physical connection between the cells in the design. Once the cells are connected by routing, the overall timing of the design needs to be preserved.

•Routing is a fundamental step in the place and route process

•Create metal shapes that meet the requirements of a fabrication process

–The physical connection between cells in the design

•Virtual routes used during placement and CTS need to become reality

–Timing of design needs to be preserved

–Timing data such as signal transitions and clock skew needs to match the virtual route estimates.

Timing Driven Routing

•Routing along the timing-critical path is given priority

–Creates shorter, faster connections

•Non-critical paths are routed around critical areas

–Reduces routing congestion problems for critical paths

–Does not adversely impact timing of non-critical paths

Concept of Routing Tracks

•Metal routes must meet minimum width and spacing “design rules” to prevent open and short circuits during fabrication

•In grid based routing systems, these design rules determine the minimum center-to-center distance for each metal layer (Track/Grid spacing)

•Congestion occurs if there are more wires to be routed than available tracks

Grid-Based Routing System

•Metal routes must meet minimum width and spacing “design rules” to prevent open and short circuits during fabrication

•

•In grid based routing systems, these design rules determine the minimum center-to-center distance for each metal layer (Track/Grid spacing)

•

•Congestion occurs if there are more wires to be routed than available tracks.

5. Verification

Formal Verification

•New standard cells have been added to the design through timing optimizations and clock tree synthesis

•The final netlist created by Astro™ needs to be compared to the original gate-level netlist

•Formal verification ensures the functional equivalency at the logic level between the two implementations (original vs. final) of the design

–The intended function was maintained throughout the physical design process.

Formality® is the Sign-Off Tool for Formal Verification

Timing Verification

•Star-RCXT™ performs the layout parasitic extraction of the resistances and capacitances of all routes in the design

•Results in a format such as SPEF (Standard Parasitic Extended Format)

–SPEF is an smaller, extended format of Standard Parasitic Format (SPF), which enables the transfer of design specific resistances and capacitances from physical design to timing analysis and simulation tools

•Primetime® performs static timing analysis

–Detects timing violations by combining SPEF from Star-RCXT™ and netlist from Astro™ and checks against the design timing constraints (clock frequencies)

Star-RCXT™ and Primetime® are the Sign-Off Tools for Timing Verification

Fabrication

•Physical Design process is complete upon successful completion of timing, functional, and physical verification

•The design can be “Taped-Out” and GDSII created for the manufacturer

–GDSII (Graphic Design System II) is a binary format containing the physical geometry information of the design.

–The shapes are assigned numeric attributes in the form of “Layer Number” and “Data Type” (Metal 1 => 100:0)

• Fabrication and Test determine which chips can be implemented into the system (yield)

6.Some Snap Shots

Floorplan

Floorplan Showing Logic Modules

AutoPlace of Logic Modules

Design placement

Reset Net

Pre Clock Tree Synthesis

Post Clock tree Synthesis

Routed Design

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