ARM Cortex M3Architecture:

Flash Patch:Permits patching flash locations for breakpointing and quick fixes3 stage pipelined Harvard ArchitectureFigure 1: ARM Cortex M3 Architecture

Thumb Instruction Set:It is a compact 16- bit encoding for a subset of ARM Instruction Set. Shorter opcodes gives improved code density. It allows increased performance in case of constrained BUS- width.

Thumb- 2 Instruction Set:It extends the limited 16- bit Instruction Set of Thumb with additional 32- bit instructions to give Instruction Set more breadth. Thus, providing a variable length Instruction Set (16- bit or 32- bit).

Programmers Model: Addressing Modes: Refer to Appendix- C Operating Modes: Thread Mode (entered on reset) and Handler Mode (entered on exception) Operating States: Thumb State (Normal Execution) and Debug State (Halt during Debug) Two types of stack: Main Stack and Process Stack 13 General Purpose Registers (32- bit) Stack point alias of banked registers, SP_process, SP_main Link Register r14 Program Counter r15 Program Status Register xPSR Application Program Status Register (APSR) Consists current state of condition flags InterruptProgram Status Register (IPSR) Consists ISR number [D8-D0] of current exception activation ExecutionProgram Status Register (EPSR) Consists Interruptible Continuous Instruction (ICI) field, Execution Status Field for If-Then (IT) Instruction and Thumb Status Bit (T- bit)

Figure 2: Processor core registers (Ref: ARM Cortex M3 Technical Reference Manual)

Instruction Set:All Thumb Instructions (Refer to Appendix- A) except BLX(1) and SETEND.All Thumb 2 instructions (Refer to Appendix- B).Special Features: Performance Efficiency: 3.32CoreMark/MHz Core Mark is a Benchmark to measure CPU performance. Performance Efficiency: 1.25/ 1.50 / 1.89DMIPS/MHz DMIPS (- Dhrystone Million Instructions per Second) is ananotherBenchmark to measure CPU performance. Optional 8 region MPU with sub regions and background region Non- maskable Interrupt (NMI) + 1 to 240 physical interrupts Interrupt priority levels: 8 to 256 priority levels Wake up Interrupt Controller: Up to 240 Wake-up Interrupts Sleep Modes 3 Sleep Modes: Sleep Now, Sleep on Exit, Deep Sleep Bit Manipulation: Integrated Instructions & Bit Banding It maps of complete word of memory onto a single bit in the bit band region. Enhanced Instruction: Hardware Divide (2-12 Cycles), Single-Cycle (32x32) Multiply, Saturated Math Support. Debug: Advanced Debug Tools (JTAG (- Joint Test Action Group) and Serial Wire Debug Ports) Trace: Optional Instruction Trace (ETM), Data Trace (DWT) and Instrumentation Trace (ITM)Commercial Chip Block Diagram (ST Microelectronics: STM32F20x):

Figure 3: STM32F20x block diagram (http://www.st.com/web/en/resource/technical/document/datasheet/CD00237391.pdf)

ARM Cortex M0+Architecture:

Figure 4: ARM Cortex M0+ Architecture

Programmers Model: Addressing Modes: Refer to Appendix- C Operating modes: Thread mode (application software enters thread mode after reset) and Handle mode (handles exceptions) Privilege levels: Unprivileged (limited access) and Privileged (complete access) Stack: Full descending stack; two types- Main stack (privileged) and Process stack (unprivileged) 13 general purpose registers R0-R12 Banked Stack Pointers: MSP (main stack pointer) and PSP (process stack pointer) Link Register (LR) R14 Program Counter (PC) R15 Program Status Register (xPSR) Application Program Status Register (APSR) Consists currentstate of condition flags InterruptProgram Status Register (IPSR) Consists ISR number [D8-D0] of current exception activation ExecutionProgram Status Register (EPSR) Consists Interruptible Continuous Instruction (ICI) field, Execution Status Field for If-Then (IT) Instruction and Thumb Status Bit (T- bit) Priority Mask Register (PRIMASK) Prevents activation of all exceptions with configurable priority Control Register (CONTROL) Controls stack used and privilege level for software execution

Figure 5: Processor core registers (Ref: ARM Cortex M0+ Technical Reference MAnual )

Instruction Set: All 16-bit Thumb instructions (Refer to Appendix- A) from ARMV7-M except CBZ, CBNZ, IT. Thumb- 2 Instructions (Refer to Appendix- B) BL, DMB, DSR, ISB, MRS, MSRSpecial Features: Most energy efficient ARM processor Performance Efficiency: 2.42 CoreMark/MHz Performance Efficiency: 0.93 DMIPS/MHz Sleep Modes: Normal Sleep Mode and Deep Sleep Mode Bit Manipulation: Implemented with Cortex- M system design kit Enhanced Instructions: Hardware single-cycle (32x32) multiply option Debug: optional JTAG( - Joint Test Action Group) or Serial- Wire Debug PortsCommercial Chip Block Diagram (ST Microelectronics: STM32F20x):

Figure 6: STM32L063x8 block diagram (http://www.st.com/web/en/resource/technical/document/datasheet/DM00102435.pdf)

ARM Cortex A9 MP DualCore

Architecture:

Figure 7: ARM Cortex A9 MP Dual Core ArchitectureProgrammers Model: Addressing Modes Refer to Appendix- C Modes of operation: User Mode (in which all the applications run), System Mode (provides privileged access to memory and coprocessors), Supervisor Mode (entered in it when CPU is reset or SVC is executed), Abort Mode (entered in it on Prefetch Abort or Data Abort eception), Undefined Mode (entered during undefined instruction exception), IRQ Mode (entered on IRQ execution), FIQ Mode (entered when processor handles FIQ interrupt), Hyp Mode (Hypervision Mode- provides hardware virtualization support), Monitor Mode (used for debugging without stopping the core entirely).

Figure 8: Modes of operations ARM Cortex A9 MPCore (Ref: ARM Cortex A9 MPCore Technical Reference Manual)

Privilege Levels: PL0 (executes User Mode), PL1 (executes in all modes other than User Mode and Hyp Mode), PL2 (executes in Hyp Mode) 16 ARM Core registers including R0 to R12, Stack Pointer (SP), Link Register and Program Counter (PC). Registers are selected from a large set of registers, that includes Banked copies of some registers. Banked copies of stack pointer are SP_irq and SP_hyp. CPSR (- Current Program Status Register) holds the processor status and control information. APSR- Application Program status resister ISATSTATE- Instruction Set status register ITSTATE- IT (If-Then) block status register ENDIANSTATE- Endianness mapping register SPSR- Saved Program Status Register (to record pre- execution value of CPSR)

Figure 9: ARM A9 Dualcore core registers, PSR, and ELR_hyp, showing register banking (Ref: ARM Cortex A9 MPCore Technical Reference Manual)

Instruction Set: 32- bit ARM Instruction Set 16- bit Thumb- 2 Instruction Set (Refer to Appendix- B)Specifications: Architecture: ARM v7-A Cortex Performance Efficiency: 2.50 DMIPS/MHz per core Optimized Level 1 Cache Optional Level 2 Cache Controller 8 to 11 stages pipeline Clock rate- 800 MHz to 2GHz NEON Media and Floating Point Processing Engine TrustZone Technology(Provides support for secured wide array of client and server computing)

Commercial Chip Block Diagram (Xilinx: Zynq7000):

Figure 9: Zynq7000 block diagram(http://www.xilinx.com/products/silicon-devices/soc/zynq-7000/index.htm)

ARM A1176JZF-S

Architecture:

Figure 10: ARM A1176JZF-S Core ArchitectureProgrammers Model: Addressing Modes Refer to Appendix- C Modes of operation: User Mode (in which all the applications run), System Mode (provides privileged access to memory and coprocessors), Supervisor Mode (entered in it when CPU is reset or SVC is executed), Abort Mode (entered in it on Prefetch Abort or Data Abort eception), Undefined Mode (entered during undefined instruction exception), IRQ Mode (entered on IRQ execution), FIQ Mode (entered when processor handles FIQ interrupt), Hyp Mode (HypervisionMode- provides hardware virtualization support), Secure Monitor Mode (secure mode for TustZone Secure Monitor code).

Figure 11: Mode Structure (Ref: ARM A1176JZF-S Reference Manual)

16 General purpose registers R0- R15 R13 is Stack Pointer (SP) R14 is Link Register (LR) R15 is Program Counter (PC)

Figure 12: Processor Core registers (Ref: ARM A1176JZF-S Reference Manual)

17 General purpose Mode- Specific registers 7 status registersInstruction Set: 16- bit Thumb Instruction Set (Refer to Appendix- A) 32- bit ARM Instruction Set 8- bit JAVA Instruction SetSpecifications: ARM v6 Instruction Set Architecture ARM DSP Extension SIMD (Single Instruction Multiple Data) media processing extensions deliver up to 2x performance for video processing ARM TrustZone Technology for on-chip security foundation 0.21 mW/MHz (65G) including cache controllers 8 stage pipelined architecture High performance Integer Processor High performance Memory System (Supports 4-64 k cache sizes)Commercial Chip Block Diagram (Samsung: S3C6400):

Figure 13: S3C6400 block diagram (http://read.pudn.com/downloads155/doc/project/687474/s3c6400_introduction01.pdf)

APPENDIX-AThumb Instruction Set:Rd is the destination register.Rn is the register holding the data for the first operand.Rm is the register holding the data for the second operand.shift is an optional shift to be applied to Rm.immedis the immediate operand.PCis the program counter.SP is the stack pointer.reglistis the non- empty list of registers. Rd, # MOV, ADD, SUB, CMP Rd, Rm MOV, CPY, ADD, ADC, SBC, NEG, MUL, AND, EOR, ORR, BIC, MVN, REV, REV16, REVSH, SXTH, SXTB, UXTH, UXTB Rd, Rn, # ADD, SUB Rd, Rn, Rm ADD, SUB SP, # ADD, SUB Rd, SP, # ADD Rd, PC, # ADD Rn, Rm CMP, CMN, TST Rd, Rm, # LSL, LSR, ASR Rd, Rs LSL, LSR, ASR Rd, [Rn, #] LDR, LDRH, LDRB, STR, STRH, STRB Rd, [Rn, Rm] LDR, LDRH, LDRSH, LDRB, LDRSB, STR, STRH, STRB Rd, [PC, #] LDR Rd, [SP, #] LDR, STR Rn!, LDMIA, STMIA Rm BLX SETEND

APPENDIX-B

Thumb-2 Instruction Set:Operand2 is a flexible operand which can be register or immediate data.Immx is x- bit immediate data.

Rd, Rn, ADD, ADC, SUB, SBC, RSB, RSC, AND, EOR, ORR, ORN, BIC Rd, Rn, # ADD, SUB Rd, Rm, Rn ADD, SUB, ADD16, SUB16, ADD8, SUB8, ASX, SAX, SEL PC, LR, # SUBS Rd, Rm, Rs USAD8, MUL, SMULxy, SMULWy, SMUAD, SMUSD, SMMUL Rd, Rm, Rs, Rn USADA8, USADA8, SMLAxy, SMLAWy, SMLAD, SMMLA, SMMLS Rd, #, Rm{, ASR } SSAT, USAT Rd, #, Rm{, LSL} SSAT, USAT Rd, MOV, MVN Rd, # MOVT, MOV Rn, CMP, CMN, TST, TEQ B, BL, BX, BLX, BXJ, DMB, DSB, ISB

APPENDIX-C

Addressing Modes: Register direct addressing mode MOV R0, R1 Direct addressing mode LDR R0, MEM Immediate addressing mode MOV R0, #15 ADD R1, R2, #12 Register Indirect addressing mode LDR R0, [R1] Register Indirect with Offset addressing mode LDR R0, [R1, #4] Register Indirect Pre Incrementing addressing mode LDR R0, [R1, #4]! Register Indirect Post Incrementing addressing mode LDR R0, [R1], #4 Register Indirect Index addressing mode LDR R0, [R1, R2] Register Indirect Index with Scaling addressing mode LDR R0, [R1, r2, LSL #2] Program Counter Relative addressing mode LDR R0, [PC, #offset]

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ARM Cortex M0+

Nested Vectored Interrupt Controller

Wake Up Interrupt Controller Interface

2 Stage pipeline

32 bit processor

CPU

Memory Protection Unit

Debug Access Port

Data Watchpoint

Breakpoint

Micro Trace Buffer

AHB- liteInterface

Low latency I/O interface

NVIC:Provides NMI and 32- external interrupt inputs

8 Region MPU (Optional):Enables enforcing privilege rules and managing memory attributes

AMBA (Advanced Microcontroller Bus Archi.) High performance BUS:Provides simple integration to all system peripherals and memory

MTB (Optional):Provides simple execution trace capability

AMBA (Advanced Microcontroller Bus Archi.) High performance BUS:Provides simple integration to all system peripherals and memory

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ARM CoreSight MulticoreDebug and Trace Architecture

FPU/NEON

PTM I/F

Cortex A9 CPU

I- Cache

D- Cache

FPU/NEON

PTM I/F

Cortex A9 CPU

I- Cache

D- Cache

Generic Interrupt Control and Distribution

Snoop Unit

Cache-2-Cache Transfet

Snoop Filtering

Timers

Accelerator Coherency Port

Advanced Bus Interface Unit

Primary AMBA 3 64- bit interface

Floating Point Unit:High performance single, double precision floating point instructions

Second interface with address filtering

Snoop Control Unit:Maintains data cache coherency between A9 processors

Data Cache and Instruction Cache:To avoid Structural Hazards.

Accelerator Coherency Port:Provides an interconnect point for system masters

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Debug Interface

Optional VFP

CoprocessorController

TrustZoneTM enabled ARM11TM core

Data Cache

TCRAM 1

TCRAM 0

Instruction Cache

TCRAM 1

TCRAM 0

Memory Management

AMBA AXI Interface

Instruction Interface

Data Interface

DMA

PeripheralPort

Vector floating Point (Optional):For floating point computations

Direct Memory Access:Accesses system memory independently of CPU

Tightly Coupled RAM:Low- latency memory used by the processor without unpredictability

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ETM interface

Control Logic

Thumb Decode

Thumb 2 Decode

32 bit ALU

Single Cycle 32 bit multiplier

Divider

NVIC interface

Bus interface

3 stage pipelined Harvard Architecture