1TMT H E A R C H I T E C T U R E F O R T H E D I G I T A L W O R L D

Introduction to ARM Processors

2TM 239v10 The ARM Architecture

3TM 339v10 The ARM Architecture

ARM History and Original Key Features

First ARM processor was developed in mid-eighties at Acorn Computers Limited in Cambridge, England

Originally, ARM stood for: Acorn RISC Machine Later it changed to: Advanced RISC Machine

Primary features right from the beginning: Load-store architecture

32-bit, fixed length instruction Many with single cycle execution

Where multiple cycles are required, memory access is minimized

15 general purpose registers Instruction pipeline Originally, 3-stage pipeline A 5-stage pipeline is available on some

of the newer derivatives

4TM 439v10 The ARM Architecture

5TM 539v10 The ARM Architecture

6TM 639v10 The ARM Architecture

7TM 739v10 The ARM Architecture

8TM 839v10 The ARM Architecture

ARM Today – www.arm.com

All major chip manufacturers have licenses to one or several ARM

cores 75% of the market Selection of license holders:

Analog Devices, Atmel, Cirrus, Fujitsu, IBM, Infineon, Intel, Mitsubishi, Motorola, National Semiconductor, NEC, Philips, Sharp, ST Microelectronics, Texas Instruments, Toshiba

The most popular ARM core for the use in embedded systems is the ARM7TDMI

TDMI stands for: Thumb Debug support Multiplier (64-bit result) In-Circuit Emulator interface

9TM 939v10 The ARM Architecture

RISC vs. CISC

ARM is a 32-bit RISC architecture(Reduced Instruction Set Computer)

Compared to the more traditional CISC architecture, a RISC architecture

Has a limited number of instructions All instructions are of fixed length

Allows for faster execution (often single cycle) Load-Store architecture:

Most instructions require that either the input or the output is one of the general purpose registers

10TM 1039v10 The ARM Architecture

RISC Performance and Drawback

RISC architectures can easily be optimized for best performance Instruction set with fixed length allow for faster execution Pipelining can be used more effectively

Chip die sizes get smaller for reduced instruction sets, allowing for faster clock rates

There is only one “real” drawback Code sizes tend to get bigger On a 32-bit RISC machine, every single instruction requires 4 bytes of code

space

11TM 1139v10 The ARM Architecture

ARM Derivatives: ARM7

Supersedes the ARM6

3-stage instruction pipeline

Low voltage support (some derivatives below 1V) Van Neumann memory layout with linear

32-bit address space (4 GByte)

Supports 8-bit and 16-bit data types

32-bit data bus

Supports little- and big-endian

12TM 1239v10 The ARM Architecture

ARM Derivatives: ARM9

Supersedes the ARM8

Roughly twice the performance of ARM7 Harvard memory layout with two 32-bit linear address spaces, one for

code and one for data

Improves overall memory access, as code AND data can be accessed in parallel

Double-bandwidth memory access

Making two memory accesses per cycle

5-stage instruction pipeline Reduced CPI (Clocks Per Instruction) Separate memory ports for instructions and data

13TM 1339v10 The ARM Architecture

ARM development tools

ARM has one of the widest development tool ranges available on the market

A commercial product listing is atwww.embedded.com/directories/embedded/arm2001/

C and C++ Compilers, Debuggers ADS (Arm Developer Suite)

Gnu gcc

Green Hills Software Multi 2000

MetaWare MetaWare High C++

Wind River Diab C/C++