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EE141

Adders

EE141- Fall 2002Lecture 17

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Announcements

l Homework 7 due next Tuesdayl No lab this weekl Project launch today: 32-bit ALU

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Today’s lecture

l Adder design

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Arithmetic Circuits

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A Generic Digital Processor

MEMORY

DATAPATH

CONTROL

INP

UT

-OU

TPU

T

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Building Blocks for Digital Architectures

Arithmetic unit

- Bit-sliced datapath (adder , multiplier, shifter, comparator, etc.)

Memory

- RAM, ROM, Buffers, Shift registers

Control

- Finite state machine (PLA, random logic.)

- Counters

Interconnect

- Switches

- Arbiters

- Bus

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An Intel Microprocessor

9-1

Mux

9-1

Mux

5-1

Mux

2-1

Mux

ck1

CARRYGEN

SUMGEN+ LU

1000um

b

s0

s1

g64

sum sumb

LU : LogicalUnit

SUM

SEL

a

to Cache

node1

REG

Itanium has 6 integer execution units like this

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Bit-Sliced Design

Bit 3

Bit 2

Bit 1

Bit 0

Reg

iste

r

Add

er

Shif

ter

Mul

tiple

xer

Control

Dat

a-In

Dat

a-O

ut

Tile identical processing elements

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Bit-Sliced Datapath

Adder stage 1

Wiring

Adder stage 2

Wiring

Adder stage 3

Bit slice 0

Bit slice 2

Bit slice 1

Bit slice 63

Sum Select

Shifter

Multiplexers

Loopback Bus

From register files / Cache / Bypass

To register files / CacheLoopback B

us

Loopback Bus

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Itanium Integer Datapath

Fetzer, Orton, ISSCC’02

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Full-Adder

A B

Cout

Sum

Cin Fulladder

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The Binary Adder

S A B Ci⊕ ⊕=

A= BCi ABCi ABCi ABCi+ + +

Co AB BCi ACi+ +=

A B

Cout

Sum

Cin Fulladder

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Express Sum and Carry as a function of P, G, D

Define 3 new variable which ONLY depend on A, B

Generate (G) = AB

Propagate (P) = A ⊕ B

Delete = A B

Can also derive expressions for S and Co based on Dand P

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The Ripple-Carry Adder

A0 B0

S0

Co,0Ci,0

A1 B1

S1

Co,1

A2 B2

S2

Co,2

A3 B3

S3

Co,3

(= Ci,1)FA FA FA FA

Worst case delay linear with the number of bits

tadder N 1–( )tcarry tsum+≈

td = O(N)

Goal: Make the fastest possible carry path circuit

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Complimentary Static CMOS Full Adder

VDD

VDD

VDD

VDD

A B

Ci

S

Co

X

B

A

Ci A

BBA

Ci

A B Ci

Ci

B

A

Ci

A

B

BA

28 Transistors

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Inversion Property

A B

S

CoCi FA

A B

S

CoCi FA

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Minimize Critical Path by Reducing Inverting Stages

A0 B0

S0

Co,0Ci,0

A1 B1

S1

Co,1

A2 B2

S2

Co,2 Co,3FA’ FA’ FA’ FA’

A3 B3

S3

Odd CellEven Cell

Exploit Inversion Property

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The better structure: the Mirror Adder

VDD

Ci

A

BBA

B

A

A BKill

Generate"1"-Propagate

"0"-Propagate

VDD

Ci

A B Ci

Ci

B

A

Ci

A

BBA

VDD

SCo

24 transistors

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The Mirror Adder

• The NMOS and PMOS chains are completely symmetrical. This guarantees identical rising and falling transitions if the NMOS and PMOS devices are properly sized. A maximum of two series transistors can be observed in the carry-generation circuitry.

• When laying out the cell, the most critical issue is the minimization of the capacitance at node Co. The reduction of the diffusion capacitances is particularly important.

• The capacitance at node Co is composed of four diffusion capacitances, two internal gate capacitances, and six gate capacitances in the connecting adder cell .

• The transistors connected to Ci are placed closest to the output.

• Only the transistors in the carry stage have to be optimized for optimal speed. All transistors in the sum stage can be minimal size.

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Transmission Gate Full Adder

A

B

P

Ci

VDDA

A A

VDD

Ci

A

P

AB

VDD

VDD

Ci

Ci

Co

S

Ci

P

P

P

P

P

Sum Generation

Carry Generation

Setup

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Manchester Carry Chain

CoCi

Gi

Di

Pi

Pi

VDD

CoCi

Gi

Pi

VDD

φ

φ

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Manchester Carry Chain

G2

φ

C3

G3

Ci,0

P0

G1

VDD

φ

G0

P1 P2 P3

C3C2C1C0

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Manchester Carry Chain

Pi + 1 Gi + 1 φ

Ci

Inverter/Sum Row

Propagate/Generate Row

Pi Gi φ

Ci - 1Ci + 1

VDD

GND

Stick Diagram

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Carry-Bypass Adder

FA FA FA FA

P0 G1 P0 G1 P2 G2 P3 G3

Co,3Co,2Co,1Co,0Ci,0

FA FA FA FA

P0 G1 P0 G1 P2 G2 P3 G3

Co,2Co,1Co,0Ci,0

Co,3

Mul

tiple

xer

BP=PoP1P2P3

Idea: If (P0 and P1 and P2 and P3 = 1)then Co3 = C0, else “kill” or “generate”.

Also called Carry-Skip

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Carry-Bypass Adder (cont.)

Setup

CarryPropagation

Sum

Setup

CarryPropagation

Sum

Setup

CarryPropagation

Sum

Setup

CarryPropagation

Sum

Bit 0-3 Bit 4-7 Bit 8-11 Bit 12-15

Ci,0

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Carry Ripple versus Carry Bypass

N

tp

ripple adder

bypass adder

4..8

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Carry-Select Adder

Setup

"0" Carry Propagation

"1" Carry Propagation

Multiplexer

Sum Generation

Co,k-1 Co,k+3

"0"

"1"

P,G

Carry Vector

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Carry Select Adder: Critical Path

Setup

"0" Carry

"1" Carry

Multiplexer

Sum Generation

"0"

"1"

Setup

"0" Carry

"1" Carry

Multiplexer

Sum Generation

"0"

"1"

Setup

"0" Carry

"1" Carry

Multiplexer

Sum Generation

"0"

"1"

Setup

"0" Carry

"1" Carry

Multiplexer

Sum Generation

"0"

"1"

Bit 0-3 Bit 4-7 Bit 8-11 Bit 12-15

S0-3 S4-7 S8-11 S12-15

Co,15Co,11Co,7Co,3Ci,0

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Linear Carry Select

Setup

"0" Carry

"1" Carry

Multiplexer

Sum Generation

"0"

"1"

Setup

"0" Carry

"1" Carry

Multiplexer

Sum Generation

"0"

"1"

Setup

"0" Carry

"1" Carry

Multiplexer

Sum Generation

"0"

"1"

Setup

"0" Carry

"1" Carry

Multiplexer

Sum Generation

"0"

"1"

Bit 0-3 Bit 4-7 Bit 8-11 Bit 12-15

S0-3 S4-7 S8-11 S12-15

Ci,0

(1)

(1)

(5)(6) (7) (8)

(9)

(10)

(5) (5) (5)(5)

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Square Root Carry Select

Setup

"0" Carry

"1" Carry

Multiplexer

Sum Generation

"0"

"1"

Setup

"0" Carry

"1" Carry

Multiplexer

Sum Generation

"0"

"1"

Setup

"0" Carry

"1" Carry

Multiplexer

Sum Generation

"0"

"1"

Setup

"0" Carry

"1" Carry

Multiplexer

Sum Generation

"0"

"1"

Bit 0-1 Bit 2-4 Bit 5-8 Bit 9-13

S0-1 S2-4 S5-8 S9-13

Ci,0

(4) (5) (6) (7)

(1)

(1)

(3) (4) (5) (6)

Mux

Sum

S14-19

(7)

(8)

Bit 14-19

(9)

(3)

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Adder Delays - Comparison

0.0 20.0 40.0 60.0N

0.0

10.0

20.0

30.0

40.0

50.0tp

ripple adder

linear select

square root select

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LookAhead - Basic Idea

A0,B0 A1,B1 AN-1,BN-1...

Ci,0 P0 Ci,1 P1Ci,N-1 PN-1

...

Co k, f Ak Bk Co k, 1–, ,( ) Gk P kCo k 1–,+= =

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Look-Ahead: Topology

VDD

P3

P2

P1

P0

G3

G2

G1

G0

Ci,0

Co,3

Co k, Gk Pk Gk 1– Pk 1– Co k 2–,+( )+=

Co k, Gk Pk Gk 1– P k 1– … P1 G0 P0 Ci 0,+( )+( )+( )+=

Expanding Lookahead equations:

All the way:

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Logarithmic Look-Ahead Adder

A7

F

A6A5A4A3A2A1

A0

A0

A1

A2A3

A4A5

A6

A7

F

tp∼ log2(N)

tp∼ N

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Carry Lookahead Trees

Co 0, G0 P0Ci 0,+=

Co 1, G1 P1 G0 P1P0 Ci 0,+ +=

Co 2, G2 P2G1 P2 P1G0 P+ 2 P1P0C i 0,+ +=

G2 P2G1+( )= P2P1( ) G0 P0Ci 0,+( )+ G 2:1 P2:1Co 0,+=

Can continue building the tree hierarchically.

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Tree Adders

Radix-2 Kogge-Stone Tree

(A0,

B0)

(A1,

B1)

(A2,

B2)

(A3,

B3)

(A4,

B4)

(A5,

B5)

(A6,

B6)

(A7,

B7)

(A8,

B8)

(A9,

B9)

(A10

, B10

)

(A11

, B11

)

(A12

, B12

)

(A13

, B13

)

(A14

, B14

)

(A15

, B15

)

S0

S1

S2

S3

S4

S5

S6

S7

S8

S9

S10

S11

S12

S13

S14

S15