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Comparative Analysis of 8 X 8 Bit

Vedic and Booth Multiplier

Sasha Garg, Swati Garg, Vidhi SachdevaElectronics and Communication

ITM UniversityGurgaon, INDIA

sasha4garg@yahoo.co.in, swatigarg_1992@yahoo.co.in,vidhisach@gmail.com

Abstract - Speed and power consumption are one of the mostimportant parameters to judge the performance of a

computational method. In this paper, we compare two

algorithms for 8 Bit multiplication namely Vedic

Multiplication Algorithm and Booth algorithm. This paper

aims in bringing to the fore the differences in compilation

speeds and the chip area consumption of the two

methodologies. The programming language used is Verilog andthe synthesis has been done on Xilinx 14.5.

Keywords: Vedic Multiplication, Booth Multiplication, Xilinx,

Verilog

I. INTRODUCTIONMultiplication forms one of the basic arithmetic

operations that find itself in wide use, especially in DigitalSignal Processing. A variety of computerarithmetic techniques are available which can be used inimplementation of a digital multiplier. Most of thesetechniques employ the concept of a set of partial productsand their simultaneous addition. The above process issimilar to the method that is taught to schoolchildren forconducting long multiplication on decimals, but has beenmodified here for application to binary digits. Variousmultiplication techniques are available in the field ofmathematics like, repetitive addition, Vedic Multiplication,Booth Multiplication, Ancient Egyptian Method etc. Thecomparison is based on 3 parameters: delay, area, power.These form the basis for judging the efficiency of the VLSIdesign of the multiplier in concern. The ancient technique ofVedic multiplication involves the use of UrdhavaTiryagbhyam Sutra[2]. Booth Multiplication algorithm[6,7]uses recorded multipliers. Vedic mathematics is mainly

based on sixteen principles or word-formulae which are

termed as sutras one of which is Urdhava TiryagbhyamSutra. Booth's multiplication algorithm is a multiplicationalgorithmthat multiplies two signed binary numbersin twos complements notation. In this paper, we focus on 8X 8 Bit multiplier using the above two mentionedtechniques implemented and simulated on Xilinx Version14.5.

II. BOOTH MULTIPLIERIn Booth multiplication the compilation speed it

increased due to the decrease in the number of partialproducts required to compute the result[1]. The algorithmmakes use of simple operations like twos complement,arithmetic right shift etc.; instead of more complicated ones

like addition. The architecture takes two 8 bit numbers asinput and generates a 16 bit product as the output. Since, weare performing signed multiplication the MSB of theoperands is always the signed bit and will not be used as

part of the magnitude. To decide on the multiplier and themultiplicand, we take the 2s complement of the twonumbers. The numerically smaller number is designated to

be the multiplicand and the other to be the multiplier. Nowthe beginning product is obtained by concatenating 8 0-bitswith the multiplier. The previous LSB is initialized as 0.Thecurrent LSB and the previous LSB together decide thecourse of the arithmetic action to be taken according to thefollowing:

00: no arithmetic operation

01: add multiplicand to left half of the product

10: subtract multiplicand from left half of theproduct

11: no arithmetic operation

Next, an arithmetic right shift (ASR) is performed on theentire product. The above process is repeated 8 times (sizeof operands).At the end of the 8

thpass, the final product is

obtained.

For hardware implementation of multiplication, same steps

are replicated as is done by hand, i.e., partial products are

computed, shifted accordingly, and summed. This algorithmthus, becomes very slow if there are many partial products

(i.e. many bits) as the output needs to wait until each sum isperformed. Booths algorithm decreases the number of

required partial products and hence is faster owing to thefact that the number of sums of partial products wasreduced.

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III. VEDIC MULTIPLIERThe Vedic Multiplier[2,3] uses the Urdhva Tiryagbyham

Sutra. It is also known as Vertical and Cross Wise method.

In this the partial products are obtained with the subsequentaddition of all the partial products.

For example, take two numbers and place them onebelow the other.

The following steps are then performed:

Multiply the digits at ones place with each otherand write it as the right most part of the answer.

Multiply the digits at tens place with each other.This is the left most part of the answer.

Then multiply the numbers crosswise and add theproducts to get the middle part.

If any carry is generated, it is added to the numberto its left.

Hence the answer is obtained.

In the case of Binary numbers, the multiplication isreplaced by AND logic. For a 4 bit multiplier consider twonumbers a3a2a1a0and b3b2b1b0. By using Vedic methods the

result obtained is a number which is more than 4 bits. Henceit is taken to be R7R6R5R4R3R2R1R0. The result is obtainedto be[1]:

i) R0= a0b0ii) R1= a0b1+ a1b0iii) R2= a0b2+ a1b1+ a2b0+ R1iv) R3 = a0b3+ a1b2+ a2b1+ a3b0+ R2v) R4= a1b3+ a2b2+ a3b1+ R3vi) R5= a1b2+ a2b1+ R4

vii) R6= a3b3+ R5viii) R7= carry of R6

An 8 bit multiplier is generated using four 4 bitmultipliers (which are formed with the help of AND gates,half adders and full adders) and 3 ripple carry adders. Theripple carry adders are formed by the combinations of XORgates, full adders and half adders. The ADDER 1 consists of7 full adders and a half adder. ADDER 2 comprises of fourhalf adders, three full adders and a XOR gate. ADDER 3has three half adders, four full adders and a XOR gate[4,5].

ARITHMETIC SHIFTRIGHTp,Q,cy_p

COUNT

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Fig. 3. OUTPUT FOR BOOTH MULTIPLIER

Fig. 4. OUTPUT FOR VEDIC MULTIPLIER

IV. COMPARISIONBased on our experimental findings of the comparison

conducted on the Nexys3, Spartan 6, the differences

between 8X8 Vedic Multiplier and Booth Multiplier can besummarized as follows:

The area in terms of utilization of slices is comparativelyless in Vedic Multiplier. The Vedic Multiplier uses 161slices whereas the Booth Multiplier uses 287 slices. Thenumber of fully used LUT-FF pairs is 0 in case of VedicMultiplier and 1 in case of Booth Multiplier.

The delay generated in Vedic Multiplier is approximately1/10th of the delay generated in Booth Multiplier.

TABLE 1. DELAY SUMMARY (BOOTH)

DELAY SUMMARY (BOOTH)

Delay 73.962 ns (Levels of Logic = 186)

Source u_7 (LATCH)

Destination u_7 (LATCH)

Source Clock x[7]_x[6]_Mux_o falling

Destination Clock x[7]_x[6]_Mux_o falling

TABLE 2. DELAY SUMMARY (VEDIC)

DELAY SUMMARY (VEDIC)

Delay 7.929 ns (Levels of Logic = 13)

Source x (PAD)

Destination Prod (PAD)

2014 International Conference on Advances in Computing,Communications and Informatics (ICACCI) 2609

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Fig. 9. COMPARISON (Delay)

Fig. 10. COMPARISON (Area)

V. CONCLUSIONThe Urdhva Tiryagbyham Sutra provides us with a

highly efficient method over Booth Algorithm formultiplication in terms of speed, delay and area utilization.Therefore, it can be concluded that the 8X8 bit VedicMultiplier is better than Booth Multiplier based on the

parameters discussed above. The specified architectures for

Vedic Multiplication and Booth Multiplication can beextended for 16- bit, 64-bit etc. multiplication.

VI. ACKNOWLEGMENTThis research paper is made possible through the help

and support from our Department of EECE, ITM Universitywho provided us with the necessary software and hardwareincluding Xilinx and FPGA Kit.

We would like to acknowledge the efforts and guidanceoffered by our faculty.

VII. REFERENCES[1] Premananda B.S.,Samarth S. Pai, Shashank B, Shashank S.

Bhat, Design and Implementation of 8-Bit Vedic Multiplier,

IJAREEIE, Volume. 2, Issue 12, December 2013

[2] Swami Bharati Krishna Tirthaji Maharaja, VedicMathematics, MotilalBanarsidass Publishers, 1965.

[3] Ch. Harish Kumar "Implementation and Analysis of Power,Area and Delay of Array Urdhava, Nikhilam Vedic Multipliers," Internatinal Journal of Scientific and Research Publications,

Volume 3, Issue 1 January 2013, ISSN 2250 3153.

[4] Anju and V.K. Agrawal, FPGA Implementation of Low Power

and High Speed Vedic Multiplier using Vedic Mathematics,IOSR Journal of VLSI and Signal Processing (IOSR-JVSP)Volume 2, Issue 5 Jun. 2013, ISSN: 2319 4200, pp. 51-57.

[5] Aniruddha Kanhe, Shishir Kumar Dasand Ankit Kumar Singh,Design and Implementation of Low Power Multiplier usingVedic Multiplication Technique, International Journal of

Computer Science and Communication, Volume 3, No. 1, June

2012, pp. 131-132.[6] Dr. Ravi Shankar Mishra, Prof. Puran Gour and Braj Bihari

Soni, 'Design and Implements of Booth and Robertsons

multipliers algorithm on FPGA',International Journal ofEngineering Research and Applications (IJERA)Vol 1(Issue 3),

pp. 905-910.

[7] Neha Goyal, Khushboo Gupta and Renu Singla (2014), 'Studyof Combinational and Booth Multiplier',International Journalof Scientific and Research PublicationsVolume 4(Issue 5).

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0

20

40

60

80

Delay(inns)

Vedic Mul.

Booth Mul.

0

100

200

300

400

NumberofLUTSlices

used Vedic Mul

Booth Mul2

2610 2014 International Conference on Advances in Computing,Communications and Informatics (ICACCI)