analysis and design of voltage-controlled oscillator

18 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 57, NO. 1, JANUARY 2010

Analysis and Design of Voltage-Controlled OscillatorBased Analog-to-Digital Converter

Jaewook Kim, Student Member, IEEE, Tae-Kwang Jang, Student Member, IEEE,Young-Gyu Yoon, Student Member, IEEE, and SeongHwan Cho, Member, IEEE

Abstract—A voltage-controlled oscillator (VCO) basedanalog-to-digital converter (ADC) is a time-based architecturewith a first-order noise-shaping property, which can be imple-mented using a VCO and digital circuits. This paper analyzes theperformance of VCO-based ADCs in the presence of nonidealitiessuch as jitter, nonlinearity, mismatch, and the metastability of Dflip-flops. Based on this analysis, design criteria for determiningparameters for VCO-based ADCs are described. In addition, adigital calibration technique to enhance the spurious-free dynamicrange degraded by the nonlinearity is also introduced. To verifythe theoretical analysis, a prototype chip is implemented in a0.13- � CMOS process. With a 500-MHz sampling frequency,the prototype achieves a signal-to-noise ratio ranging from 71.8to 21.3 dB for an input bandwidth of 100 kHz–247 MHz, whiledissipating 12.6 mW and occupying an area of 0.078��.

Index Terms—Analog to digital, analog-to-digital converter(ADC), analysis, data converter, design, digital calibration, fre-quency delta–sigma modulator, nonidealities, reconfigurable, timebased, voltage-controlled oscillator (VCO) quantizer, VCO based.

I. INTRODUCTION

I N DEEP-SUBMICROMETER processes, the design of ananalog-to-digital converter (ADC) based on voltage-do-

main signal processing is becoming more difficult due to thelow supply voltage that comes along with technology scaling.However, for time-based architectures, time resolution is im-proved from the reduced transition time of digital signals,which is on the order of tens of picoseconds for 130-nm CMOSprocesses and below [1].

An ADC based on a voltage-controlled oscillator (VCO) gen-erates a time-based signal whose frequency is proportional tothe analog input. The frequency is then quantized by countingthe edges of the VCO output during a sampling period [2].Since the VCO produces a continuous phase output, the quan-tization noise of the previous sample affects that of the currentsample, and hence, an inherent first-order quantization noise-shaping property can be achieved. However, unlike conventional

Manuscript received September 23, 2008; revised January 23, 2009.First published March 24, 2009; current version published January 08,2010. This work was supported by the Korean Government (MEST) underthe Korea Science and Engineering Foundation (KOSEF) under GrantR01-2008-000-11892-0. This paper was recommended by Associate Editor S.Pavan.

J. Kim and S. Cho are with the Department of Electrical Engineering andComputer Science, Korea Advanced Institute of Science and Technology(KAIST), Daejeon 305-701, Korea (e-mail: [email protected]).

T. Jang is with Samsung Electronics Company Ltd., Giheung 449-711, Korea.Y.-G. Yoon is with the Medical System Research Group, KAIST Institute,

Daejeon 305-701, Korea.Digital Object Identifier 10.1109/TCSI.2009.2018928

delta–sigma ADCs that require complex analog building blockssuch as op-amps and digital-to-analog converters (DACs), theVCO-based ADC can be implemented using only a VCO anddigital circuits. Since the operating frequency is limited by thespeed of the logic gates, it could easily reach up to gigasamplesper second in advanced CMOS processes.

Due to these attractive properties, there has recently beensome research on the VCO-based ADC. In [3], an energy-effi-cient VCO-based architecture operating in the subthreshold re-gion was implemented. In [4], a high-resolution and low-speedNyquist-rate ADC is realized for sensor application. In [5] and[6], a third-order noise-shaping ADC is realized by employinga feedback loop using two current DACs and an op-amp. In[7], a time-based bandpass ADC is realized by time-interleavingVCO-based ADCs. While these works have demonstrated thepotential of the VCO-based ADC, there has not been a thor-ough analysis of its performance, which includes the effectsof nonidealities. In terms of performance, an open-loop VCO-based ADC whose sampling frequency is over a few hundredsof megasamples per second has not yet been reported.

In this paper, nonidealities of the VCO-based ADC are the-oretically analyzed and verified in a prototype integrated cir-cuit (IC) with a sampling frequency of 500 MHz using 0.13-CMOS technology. From this analysis, the design criteria fordetermining the sampling frequency and the number of VCOdelay cells is described. In addition, a digital calibration methodto enhance the spurious-free dynamic range (SFDR) is intro-duced. This paper is organized as follows. In Section II, the op-eration principle and the properties of the VCO-based ADC arepresented. Section III describes the effect of nonidealities, andSection IV presents the design considerations for quantizers andthe digital calibration technique for VCO nonlinearity. Mea-surement results are then presented in Section V, and conclu-sions are drawn in Section VI.

II. VCO-BASED ADC

The basic architecture of a VCO-based ADC is shown inFig. 1. In previous works, this VCO–counter architecturehas been called a VCO–quantizer [5], [8], [9] or a frequencydelta–sigma modulator [3], [10]. In this paper, we will usethe term VCO–quantizer or VCO-based ADC to represent aVCO–counter architecture. The VCO converts the analog inputsignal from voltage domain to phase domain and generatesan output signal whose frequency is proportional to the averageanalog input signal . The reset counter counts the edges ofthe multiphase VCO outputs during a sampling clock periodand produces the digital output. Note that a sample-and-hold(S/H) is absent in our analysis, which is in contrast to previousanalyses that assume S/H before the VCO [5], [8]. In addition,

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KIM et al.: ANALYSIS AND DESIGN OF VCO-BASED ADC 19

Fig. 1. Block diagram of the VCO-based ADC including decimation filter.CLKs represents sampling clock.

our analysis is generalized with a multiphase VCO rather thana single-phase VCO. The signal waveform of a VCO–quantizeris shown in Fig. 2, where the VCO has a differential output andtwo counters count the rising edges of each output. Note thatthe quantizer resolution will increase if multiple output phasesare available from the VCO. Since the residual phase (i.e.,quantization error ) of the previous sampling periodinherently becomes the initial phase of the next period,the output of the VCO–quantizer can be represented as

(1)

where is the number of the VCO phase and is theVCO phase change due to the analog input. Taking the -trans-form of (1) gives

(2)

It can be seen that the quantization error of the VCO–quan-tizer is first-order shaped and, hence, is equivalent to a first-orderdelta–sigma modulator. To obtain the signal-to-quantizationnoise ratio (SQNR), is assumed to be a sinusoidalsignal with an amplitude of and frequency of [i.e.,

]. The phase-domain input signal canbe described as

(3)

where

(4)

where is the sampling period and and are the free-running frequency and gain of the VCO, respectively. It can beseen that the input-signal amplitude in the phase domain is asinc function of the input frequency, where is defined as

. Hence, the input-signal power in the phase domaincan be represented as

(5)

Fig. 2. Operation principle and waveforms of the VCO–quantizer.

For a general multiphase VCO with outputs, the counterquantizes the VCO phase by . As shown in Fig. 2, quan-tization error depends on the position of the sampling clock edgein a VCO period. Since there is no correlation between the sam-pling clock and the VCO, quantization error can be assumed tobe random and uniformly distributed from 0 to . Hence,the quantization error power in the phase domain can be ob-tained as follows, using a similar method to that of a conven-tional first-order delta–sigma ADCs [11]:

(6)

where , represents the sampling frequency,and represents the input frequency. From (5) and (6), thetheoretical SQNR can be calculated as follows:

(7)

where is the quantizer resolution, which can be representedas

(8)

where is the tuning range of the VCO .Note that the SQNR of the VCO–quantizer is different from theconventional delta–sigma modulator in that the quantizer reso-lution is inversely proportional to the sampling frequency.By plugging (8) to (7), it can be seen that SQNR is enhanced by10 dB/decade as the sampling frequency is increased. Anotherinteresting property that cannot be seen from the prior analyses[5], [8] is that SQNR is decreased with input-signal frequencydue to the absence of an S/H, i.e., the averaging nature of theVCO results in the last term in (7) which has a low-pass filteringproperty with nulls at integer multiples of the sampling fre-quency. Hence, when the VCO–quantizer is operated at Nyquistrate, the SQNR is reduced by 3 dB and signals near the integermultiples of are inherently filtered out.



Fig. 3. Timing diagram of sampling clocks with and without jitter. � �� and� �� represent absolute and period jitters of the �th sampling clock edge, re-spectively.

III. NONIDEAL EFFECTS

Nonidealities such as jitter, nonlinearity, mismatch of theVCO, and metastability of D flip-flops (DFFs) degrade or limitthe performance of the VCO-based ADC. In this section, theeffect of these nonidealities will be analyzed and simulated inMATLAB and CppSim [12], which is a behavioral simulatorthat accurately models the phase noise and jitter of oscillators.Throughout the simulation, it is assumed that there is a 64-phasering VCO with a tuning range of 50–450 MHz and that thesampling frequency is 500 MHz unless otherwise noted.

A. Sampling Clock Jitter

The sampling clock in the VCO-based ADC is not only usedfor sampling the input signal but is also used as a time referencefor integration. Hence, the effect of sampling clock jitter can bedivided into two parts: the sampling uncertainty caused by theabsolute jitter (i.e., aperture jitter) and the error in the integrationtime caused by the period jitter.

To analyze these effects, sampling clocks with and withoutjitter are shown in Fig. 3 together with the input signal .In this analysis, absolute jitter is defined as the time dif-ference between the th edge of an ideal and a practical sam-pling clock. Period jitter is defined as the time differencebetween the th period of an ideal and a practical clock [13].The phase-domain input signal with sampling jitter can be rep-resented as

(9)

This equation can be decomposed into the ideal phase-do-main input signal , the phase error due to sampling un-certainty , and the phase error due to integration time

, which can be described as follows:

(10)

where “ ” represents . Assuming thatis much smaller than the sampling period, and

can be approximated as the following:

(11)

(12)

Assuming that , the autocorrelation ofcan be expressed as [14], [15]

(13)

where represents the autocorrelation of . It can beseen that the power spectral density. (PSD) of , which is theFourier transform of , is upconverted to the input fre-quency at . Hence, a skirt around is expected in the outputspectrum of the ADC. In order to consider a general case of ab-solute-jitter PSD, the total noise power of is obtained, anda lower bound of the signal-to-noise ratio (SNR) is calculated.The total noise power of the sampling-clock uncertainty can beobtained as

(14)

(15)

where is the variance of the absolute jitter. Using the input-signal power of (5), the lower bound of can be obtainedas follows:

(16)

It can be seen that the effect of the absolute jitter on theVCO-based ADC is the same as the conventional voltage-basedADC. This result is quite natural, since the SNR degradationshould not depend on how the error due to sampling uncertaintyis processed, whether in voltage or time domain.

By obtaining the autocorrelation of and taking thediscrete-time Fourier transform, the PSD due to integration-timeerror can be obtained as

(17)

where represents the PSD of . It can be seenthat is equal to scaled by the tuning rangeand the free-running frequency of the VCO. The lower boundof the SNR can be obtained by calculating the total noise powerof , which can be expressed as

(18)



Fig. 4. FFT result of the VCO-based ADC in CppSim simulation without andwith sampling jitter.

Hence, is obtained as

(19)

Intuitively, the first term is natural since the periodjitter can be considered as the integration-time error. The sincfunction represents the effect of integration sampling on theinput signal. The last term shows up since aVCO with high free-running frequency will have a larger phaseerror than a VCO with low free-running frequency for the sameperiod jitter and tuning range. Hence, to minimize the effect ofperiod jitter, free running frequency should be reduced.

To verify the aforementioned theoretical analysis, CppSimsimulation is performed when the input frequency is 10 MHz.The fast-Fourier-transform (FFT) result of VCO-based ADCwith and without sampling jitter is shown in Fig. 4. As ex-pected, the skirt centered around the input frequency is showndue to the sampling uncertainty, and the noise floor is raised atlow frequencies due to both the sampling uncertainty and in-tegration-time error. Unfortunately, the effects of sampling un-certainty and integration time cannot be easily distinguished inthis simulation, and the SNR described in (16) and (19) cannotbe confirmed. Hence, two different simulations are performedunder the conditions that exclude the effect of each other. First,the number of VCO multiphases is increased to 1024 in orderto remove the effect of quantization noise. To make the effect ofsampling uncertainty dominant, the input frequency is increasedto 200 MHz. The FFT result is shown in Fig. 5(a) where therms absolute jitter is 68.1 ps and the resulting SNR is 22.2 dB.This is very close to the theoretical value of 21.34 dB obtainedfrom (16). To make the effect of integration-time error domi-nant, input frequency is reduced to 1 MHz, and the free-runningfrequency of the VCO is increased to 5 GHz. The FFT result isshown in Fig. 5(b), where the rms period jitter is 1.98 ps and theresulting SNR is 29.6 dB. This is very close to the theoreticalvalue of 30.0 dB obtained from (19).

Fig. 5. FFT result of the VCO-based ADC in CppSim simulation with sam-pling jitter. (a) Sampling uncertainty is dominant. (b) Integration-time error isdominant.

B. VCO Phase Noise

Similar to the previous analysis, the effect of the VCO phasenoise on the phase domain input can be described by the fol-lowing:

(20)

where is the input referred noise of the VCO and isthe output phase noise of the VCO. Taking the -transform ofthe aforementioned gives

(21)

The noise power can be expressed as

(22)

where is the continuous-time PSD of the VCO phase noise.It can be seen that the phase noise of the VCO is first aliased dueto sampling and then shaped by the high-pass filter . If



Fig. 6. SNR versus VCO phase noise. The �-axis represents the phase noiseof a single-phase VCO that can be run in CppSim. This phase noise can beconverted to the phase noise of a multiphase VCO by subtracting �� .For example, a 64-phase VCO with a tuning range of 400 MHz and a phasenoise of �120 dBc/Hz at a 1-MHz offset corresponds to a single-phase VCOwith a tuning range of 64� 400 MHz and a phase noise of�60 dBc at 1 MHz.

we assume that the VCO has a phase noise of L at a frequencyoffset of and a slope of 20 dB/decade, then incontinuous-time–frequency domain can be expressed as

L(23)

Applying (23) to (22), can be described as follows:

L

L(24)

Therefore, the SNR due to the VCO phase noisecan be obtained as the following:

L(25)

where is the input-signal frequency. To verify the aforemen-tioned theoretical analysis, the SNR due to the VCO phase noiseis obtained using CppSim when the VCO has a phase noise of

80 to 40 dBc at a 1-MHz offset. The SNR versus VCO phasenoise is shown in Fig. 6 with the theoretical result from (25),where it can be seen that the theoretical-analysis result is about2 dB higher than the simulation result. In Fig. 7, the FFT resultwith the VCO phase noise of 60 dBc/Hz at a 1-MHz offsetis shown along with that using an ideal VCO. It can be seenthat the white noise from the VCO phase noise is added to thefirst-order shaped quantization noise. Notice that the FFT plotdoes not have a skirt around the input signal, which is in contrastto the case of the sampling clock.

Fig. 7. FFT result of the VCO-based ADC in CppSim simulation without andwith VCO phase noise.

C. Nonlinearity of VCO Tuning Characteristic

When the VCO has a nonlinearity in its tuning curve, har-monic spurs are generated similar to a general voltage-basedADC with nonlinearity. However, there is a difference in howthe spurs show up, due to the absence of S/H in the VCO-based ADC, i.e., the harmonic spurs are sinc filtered just likethe signal. The input phase change due to the nonlinearity ofthe VCO can be represented as

(26)

The power of the second-harmonic and third-harmonic (HD3)spurs can be obtained by the following:

(27)

where it can be seen that the th harmonic spur is filtered bynulls at integer multiples of . Note that, due to such filtering,the intermodulation product can be much larger than the har-monic spurs. An example is shown in Fig. 8 where the samplingfrequency is 600 MHz and the two-tone inputs are at 198 and202 MHz. It can be seen that the power of the HD3 at 6 MHzis 26 dB smaller than that of the the third intermodulation prod-ucts (IM3s) at 194 and 206 MHz. In general, HD3 is 10 dB lowerthan IM3 [16] but sinc filtering further reduces the power of theHD3 by 16 dB.



Fig. 8. FFT result of a two-tone test. Sampling frequency is 600 MHz, and theinputs are at 198 and 202 MHz.

Fig. 9. Three-stage ring VCO and effect of VCO mismatch in phase diagram.

D. Mismatch of VCO Delay Cells

The mismatch of the VCO delay cells (VCO mismatch)causes error in their propagation delay and adds the deter-ministic phase error to the phase-domain input signal. Amultiphase ring VCO with mismatch is shown in Fig. 9, wherethe analog input is constant and the rising and falling edges ofthe delay-cell outputs are represented by upward and downwardarrows, respectively. It can be seen that, when the VCO hasa mismatch, the phase error is a periodic signalwhose period is half the VCO period because of the inherentcycling structure of the ring oscillator. In the VCO–quantizer,the phase error sampled at the sampling clock edgeis included as the quantization error, as shown in Fig. 9. Hence,the output of the VCO–quantizer with the VCO mismatch

can be represented as

(28)

where is the quantization error when the VCO is ideal.It can be seen that the phase error due to the VCO mismatch issampled and then first-order noise shaped.

Fig. 10. (a) PSD of phase error due to the VCO mismatch �� . PSD(b) when � �� is sampled by sampling clock and (c) when � �� issampled and first-order noise shaped.

When the analog input is not dc, the periods of the VCO andare changed. In this analysis, to get an insight in the

PSD, both and the analog input ) are as-sumed to be sinusoidal signals. Then, can be describedas

(29)

where is the amplitude of . The functionis periodic with frequency and,

hence, can be expanded in a Fourier series that can be describedas

(30)

where

(31)

and is the Bessel function of the first kind of order andargument [17]. Applying (30) to (29) and taking the real partgives

(32)

where it can be seen that spurs are generated at twice the free-running frequency and an infinite number of sidebands are sep-arated from the by integer multiples of . The PSD of (32)can be obtained as follows and is shown in Fig. 10(a):

(33)

Since the phase error due to the VCO mismatch is sampledand first-order noise shaped in the VCO–quantizer, as shown



in Fig. 10(b) and (c), the noise power can be expressed as thefollowing:

(34)

Therefore, the SNR due to the VCO mismatch can be ob-tained as follows:

(35)

Although this analysis restricts the periodic phase error dueto the VCO mismatch to a sinusoidal signal, it provides usefulinsights. From (33) and (34), it can be seen that shouldbe reduced in order to reduce the noise power due to mismatch.Since is proportional to the number of VCO delay cells,a small number of VCO delay cells is required, which means thatVCO operates at high speed. Another way to reduce the effectof the VCO mismatch is to control the free-running frequency.It can be seen from (33) that spurs due to the VCO mismatchare generated around the free-running frequency. Hence, spurscan be removed if the free-running frequency is moved far awayfrom the desired frequency.

To verify aforementioned theoretical analysis, a MATLABsimulation was performed as follows: A 514-phase ring VCOhas a tuning range of 6–55 MHz, the mismatch of VCO delaycells is 3%, and the analog input frequency and sampling fre-quency are 10 and 500 MHz, respectively. The FFT result and itsmagnified view are shown in Fig. 11. Since the VCO free-run-ning frequency is 30.5 MHz, dominant spurs are generated attwice the free-running frequency of the VCO, at 61 MHz, andthe sidebands are separated by 10 MHz. Note that sidebandspurs are symmetrical around 61 MHz and low-frequency side-bands are smaller than high-frequency sidebands due to the first-order noise shaping. In Fig. 12, two FFT results with differentfree-running frequencies are shown: 31 MHz for (a) and 87.5MHz for (b). It can be seen that a VCO with higher free-run-ning frequency moves the spurs in the desired bandwidth to highfrequencies. However, as described in Section III-A, the highfree-running frequency of the VCO increases the noise powerdue to the period jitter of the sampling clock. Therefore, tradeoffbetween the effect of sampling jitter and VCO mismatch exists.

E. Metastability of DFF

The reset counter of the VCO–quantizer shown in Fig. 1 isusually implemented by using DFFs and a subtractor, as shownin Fig. 13 [6]. The output of the counter is captured by the firstDFF at every rising (or falling) edge of the sampling clock,which is then delayed by the second DFF before subtraction.When the output of the counter is not stable at the samplingclock edges, an error may occur in the first DFF due to metasta-bility. The output of the VCO–quantizer that includesthe error from metastability can be described as the following:

(36)

Fig. 11. FFT result of VCO-based ADC and its magnified view in MATLABsimulation with 3% VCO mismatch.

Fig. 12. FFT result of VCO-based ADC in MATLAB simulation with 3% VCOmismatch when free-running frequency is (a) 31 and (b) 87.5 MHz.

where is the ideal counter output captured by the firstDFF, is the error of the DFF due to metastability, and

is defined in (1). It can be seen that is also first-ordershaped, similar to the error due to the quantization error. In thisanalysis, we assume that occurs only at the LSB of thecounter output. Although it is possible that error occurs at otherbits, it will be shown in the next section that these errors can beremoved.

To observe and the corresponding SNR, we consider ascenario where the VCO edges lie within the metastable window

of the DFF, as shown in Fig. 13. We assume that themetastable window is evenly split before and after the sam-pling clock. When the output of the counter changes during themetastability window , the captured output of the DFF can



Fig. 13. Effect of DFF metastability in timing diagram.

be more or less than the ideal output. In general, de-scribes the number of VCO edges during the metastable windowthat is incorrectly over- or undercounted. If we assume that theVCO has phases, can be expressed as the following:

(37)

where means to round up and is the VCO period.Assuming that is uniformly distributed, the variance of

can be calculated as

(38)

To obtain the total noise power due to the metastability ofDFF , the average of should be obtained becauseit depends on the analog input signal and hence changes everysampling period

(39)

Since the error of DFF due to metastability is first-ordershaped, the noise power in the phase domain can be obtainedas follows:

(40)

Therefore, the theoretical limit of the SNR due to DFFmetastability can be obtained as the following:

(41)

For example, when the input bandwidth is 5 MHz andis 500 ps, the maximum theoretical SNR is 59.04 dB. This wasverified using a MATLAB simulation whose SNR was 60.26 dB.

Fig. 14. Block diagram of reset counter for multibit quantization. Second DFFand subtractor are omitted.

The aforementioned analysis assumes that the error is uni-formly distributed. However, in practical situations, errors havea biased distribution rather than a uniform distribution, in whichcase metastability may manifest itself as VCO mismatch and in-troduces spurs.

IV. DESIGN OF VCO-BASED ADC

In this section, implementation issues regarding the numberof the delay cells and the digital calibration method for VCOnonlinearity will be described.

A. Multibit Quantization Versus 1-bit Quantization

When designing the VCO, one can either maximize the tuningrange and reduce the number of phases or maximize the numberof phases and reduce the tuning range. For a given process, theminimum time resolution is fixed, and the ADC’s performanceis the same for both cases. However, when nonidealities such asmismatch and metastability are considered, their performancewill be different. When the maximum output frequency of theVCO is higher than the sampling frequency, the number of edgesduring a sampling period can be more than one, thus requiringa multibit quantizer. This is called a multibit quantization, asopposed to a 1-bit quantization, where the output frequency ofthe VCO is always lower than the sampling frequency. Ideally,the performance of the VCO-based ADCs that use either oneof these techniques are the same, but nonidealities such as themetastability of DFF and the VCO mismatch cause differences.

As described in Section III, the DFF that stores the counteroutput at the sampling instance can cause errors because ofmetastability. Considering only one phase among the multi-phase VCO outputs, the maximum error due to metastability in1-bit quantization is just one. However, that of the multibit quan-tization is more, and it can severely degrade the performance ofthe VCO-based ADC. Assuming that the metastability windowis narrower than the propagation delay of the VCO, the afore-mentioned problem of a multibit quantizer can be solved bycomparing the counter output of the neighborhood multiphaseand replacing it when the difference is more than 1, as shown inFig. 14. Using this architecture, the maximum error of multibitquantization can be 1 bit, but the complexity and the power dis-sipation of the reset counter are increased due to the comparatorand multiplexer. On the other hand, 1-bit quantization can be re-alized with two DFFs and an XOR, as shown in Fig. 15. While itachieves simple implementation for the reset counter, too many



Fig. 15. Block diagram of reset counter for 1-bit quantization.

Fig. 16. Basic concept and block diagram of digital calibration for VCO non-linearity.

delay cells in the VCO can cause spurs from the mismatch ofthe delay cells, as described in Section III.

B. Digital Calibration of VCO Nonlinearity

As described in Section III, the nonlinearity of the VCOtuning characteristic generates harmonic spurs and degradesthe SNDR. The effect of nonlinearity is particularly moresevere when the input frequency is low, as the reduced SFDRdegrades the SNDR gained from oversampled noise shaping. Inorder to improve the resolution, a calibration technique can beemployed, as shown in Fig. 16. When the ADC is in calibrationmode, a ramp signal is applied to the VCO–quantizer. In termsof implementation, the ramp signal can be realized using adigital 1-bit accumulator and a DAC or a resistive divider anda switch. Note that the linearity of the DAC or the resistivedivider should be better than that of the VCO–quantizer. Next,the digital output of the VCO–quantizer goes througha moving average filter (MAF) that reduces the quantizationnoise. The output of the MAF can be represented as

(42)

where is the width of the moving average window. In prac-tical implementation, the MAF can be realized using a simpleadder, and can be removed by increasing the bit width ofthe by bits. The output of the MAF is stored in alookup table (LUT) which, in effect, is the inverse transfer func-tion of the VCO tuning curve. An example of the LUT is shownin Fig. 17, where the solid line represents the ideal ADC transfercurve and the bold dots represent the actual MAF output of theADC when a ramp is applied. When the ADC receives the ac-tual input signal, the digital output (D3) is mapped in the LUTto its corresponding address (011) and the calibrated output isproduced.

The complexity of the calibration circuitry depends on thesize of the LUT. When the duration of the ramp signal is

Fig. 17. Example of the proposed digital calibration scheme.

Fig. 18. Implemented overall architecture.

and the quantizer resolution is , the size of the LUT can bedescribed as

(43)

For example, a ramp signal of , an of 2,and result in a 150-byte mapping table, which isenough to improve the SFDR from 30 to 65 dB. The proposedcalibration technique is verified by the experimental results inthe next section.

V. IMPLEMENTATION AND MEASUREMENT RESULTS

The VCO–quantizer shown in Fig. 18 was fabricated in a0.13- CMOS technology. The VCO was implemented usingthe 32-stage differential delay cell shown in Fig. 19 [18]. Thering VCO is followed by 64 1-bit quantized reset counters anda 64-bit adder. The reset counter consists of one divider, twoDFFs, and an XOR gate. The divider and the first DFF use asense-amplifier-based flip-flop (SAFF), shown in Fig. 20 [19],for a small metastability window. The second DFF uses a truesingle-phase clocked register (TSPC) for low power consump-tion. The 64-bit adder is based on a carry–save architecture withthree-stage pipelining for a high-speed operation. The die pho-tograph is shown in Fig. 21, where it can be seen that the activearea is 0.078 .



Fig. 19. Delay-cell schematic of 64-phase ring VCO.

Fig. 20. SAFF schematic [19].

The measured tuning characteristic of the VCO is shown inFig. 22. In order to use the linear range of the tuning curve,the full-scale analog input is set to 0–0.7 V, which correspondsto 381–69 MHz of output frequency. The measured phasenoise of the ring VCO is 112 dBc/Hz at a 1-MHz offset.The VCO–quantizer operates at a sampling clock of 500 MHz,which has an absolute rms jitter of 83.9 ps when 1 millionsamples are collected. For an input frequency of 1.1 MHzand a peak-to-peak amplitude of 0.6 V, the FFT result of theVCO–quantizer is shown in Fig. 23, where the SNR is 64.25dB. It can be seen that the skirt centered around the inputfrequency reflects the effect of sampling jitter, particularlysampling uncertainty. When input bandwidth is determined asdc to 2 MHz, the theoretical limit of the SNR due to samplinguncertainty can be calculated as 64.73 dB from (16), whichis close to the measured SNR of 64.25 dB. As expected inSection III, the effect of other limiting factors such as VCO

Fig. 21. Die photograph of the ADC. The chip was fabricated in a 0.13-��CMOS process. The core area is �� .

Fig. 22. Measured tuning characteristic of the ring VCO.

Fig. 23. Measured power spectrum of ADC output. The peak-to-peak ampli-tude of the input signal is 0.6 V.

mismatch and metastability of the DFF are represented asspurs that can be seen in Fig. 23. However, these spurs do notdegrade the effective performance of the ADC because theyare located at high frequencies, i.e., when the ADC operatesas an oversampling ADC, these spurs can be filtered out. For a



Fig. 24. Measured power spectrum of ADC output. The peak-to-peak ampli-tude of the input signal is 13.4 mV.

Fig. 25. Measured power spectrum of ADC output before and after digital cal-ibration for VCO nonlinearity.

Nyquist-rate ADC, harmonic spurs from VCO nonlinearity arelarger than these spurs.

To verify the analysis of the VCO phase noise, a small inputsignal whose peak-to-peak amplitude of 13.4 mV was applied.Since SNR degradation due to sampling uncertainty is not afunction of input-signal power, the small input signal reducesthe noise power due to sampling uncertainty which otherwiseovershadows the effect of the VCO phase noise. The measuredpower spectrum of the VCO–quantizer is shown in Fig. 24,where the SNR of 48.63 dB is close to the theoretical-analysisresult of 47.59 dB from (25). Note that, for noise-power calcu-lation, the integration range is determined as 300 kHz–2 MHzbecause that is where the VCO phase noise has the char-acteristic assumed in (23)–(25).

To enhance the SFDR, the digital calibration method intro-duced in Section IV was applied. For an input frequency of

Fig. 26. SNR/SNDR/SNDR after calibration versus input power when theinput frequency is 1 MHz.

Fig. 27. SNR/SNDR/SNDR after calibration versus input bandwidth when theinput-signal power is �4.7 dBFS.

10 MHz, the FFT results of the VCO-based ADC before andafter calibration are shown in Fig. 25, where it can be seen thatthe SFDR is improved from 32.2 to 61 dB due to calibration.In this calibration, the width of the moving average is 2,and the duration of the ramp signal is 203 ns (about 100samples); hence, a 150-byte LUT is required. The MAF and theLUT for the calibration and decimation filters are implementedoff-chip. The SNR, SNDR, and SNDR after calibration versusthe input-signal power at 1 MHz are shown in Fig. 26. It canbe seen that the SNR of the VCO-based ADC is proportionalto the input-signal power to the full-scale input, which is incontrast to a conventional delta–sigma ADC whose SNR is de-graded near the full-scale input due to stability. When the inputsignal is small, the linearity of the VCO is better, and hence, theSNDR is limited by the quantization noise rather than harmonicspurs. As the analog input amplitude is larger than 20 dBFS,the linearity of the VCO is severely degraded, and the SNDR isreduced. However, the SNDR is improved to more than 60 dBwhen calibration is used.

The SNR, SNDR, and SNDR after calibration versus theanalog input bandwidth are shown in Fig. 27, when theinput-signal power is 4.7 dBFS. As expected, the SNDR islimited by the SFDR of 33.2 dB, and the SNR is limited by



TABLE IADC PERFORMANCE SUMMARY

Fig. 28. FOM versus input bandwidth.

the VCO phase noise for a low input bandwidth and by thequantization noise in a high input bandwidth. The figure ofmerit (FOM) of the VCO-based ADC versus the analog inputbandwidth is shown in Fig. 28, where the FOM is defined by

(44)

and the total power consumption is 12.6 mW. It can be seenthat the FOM is increased as the input bandwidth is reduced.This is due to the VCO phase noise that corrupts the quantiza-tion noise shaping, as shown in Fig. 23. When the input band-width is larger than 5 MHz, the FOM is relatively constant at1.01 pJ/conversion.

The performance of the measured VCO-based ADC is sum-marized in Table I with two other recently reported ADCs. Oneis a Nyquist-rate ADC which has the same sampling frequency,and the other is another VCO-based ADC, but it has an analogfeedback loop providing third-order noise shaping. Note thatthis paper has mostly digital circuits and should provide themost benefit in advanced CMOS process.

VI. CONCLUSION

A VCO-based ADC is an attractive time-based architecturethat offers a high sampling rate, an inherent first-order noise-shaping property, and mostly digital implementation. In thispaper, nonidealities from the VCO, DFF, and sampling clockthat degrade the performance of the ADC were analyzed and

verified using simulation and measurement. In addition, a dig-ital calibration method for the VCO nonlinearity has been in-troduced and proved using implemented IC and off-chip signalprocessing. The implemented ADC achieves an SNR from 71.8to 21.3 dB for an input bandwidth from 100 kHz to 247 MHzand dissipates 12.6 mW. With the continued scaling of CMOSprocesses, a VCO-based ADC is expected to gain higher perfor-mance, as its resolution is determined by the speed of the logicgate.

ACKNOWLEDGMENT

The authors would like to thank J. H. Lee and D. M. Park fortheir invaluable advices.

REFERENCES

[1] R. B. Staszewski and K. Muhammad, “All-digital TX frequencysynthesizer and discrete-time receiver for Bluetooth radio in 130-nmCMOS,” IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2278–2291,Dec. 2004.

[2] J. Kim and S. H. Cho, “A time-based analog-to-digital converter usinga multi-phase voltage-controlled oscillator,” in Proc. IEEE Int. Symp.Circuits Syst., May 2006, pp. 3934–3937.

[3] U. Wismar, D. Wisland, and P. Andreani, “A 0.2 V 0.44 �� 20 kHzanalog to digital delta sigma modulator with 57 fJ/conversion FoM,” inProc. ESSCIRC, Sep. 2006, pp. 187–190.

[4] T. Watanabe, T. Mizuno, and Y. Makino, “An all-digital analog-to-digital converter with 12- ��/LSB using moving-average filtering,”IEEE J. Solid-State Circuits, vol. 38, no. 1, pp. 120–125, Jan. 2003.

[5] M. Z. Straayer and M. H. Perrott, “A 10-bit 20 MHz 950 MHz CT��ADC with a 5-bit noise-shaping VCO-based quantizer and DEM circuitin 0.13 u CMOS,” in Proc. IEEE Int. Conf. VLSI Des., Jan. 2007, pp.246–247.

[6] M. Z. Straayer and M. H. Perrott, “A 12-bit, 10 MHz bandwidth, con-tinuous-time�� ADC with a 5-bit, 950 MS/s VCO-based quantizer,”IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 805–814, Apr. 2008.

[7] Y. Yoon, J. Kim, T. K. Jang, and S. Cho, “A time-based bandpassADC using time-interleaved voltage-controlled oscillators,” IEEETrans. Circuits Syst. I, Reg. Papers, vol. 55, no. 11, pp. 3571–3581,Dec. 2008.

[8] A. Iwata, N. Sakimura, and T. Morie, “The architecture of delta sigmaanalog-to-digital converters using a voltage-controlled oscillator as amultibit quantizer,” IEEE Trans. Circuits Syst. II, Analog Digit. SignalProcess., vol. 46, no. 7, pp. 941–945, Jul. 1999.

[9] H. T. R. Naiknaware and T. S. Fiez, “Time-referenced single-pathmulti-bit �� ADC using a VCO-based quantizer,” IEEE Trans.Circuits Syst. II, Analog Digit. Signal Process., vol. 47, no. 7, pp.596–602, Jul. 2000.

[10] M. Hovin, A. Olsen, T. S. Lande, and C. Toumazou, “Novel second-order �� modulator/frequency-to-digital converter,” Electron. Lett.,vol. 31, no. 2, pp. 81–82, Jan. 1995.

[11] D. Johns and K. Martin, Analog Integrated Circuit Design. Hoboken,NJ: Wiley, 1997.



[12] M. Perrott, “Fast and accurate behavioral simulation of fractional-Nsynthesizers and other PLL/DLL circuits,” in Proc. DAC, 2002, pp.498–503.

[13] U. Moon, K. Mayaram, and T. Stonick, “Spectral analysis of time-do-main phase jitter measurement,” IEEE Trans. Circuits Syst. II, AnalogDigit. Signal Process., vol. 49, no. 5, pp. 321–327, May 2002.

[14] H. Tao, L. Tóth, and J. M. Khoury, “Analysis of timing jitter in bandpass sigma–delta modulators,” IEEE Trans. Circuits Syst. II, AnalogDigit. Signal Process., vol. 46, no. 8, pp. 991–1001, Aug. 1999.

[15] K. Reddy and S. Pavan, “Fundamental limitations of continuous-timedelta–sigma modulators due to clock jitter,” IEEE Trans. Circuits Syst.I, Reg. Papers, vol. 54, no. 10, pp. 2184–2194, Oct. 2007.

[16] B. Razavi, RF Microelectronics. Hoboken, NJ: Wiley, 1994.[17] R. E. Ziemer and W. H. Tranter, Principles of Communications.

Boston, MA: Houghton Mifflin, 1990.[18] J. Lee and B. Kim, “A low-noise fast-lock phase-locked loop with adap-

tive bandwidth control,” IEEE J. Solid-State Circuits, vol. 35, no. 8, pp.1137–1145, Aug. 2000.

[19] A. G. M. Strollo, D. De Caro, E. Napoli, and N. Petra, “A novel high-speed sense-amplifier-based flip-flop,” IEEE Trans. Very Large ScaleIntegr. (VLSI) Syst., vol. 13, no. 11, pp. 1266–1274, Nov. 2005.

[20] B. Ginsburg and A. Chandrakasan, “500 MS/s 5 bit ADC in 65-nmCMOS with split capacitor array DAC,” IEEE J. Solid-State Circuits,vol. 42, no. 4, pp. 739–747, Apr. 2007.

Jaewook Kim (S’06) received the B.S. and M.S. de-grees in electrical engineering from the Korea Ad-vanced Institute of Science and Technology, Daejeon,Korea, in 2006 and 2008, respectively, where he iscurrently working toward the Ph.D. degree.

His research interests are time-based analog-to-digital converters, digital RF receivers, and soft-ware-defined radio.

Mr. Kim was the co-recipient of 2009 IEEETRANSACTIONS ON CIRCUITS AND SYSTEMS

Guillemon–Cauer Best Paper Award.

Tae-Kwang Jang (S’07) received the B.S. and M.S.degrees in electrical engineering from the Korea Ad-vanced Institute of Science and Technology, Daejeon,Korea, in 2006 and 2008, respectively.

Since 2008, he has been with Samsung Elec-tronics Company Ltd., Giheung, Korea, wherehe is involved in analog-circuit design includingphase-locked loops and data converters for com-munication systems and mobile processors. Hisresearch interests include the low-power design ofanalog and mixed-signal circuits.

Mr. Jang was the co-recipient of 2009 IEEE TRANSACTIONS ON CIRCUITS

AND SYSTEMS Guillemon–Cauer Best Paper Award.

Young-Gyu Yoon (S’08) received the B.S. and M.S.degrees in electrical engineering from KAIST, Dae-jeon, Korea, in 2007 and 2009, respectively.

Since 2009, he has been with KAIST Institute(KI), Daejeon, for IT Convergence as a research engi-neer. His research interests include analog-to-digitalconverter, time-based signal processing, soft-ware-defined radio and biomedical system.

Mr. Yoon was the recipient of 2009 IEEETRANSACTIONS ON CIRCUITS AND SYSTEMS

Guillemon–Cauer Best Paper Award.

SeongHwan Cho (S’94–M’03) received the B.S.degree in electrical engineering from the KoreaAdvanced Institute of Science and Technology(KAIST), Daejeon, Korea, in 1995, and the M.S. andPh.D. degrees in electrical engineering and computerscience from the Massachusetts Institute of Tech-nology, Cambridge, in 1997 and 2002, respectively.

During the summer of 1999, he was with the IBMT. J. Watson Research Center, Yorktown Heights,NY. In 2002, he joined Engim, Inc., where he wasinvolved in data converters, phased-locked loops,

and voltage-controlled-oscillator (VCO) design for IEEE 802.11(a)(b)(g) Wire-less LANs. From 2003 to 2004, he was with the military of Korea as a PublicService Agent. Since November 2004, he has been an Assistant Professor withthe Department of Electrical Engineering and Computer Science, KAIST.His research interests include mixed-signal and analog circuits for low-powercommunication systems and wireless sensor networks.

Dr. Cho has served as member of technical program committees (TPC) in sev-eral IEEE conferences, including the International Solid-State Circuits Confer-ence, the Asian Solid-State Circuits Conference, the Asia and South Pacific De-sign Automation Conference, and the International Symposium on Low PowerElectronics and Design. He was the co-recipient of 2009 IEEE TRANSACTIONS

ON CIRCUITS AND SYSTEMS Guillemon–Cauer Best Paper Award.


analysis and design of voltage-controlled oscillator

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