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CRC PRESS

Boca Raton London New York Washington, D.C.

AnalogVLSI

DesignAutomation

Sina BalkirGnhan DndarA. Seluk grenci


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This book contains information obtained from authentic and highly regarded sources. Reprinted material

is quoted with permission, and sources are indicated. A wide variety of references are listed. Reasonableefforts have been made to publish reliable data and information, but the author and the publisher cannotassume responsibility for the validity of all materials or for the consequences of their use.

Neither this book nor any part may be reproduced or transmitted in any form or by any means, electronicor mechanical, including photocopying, microfilming, and recording, or by any information storage orretrieval system, without prior permission in writing from the publisher.

The consent of CRC Press LLC does not extend to copying for general distribution, for promotion, forcreating new works, or for resale. Specific permission must be obtained in writing from CRC Press LLCfor such copying.

Direct all inquiries to CRC Press LLC, 2000 N.W. Corporate Blvd., Boca Raton, Florida 33431.

Trademark Notice: Product or corporate names may be trademarks or registered trademarks, and areused only for identification and explanation, without intent to infringe.

Visit the CRC Press Web site atwww.crcpress.com

2003 by CRC Press LLC

No claim to original U.S. Government worksInternational Standard Book Number 0-8493-1090-3

Library of Congress Card Number 2003046211Printed in the United States of America 1 2 3 4 5 6 7 8 9 0

Printed on acid-free paper

Library of Congress Cataloging-in-Publication Data

Balkir, SinaAnalog VSLI design automation / Sina Balkir, Gnhan Dndar, A. Seluk grenci.

p. cm. (VSLI circuits series)Includes bibliographical references and index.ISBN 0-8493-1090-31. Integrated circuits--Very large scale integration--Design and construction. I. Dndar,

Gnhan, 1959- II. grenci, A. Seluk (Arif Seluk) III. Title. IV. Series.TK7874.75.B35 2003621.395dc21 2003046211
http://www.crcpress.com/http://www.crcpress.com/http://www.crcpress.com/


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VLSI CIRCUITS SERIESSeries Editor

Wai-Kai Chen

PUBLISHED TITLES

PSPICE and MATLAB

for Electronics: An Integrated Approach,John O. Attia

VLSI Design,M. Michael Vai

Analog VLSI Design Automation,Sina Balkir, Gnhan Dndar, and Seluk grenci


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Structural DomainBehavioral Domain

Physical Domain

Registers, Adders, Gates, Flip-flops

Transistors

Processors, MemoriesAlgorithms, Flowcharts

RTL, Logic Level Abstraction

System Level Abstraction

Chips, Multi-chip Modules, Boards

Cells

Transistor layouts

Circuit Level Abstraction

Transistor level functions

Register transfers, Boolean expressions


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Design

System Simulation

Verification

Simulation

Verification

Simulation

VerificationDesign

Cell

Simulation

Verification

Simulation

Verification

Design

Architectural

Cell

Layout

Layout

System

System

Concept

Fabrication

Testing

and

Backtracking

redes

ign

Progress

Forward


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Selection

Topology

Specification

Translation

Verification Layout

Generation

Extraction

Verification

Level i+1

Level i

Layout at level iSpecifications at level i

Redesign

Specifications at level i+1 Layout at level i+1

-

-


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System Level

Circuit Level

Layout Level

Library

Performance

Estimator

Circuit

Extractor

Simulator

AdvisorLayout

Synthesized System

Behavioral Specifications

-

-


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Vin

Vout

1 1 1

1 1

2 2

2 2

2

-

-

+

+

S

S S

S

10

9

7

6

54

S3

S

S

S2

S

1S

8

C C

C

C C

C C

A

BD F

C

H

G


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biasbias

OUTPUTS

HIDDEN LAYER

INPUTS

-


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Read in SystemSpecifications

Block Topology

Library

Performance

Estimator

Choose a Particular

Topology

Calculate FinalCircuitSpecifications

CircuitBlockSpecificationDiagram


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Block #2

Output

Section

Section

Output

Block #1

V+

V -

Generalized

BlockEncapsulating

the Two Blocks

Block 2

Block 1


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Strength(beta,Vover,lambda)

Strength(beta,Vover,lambda)


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Subblock:

Current Mirror

Subblock:

Differential Pair

Subblock:

Current Mirror

Subblock:

Common Source

Main Block 2: Output StageMain Block 1: Differential Amplifier


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Vg

Id


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M4 M3

M2 M1


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No

Yes

No

Yes

Order?

Optimizer

Specifications

of Synthesis (Circuit and Layout)

Optimum?

Optimizer

To Topology Selection and Lower Levels

Second Stage

SC

First Stage

Increment

Current Order


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w2

w1

x1

x2

wn

w0

xn

bias

yActivation


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Multiplier

Multiplier

differences

voltage

INPUTS

as

Multiplier

WEIGHTS

R

Sigmoid

OPAMP

OUTPUT

current output


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Stage 1 specs,

error, resolution

Comp. Circuit

Stage Designer

Comp. Circuit

Stage Designer

S D

User specs,Resolution, speed

Topology Selection

Pipelined A/D Designer

Comp. specs,

Voffset, speed gain, speed

Switch specs,

error, speed

Comp. Designer

Opamp specs,

Opamp Designer Switch Designer

Opamp Circuit Switch Circuit

Comp. specs,

Voffset, speed gain, speed

Switch specs,

error, speed

Comp. Designer

Opamp specs,

Opamp Designer Switch Designer

Opamp Circuit Switch Circuit

error, resolution

Stage N specs,

Flash Designer Designer


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L

L

L

L

Vref Vin

2n

-1

2n

-1 2n

-1

Latches

bitn-

DigitalOutput

Encoder

R

R

R

R

R

2n

2n

-2

-3

1

Clock

}}

Comparators

}


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- -

- -

-


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-

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-


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Ni bits Ni bits Ni bits

FlashADC-bit Ni Ni-bit

DAC

S/HGS

Vin

Input S/H Stage 1Input

NSStageStage i

Output Register

+

-Vo

-


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2n-1+

Ni- bitFlash

C C C

DigitalCorrection Logic

Output

Vref

Vin

2C-

- +

- +

Ni- bitMDAC


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FlashADC

-bit Ni Ni-bit

DAC

S/HGS

Vin

Input S/H Stage 1Input

NSStageStage i

Output Register

+

-

Ni bit MDAC

Vo


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- -


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Configuration number1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33

7RWDO.RVW


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Plans

Design

SpecificationsPerformance

OK ?

PerformanceEvaluation

SpecificationsPerformance

Design PlanExecution

Size and Bias ValueOptimization

No Yes

Sizes and Bias Values

Sizes and BiasValues

(a) (b)


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Mismatch

Variations

TechnologyParameter

Compiler

Statistical

Predictor

DC Simulator

Trainer

Performance

Models

Network

Neural-Fuzzy

Equations

Solution

Neural-Fuzzy

User-defined

or

Topology Selection

Optimizer

Decision

Specifications


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M4

M

M M

3

1 2

CL

Vdd

V

ss

Ibias


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Vss

Vdd

Iss

M

M

MM

M M

M

M M M M

M

Cf

8 5 10 7

1 2

3 4

11

12

9

6

CL


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+

+X

X

Rule 1

Rule M

Layer 1 Layer 2 Layer 3

F

f

f

1

w

m

1

wm

x1

xn


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-


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Vin+Vin-

Vout

Vdd

Vss

I

Cf

CL

bias


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Vbias

Z

Y

Vc

X

Vss

ddV


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X

Y ZVin Vout

20 kOhm 20 kOhm

CCII circuit


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Vcm Cc

Vin- Vin+

Vbias

Cc

Vout-

Vout+

dd

I bias 1

V

ssV


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1,2,3,4,5

1144

33

22

55

2,3,5 1,

44

3,5

-

-

-

-

- -


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1,

2,

3,

4,

5

1144

33

22

55

2,3,5

3,5

1,4

2255

11 44


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1,2,3,4,5

2,3,5

3,5

1,4

1144

33

22

55

2255

11 44 22 55

11 44

44 11

55

22

33

1,2,3,4,5

2,3,5

3,5

1,4


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M1 M2

M3 M4

M5M8

M9

CC

M6

M11

M12

M10M7

Vdd

Vss

-

-

-

-

-


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H1,H2,M6,H0,M9,M8,M5,M7,M10

H1,H2,M6,H0,M9M8,M5,M7,M10

H1,H2,M6 H0,M9

M9H0 M5M8 M10M7

M8,M5 M7,M10

H2,M6H1

M6H2

-


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M3 M4

M5M8

M9

CC

M6

M11

M12

M10M7

Vdd

Vss

-


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Generation

Synthesizer

Synthesizer

Specifications

Estimation

Technology

SC Filter

SC Filter System Layout

SC

Performance

Target Manufacturing

Circuit Level

Automatic Layout

High Level

Topology Selection

-

-


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Vin+Vin-

Vout

Vdd

Vss

I

Cf

CL

bias

-


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-


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-

42

53

1

y2

y1

x1

x2

bias

Z

I1 I2

- 2.5V

+ 2.5V

U T


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Vout

bias

0V

I1 I2

I3 I4

V1V2

x

+2.5V

-2.5V


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SymbolWave

D0:A0:v(26)

D0:A0:v(25)

D0:A0:v(18)

Voltages

(lin)

0

500m

1

1.5

2

2.5

3

3.5

4

4.5

5

Time (lin) (TIME)

0 5u 10u 15u 20u 25u 30u

*** comparator ***


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SymbolWave

D0:A0:v(15)

D0:A0:v(16)

Voltages

(lin)

4

2.5

2.55

2.6

Time (lin) (TIME)

0 20u 40u 60u 80u

*** pipeline amplifier cikistan cm feedback 2***

SymbolWave

D0:A0:v(3)

D0:A0:v(2)

Vol

tages

(lin)

2.49999

2.499995

2.5

2.500005

2.50001

Time (lin) (TIME)

0 20u 40u 60u 80u


SymbolWave

D0:A0:v(15)

Voltages

(lin)

0

2

4

Time (lin) (TIME)

0 20u 40u 60u 80u


SymbolWave

D0:A0:v(16)

Voltage

s

(lin)

0

2

4

Time (lin) (TIME)

0 20u 40u 60u 80u


SymbolWave

D0:A0:v(3)

D0:A0:v(2)

Voltages

(lin)

2.4

2.6

Time (lin) (TIME)0 20u 40u 60u 80u



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SymbolWave

D0:A0:v(out7)

D0:A0:v(out8)

Voltages

(lin)

2

2.1

2.2

2.3

2.4

2.5

Time (lin) (TIME)

10u 15u 20u 25u 30u

*****pipe 1bit****


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Flash

Converters

ClockCircuitforPipeline

ClockCircuit

forFlash

FlashEncoder

andOutput

Multiplexer

Differentialto

SingleEnd

Converter

MDAC

3bit Encoder

ofFlashSub_ADC

Opamp in

MDAC

PipelineOutput

Multiplexerand

Encoder

3bit Flash

(Sub_ADC)

TestMDAC

Pads


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