analog ders 1
TRANSCRIPT
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EECE488: Analog CMOS Integrated Circuit Design
Set 2: Background
1SMEECE 488 – Set 2: Background
Shahriar Mirabbasi
Department of Electrical and Computer Engineering
University of British [email protected]
Technical contributions of Pedram Lajevardi in revising the slides is greatly acknowledged.
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Overview
1. Reading Assignments
2. Structure of MOS Transistors
3. Threshold Voltage
4. Long-Channel Current Equations
5. Regions of Operation
6. Transconductance
2SMEECE 488 – Set 2: Background
7. Second-Order Effects8. Short-Channel Effects
9. MOS Layout
10.Device Capacitances
11.Small-signal Models12.Circuit Impedance
13.Equivalent Transconductance
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Reading Assignments
• Reading:
Chapter 2 of the textbook
Section 16.2 of the textbook
Chapter 17
3SM EECE 488 – Set 2: Background
All the figures in the lecture notes are © Design of Analog CMOS Integrated Circuits ,McGraw-Hill, 2001, unless otherwise noted.
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Transistor
• Transistor stands for …
• Transistor are semiconductor devices that can be classified as
– Bipolar Junction Transistors (BJTs)
4SM EECE 488 – Set 2: Background
– e ec rans s ors s
• Depletion-Mode FETs or (e.g., JFETs)
• Enhancement-Mode FETs (e.g., MOSFETs)
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Simplistic Model
• MOS transistors have three terminals: Gate, Source, and Drain
• The voltage of the Gate terminal determines the type of connectionbetween Source and Drain (Short or Open).
• Thus, MOS devices behave like a switch
5SM EECE 488 – Set 2: Background
Device is ON
D is shorted to S
Device is OFF
D & S are disconnected
VG low
Device is OFF
D & S are disconnected
Device is ON
D is shorted to S
VG high
PMOSNMOS
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Physical Structure - 1
• Source and Drain terminals are identical except that Source providescharge carriers, and Drain receives them.
• MOS devices have in fact 4 terminals:
– Source, Drain, Gate, Substrate (bulk)
6SM EECE 488 – Set 2: Background
© Microelectronic Circuits, 2004 Oxford University Press
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Physical Structure - 2
• Charge Carriers are electrons in NMOS devices, and holes inPMOS devices.
• Electrons have a higher mobility than holes
• So, NMOS devices are faster than PMOS devices
• We rather to have a p-type substrate?!
7SM EECE 488 – Set 2: Background
LD: Due to Side Diffusion
Poly-silicon used instead of Metalfor fabrication reasons
• Actual length of the channel (Leff) is less than the length of gate
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Physical Structure - 3
• N-wells allow both NMOS and PMOS devices to reside on thesame piece of die.
8SM EECE 488 – Set 2: Background
• As mentioned, NMOS and PMOS devices have 4 terminals:
Source, Drain, Gate, Substrate (bulk)
• In order to have all PN junctions reverse-biased, substrate ofNMOS is connected to the most negative voltage, and substrateof PMOS is connected to the most positive voltage.
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Physical Structure - 4
• MOS transistor Symbols:
• electron
9SM EECE 488 – Set 2: Background
Current flows from Drain to Source
• In PMOS Devices:
Current flows from Source to Drain
• Current flow determines which terminal is Source and which oneis Drain. Equivalently, source and drain can be determined basedon their relative voltages.
DrainSource hole →
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Threshold Voltage - 1
• Consider an NMOS: as the gate voltage is increased, the surfaceunder the gate is depleted. If the gate voltage increases more,free electrons appear under the gate and a conductive channel isformed.
10SM EECE 488 – Set 2: Background
(a) An NMOS driven by a gate voltage, (b) formation of depletion region, (c) onset of inversion,and (d) channel formation
• As mentioned before, in NMOS devices charge carriers in thechannel under the gate are electrons.
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Threshold Voltage - 2
• Intuitively, the threshold voltage is the gate voltage that forces theinterface (surface under the gate) to be completely depleted of charge (inNMOS the interface is as much n-type as the substrate is p-type)
• Increasing gate voltage above this threshold (denoted by VTH or Vt)
induces an inversion layer (conductive channel) under the gate.
11SM EECE 488 – Set 2: Background
© Microelectronic Circuits, 2004 Oxford University Press
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Threshold Voltage - 3
Analytically:
ox
dep
F MS TH
C
QV +Φ⋅+Φ= 2
Where:
Potentialin-Built Φ−Φ==Φ Silicongate MS
12SM EECE 488 – Set 2: Background
substratesilicontheandgatenpolysilicothe offunctionsworkthebetweendifferencethe =
⋅
⋅==Φ
i
sub
F
n
N
q
T K lnpotential)atic(electrostFunctionWork
subF sidep N qQ ⋅Φ⋅⋅⋅== ε 4regiondepletiontheinCharge
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Threshold Voltage - 4
• In practice, the “native” threshold value may not be suited forcircuit design, e.g., VTH may be zero and the device may be on forany positive gate voltage.
• Typically threshold voltage is adjusted by ion implantation into thechannel surface (doping P-type material will increase VTH ofNMOS devices).
13SM EECE 488 – Set 2: Background
• When VDS is zero, there is no horizontal electric field present in thechannel, and therefore no current between the source to the drain.
• When VDS is more than zero, there is some horizontal electric fieldwhich causes a flow of electrons from source to drain.
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Long Channel Current Equations - 1
• The voltage of the surface under the gate, V(x), depends on thevoltages of Source and Drain.
• If VDS is zero, VD= VS=V(x). The charge density Qd (unit C/m) is uniform.
)( TH GS oxd V V WC Q −−=
( ) ( ) L
V V WLC
L
V C
L
QQ TH GS ox
d
−⋅−=
⋅−=
−=
14SM EECE 488 – Set 2: Background
))(()( TH GS oxd V xV V WC xQ −−−=
• If VDS is not zero, the channel is tapered, and V(x) is not constant. Thecharge density depends on x.
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Long Channel Current Equations - 3
velocityQdt
dx
dx
dQ
dt
dQ I d ⋅=×==
dt dV E E velocity −=⋅= , µ
))(
(dx
xdV velocity
−⋅=→ µ
• Current :
Velocity in terms of V(x):
Qd in terms of V(x):
15SM EECE 488 – Set 2: Background
))(()( TH GS oxd V xV V WC xQ −−−=
∫ −−=
∫ ==
DS V
V TH GS nox
L
x D dV V xV V WC dx I 00 ])([ µ
]2
1)[( 2
DS DS TH GS oxn D V V V V L
W C I −−= µ
dx
xdV V xV V WC I nTH GS ox D
)(])([ µ −−=
• Current in terms of V(x):
• Long-channel current equation:
© Microelectronic Circuits, 2004 Oxford University Press
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Long Channel Current Equations - 5
• For very small VDS (deep Triode Region):
ID can be approximated to be a linear function of VDS.
The device resistance will be independent of VDS
and willonly depend on Veff.
The device will behave like a variable resistor
17SM EECE 488 – Set 2: Background
( )
( )
( )TH GS oxn D
DS
ON
DS TH GS oxn D
TH GS DS
V V L
W C
I
V R
V V V
L
W C I
V V V If
−⋅⋅⋅
==
⋅−⋅⋅⋅=
−<<
µ
µ
1
:2
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Long Channel Current Equations - 6
• Increasing VDS causes the channel to acquire a tapered shape. Eventually,as VDS reaches VGS – VTH the channel is pinched off at the drain. IncreasingVDS above VGS – VTH has little effect (ideally, no effect) on the channel’s
shape.
18SM EECE 488 – Set 2: Background
© Microelectronic Circuits, 2004 Oxford University Press
• When VDS is more than VGS – VTH the channel is pinched off, and the
horizontal electric field produces a current.
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Long Channel Current Equations - 7
• If VDS > VGS – VTH, the transistor is in saturation (active) region,
and the channel is pinched off.
−V V L '
19SM EECE 488 – Set 2: Background
∫ −−=
∫ == V TH GS nox x D
dV V xV V WC dx I 00
])([
2)('2
1TH GS oxn D V V
L
W C I −= µ
• Let’s, for now, assume that L’=L. The fact that
L’ is not equal to L is a second-order effectknown as channel-length modulation.
• Since ID only depends on VGS, MOS transistors in saturation can be
used as current sources.
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Long Channel Current Equations - 8
• Current Equation for NMOS:
( )
−<<>⋅−⋅⋅⋅
−<
)()(2,;
)(;0
Triode DeepV V V V V if V V V L
W C
off Cut V V if
TH GS DS TH GS DS TH GS oxn
TH GS
µ
20SM EECE 488 – Set 2: Background
( )[ ]
−>>−⋅⋅⋅⋅
−<>⋅−⋅−⋅⋅⋅
==
)(,;)(2
1
)(,;2
1
2
2
SaturationV V V V V if V V L
W
C
TriodeV V V V V if V V V V L
W C
I I
TH GS DS TH GS TH GS oxn
TH GS DS TH GS DS DS TH GS oxn
DS D
µ
µ
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Long Channel Current Equations - 9
• Current Equation for PMOS:
( )
−<<>⋅−⋅⋅⋅
−<
)()(2,;
)(;0
Triode DeepV V V V V if V V V L
W C
off Cut V V if
TH SGSDTH SGSDTH SGox p
TH SG
µ
21SM EECE 488 – Set 2: Background
( )[ ]
−>>−⋅⋅⋅⋅
−<>⋅−⋅−⋅⋅⋅
==
)(,;)(
2
1
)(,;2
1
2
2
SaturationV V V V V if V V
L
W C
TriodeV V V V V if V V V V L
W C
I I
TH SGSDTH SGTH SGox p
TH SGSDTH SGSDSDTH SGox p
SD D
µ
µ
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Regions of Operation - 1
• Regions of Operation:
Cut-off, triode (linear), and saturation (active or pinch-off)
22SM EECE 488 – Set 2: Background
© Microelectronic Circuits, 2004 Oxford University Press
• Once the channel is pinched off, the current through the channel isalmost constant. As a result, the I-V curves have a very small slope inthe pinch-off (saturation) region, indicating the large channelresistance.
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Regions of Operation - 2
• The following illustrates the transition from pinch-off to triode region forNMOS and PMOS devices.
23SM EECE 488 – Set 2: Background
• For NMOS devices:If VD increases (VG Const.), the device will go from Triode to Pinch-off.
If VG increases (VD Const.), the device will go from Pinch-off to Triode.
** In NMOS, as VDG increases the device will go from Triode to Pinch-off.
• For PMOS devices:If VD decreases (VG Const.), the device will go from Triode to Pinch-off.
If VG decreases (VD Const.), the device will go from Pinch-off to Triode.
** In PMOS, as VGD increases the device will go from Pinch-off to Triode.
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Regions of Operation - 3
• NMOS Regions of Operation:
24SM EECE 488 – Set 2: Background
© Microelectronic Circuits, 2004 Oxford University Press
• Relative levels of the terminal voltages of the enhancement-type NMOStransistor for different regions of operation.
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Regions of Operation - 4
• PMOS Regions of Operation:
25SM EECE 488 – Set 2: Background
© Microelectronic Circuits, 2004 Oxford University Press
• The relative levels of the terminal voltages of the enhancement-type
PMOS transistor for different regions of operation.
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Regions of Operation - 5
Example:
For the following circuit assume that VTH=0.7V.
• When is the device on?
• What is the region of operation if the device is on?
26SM EECE 488 – Set 2: Background
• Sketch the on-resistance of transistor M1 as a function of VG.
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Transconductance - 1
• The drain current of the MOSFET in saturation region is ideally afunction of gate-overdrive voltage (effective voltage). In reality, it is alsoa function of VDS.
• It makes sense to define a figure of merit that indicates how well the
device converts the voltage to current.
27SMEECE 488 – Set 2: Background
•
• What voltage is in the designer’s control?
• What is this figure of merit?
.Const V V
I g
DS GS
D
m=∂
∂=
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Transconductance - 2
• Transconductance in triode:
W ∂ 1 2
Example:
Plot the transconductance of the following circuit as a function of VDS
(assume Vb is a constant voltage).
28SMEECE 488 – Set 2: Background
• Transconductance in saturation:
DS oxn
DS
DS DS TH GS oxn
GS
m
V L
W C
Const V LV g
⋅⋅⋅=
= ⋅−⋅−⋅⋅⋅
∂=
µ
.2
)(
.
)(
2
1 2
TH GS oxn
DS
TH GS oxn
GS
m
V V L
W C
Const V
V V
L
W C
V
g
−⋅⋅⋅=
=
−⋅⋅⋅⋅
∂
∂=
µ
µ
• Moral: Transconductance drops if the device enters the triode region.
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Transconductance - 3
• Transconductance, gm, in saturation:
TH GS
D
DoxnTH GS oxnmV V
I I
L
W C V V
L
W C g
−
⋅=⋅⋅⋅=−⋅⋅⋅=
22)( µ µ
• If the aspect ratio is constant: gm depends linearly on (VGS - VTH).Also, gm depends on square root of ID.
• If ID is constant: gm is inversely proportional to (VGS - VTH).
29SMEECE 488 – Set 2: Background
Also, gm depends on square root of the aspect ratio.
• If the overdrive voltage is constant: gm depends linearly on ID.
Also, gm depends linearly on the aspect ratio.
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Second-Order Effects (Body Effect)
Substrate Voltage:
• So far, we assumed that the bulk and source of the transistor are at thesame voltage (VB=VS).
• If VB >Vs, then the bulk-source PN junction will be forward biased, and
the device will not operate properly.• If VB <Vs,
– the bulk-source PN junction will be reverse biased.
– the depletion region widens, and Qde increases.
30SMEECE 488 – Set 2: Background
– VTH will be increased (Body effect or Backgate effect).
• It can be shown that (what is the unit for γ ?):
ox
subsiF SBF TH TH
C
N qV V V
⋅⋅⋅=
Φ⋅−+Φ⋅⋅+=ε
γ γ 2
220 where
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Body Effect - 2
Example:
Consider the circuit below (assume the transistor is in the active region):
• If body-effect is ignored, VTH will be constant, and I1 will only depend onVGS1=Vin-Vout. Since I1 is constant, Vin-Vout remains constant.
• In general, I1 depends on VGS1- VTH =Vin-Vout-VTH (and with body effectVTH is not constant). Since I1 is constant, Vin-Vout-VTH remains constant:
.. Conts DC V V V Const C V V V TH out inTH out in ==+=−→==−−
31SMEECE 488 – Set 2: Background
No Body Effect With Body Effect
C V V V Const C V V V TH out inTH out in +=−→==−− .
• As Vout increases, VSB1 increases, and as a result VTH increases.Therefore, Vin-Vout Increases.
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Body Effect - 3
Example:
For the following Circuit sketch the drain current of transistor M1 when VX
varies from -∞ to 0. Assume VTH0=0.6V, γ =0.4V1/2, and 2ΦF=0.7V.
32SMEECE 488 – Set 2: Background
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Channel Length Modulation - 1
L
• When a transistor is in the saturation region (VDS > VGS – VTH),
the channel is pinched off.
' W
21
33SMEECE 488 – Set 2: Background
( ) L
L L
L L L L L L
∆+⋅≈∆−
⋅=∆−
= 11
1
111
'
1
• - L
TH GS oxn D =−= '2
• Assuming we get: DS V
L L ⋅=∆ λ ( ) ( ) DS V
L L L
L L⋅+⋅=∆+⋅≈ λ 1
11
1
'
1
• The drain current is ( ) ( ) DS TH GS oxnTH GS oxn D V V V L
W C V V
L
W C I ⋅+⋅−≈−= λ µ µ 1
2
1 )(
'2
1 22
• As ID actually depends on both VGS and VDS, MOS transistors arenot ideal current sources (why?).
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Channel Length Modulation - 2
• λ represents the relative variation in effective length of the channel for a givenincrement in VDS.
• For longer channels λ is smaller, i.e., λ∝ 1 /L
• Transconductance:
In Triode:
.Const V V
I g
DS GS
D
m=∂
∂=
V W
C ⋅⋅⋅=
34SMEECE 488 – Set 2: Background
In Saturation (ignoring channel length modulation):
In saturation with channel length modulation:
• The dependence of ID on VDS is much weaker than its dependence on VGS.
L
TH GS
D DoxnTH GS oxnm
V V
I I
L
W C V V
L
W C g
−
⋅=⋅⋅⋅=−⋅⋅⋅=
22)( µ µ
( ) ( )TH GS
D DS Doxn DS TH GS oxnm
V V I V I
LW C V V V
LW C g
−⋅=⋅+⋅⋅⋅⋅=⋅+⋅−⋅⋅⋅= 2121)( λ µ λ µ
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Channel Length Modulation - 3
Example:
Given all other parameters constant, plot ID-VDS characteristic of an NMOSfor L=L1 and L=2L1
( ) ( )21
1V V V
W C I DS TH GS oxn D ⋅+⋅−≈ λ µ
• In Triode Region:
• In Saturation Region:
( )[ ] L
W
V
I
V V V V L
W
C I
DS
D
DS DS TH GS oxn D
∝∂
∂
⋅−⋅−⋅⋅⋅≈
:Therefore
2
2
1
µ
35SMEECE 488 – Set 2: Background
( )
2
2
2
1
L
W
L
W
V
I
V V L
W C V
I
DS
D
TH GS oxn DS D
∝⋅
∝∂
∂
⋅−=∂
∂
λ
λ µ
:Therefore
:getweSo
• Changing the length of the device from L1 to 2L1 will flatten the ID-VDS
curves (slope will be divided by two in triode and by four in saturation).• Increasing L will make a transistor a better current source, while
degrading its current capability.
• Increasing W will improve the current capability.
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Sub-threshold Conduction
• If VGS < VTH, the drain current is not zero.
• The MOS transistors behave similar to BJTs.
• In BJT:
•
T
BE
V
V
S C e I I ⋅=
T
GS
V
V
⋅ζ
36SM
EECE 488 – Set 2: Background
• As shown in the figure, in MOS transistors, the drain current drops byone decade for approximately each 80mV of drop in VGS.
• In BJT devices the current drops faster (one decade for approximately
each 60mv of drop in VGS).
• This current is known as sub-threshold or weak-inversion conduction.
D 0
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CMOS Processing Technology
• Top and side views of a typical CMOS process
37SM EECE 588 – Set 1: Introduction and Background
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CMOS Processing Technology
• Different layers comprising CMOS transistors
38SM EECE 588 – Set 1: Introduction and Background
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Photolithography (Lithography)
• Used to transfer circuit layout information to the wafer
39SM EECE 588 – Set 1: Introduction and Background
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Typical Fabrication Sequence
40SM
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Self-Aligned Process
• Why source and drain junctions are formed after the gate oxideand polysilicon layers are deposited?
41SM EECE 588 – Set 1: Introduction and Background
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Back-End Processing
• Oxide spacers and silicide
42SM EECE 588 – Set 1: Introduction and Background
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Back-End Processing
• Contact and metal layers fabrication
43SM EECE 588 – Set 1: Introduction and Background
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Back-End Processing
• Large contact areas should be avoided to minimize thepossibility of spiking
44SM EECE 588 – Set 1: Introduction and Background
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MOS Layout - 1
• It is beneficial to have some insight into the layout of the MOS devices.
45SM
EECE 488 – Set 2: Background
• When laying out a design, there are many important parameters we
need to pay attention to such as: drain and source areas,interconnects, and their connections to the silicon through contactwindows.
• Design rules determine the criteria that a circuit layout must meet for agiven technology. Things like, minimum length of transistors, minimumarea of contact windows, …
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MOS Layout - 2
Example:
Figures below show a circuit with a suggested layout.
46SM
EECE 488 – Set 2: Background
• The same circuit can be laid out in different ways, producing differentelectrical parameters (such as different terminal capacitances).
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Device Capacitances - 1
• The quadratic model determines the DC behavior of a MOS transistor.
• The capacitances associated with the devices are important whenstudying the AC behavior of a device.
• There is a capacitance between any two terminals of a MOS transistor.So there are 6 Capacitances in total.
• The Capacitance between Drain and Source is negligible (CDS=0).
47SM
EECE 488 – Set 2: Background
• These capacitances will depend on the region of operation (Biasvalues).
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Device Capacitances - 2
• The following will be used to calculate the capacitances betweenterminals:
1. Oxide Capacitance: ,
2. Depletion Capacitance:
3. Overlap Capacitance:
4. Junction Capacitance:
oxC LW C ⋅⋅=1ox
ox
oxt
C ε =
F
subsi
dep
N q
LW C C Φ⋅
⋅⋅⋅⋅==
42
ε
fringeox Dov C C LW C C C +⋅⋅=== 43
48SM
EECE 488 – Set 2: Background
Sidewall Capacitance:
Bottom-plate Capacitance:m
B
R
j jun
V
C C
Φ+
=
1
0 jswC
jC
jsw j C C C C +== 65
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Device Capacitances - 3
In Cut-off:
1. CGS: is equal to the overlap capacitance.
2. CGD: is equal to the overlap capacitance.
3. CGB: is equal to Cgate-channel = C1 in series with Cchannel-bulk = C2.
4. CSB: is equal to the junction capacitance between source andbulk.
3C C C ovGS ==
4C C C ovGD ==
49SM
EECE 488 – Set 2: Background
5. CDB: is equal to the junction capacitance between source and
bulk.5C C SB =
6C C DB =
D i C i
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Device Capacitances - 4
In Triode:
• The channel isolates the gate from the substrate. This means that if VG
changes, the charge of the inversion layer are supplied by the drainand source as long as VDS is close to zero. So, C1 is divided between
gate and drain terminals, and gate and source terminals, and C2 isdivided between bulk and drain terminals, and bulk and sourceterminals.
1. C : 1C C C +=
50SM
EECE 488 – Set 2: Background
2. CGD:3. CGB: the channel isolates the gate from the substrate.
4. CSB:
5. CDB:
0=GBC
2
2
25
C C C SB +=
2
26
C C C DB +=
2
1C
C C ovGD +=
D i C it 5
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Device Capacitances - 5
In Saturation:
• The channel isolates the gate from the substrate. The voltage acrossthe channel varies which can be accounted for by adding twoequivalent capacitances to the source. One is between source and
gate, and is equal to two thirds of C1. The other is between source andbulk, and is equal to two thirds of C2.
1. CGS: 13
2C C C
ovGS +=
51SM
EECE 488 – Set 2: Background
. GD
3. CGB: the channel isolates the gate from the substrate.4. CSB:
5. CDB:
0=GBC
253
2C C C
SB +=
6C C DB =
ovGD =
D i C it 6
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Device Capacitances - 6
• In summary:
CGB
CGD
CGS
SaturationTriodeCut-off
ovC
ovC
ovC
1
3
2C C ov +
0
2
1C C ov +
2
1C
C ov +
0121 C C
C C GB ⟨⟨
⋅
52SM
EECE 488 – Set 2: Background
CDB
CSB 2532C C +
6C 2
2
6
C C +
2
25
C
C +
21
6C
5C
I t f L t
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Importance of Layout
Example (Folded Structure):
Calculate the gate resistance of the circuits shown below.
53SM EECE 588 – Set 1: Introduction and Background
Folded structure:
• Decreases the drain capacitance
• Decreases the gate resistance
• Keeps the aspect ratio the same
Passive Devices
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Passive Devices
• Resistors
54SM EECE 588 – Set 1: Introduction and Background
Passive Devices
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Passive Devices
• Capacitors:
55SM EECE 588 – Set 1: Introduction and Background
Passive Devices
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Passive Devices
• Capacitors
56SM EECE 588 – Set 1: Introduction and Background
Passive Devices
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Passive Devices
• Inductors
57SM EECE 588 – Set 1: Introduction and Background
Latch-Up
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Latch-Up
• Due to parasitic bipolar transistors in a CMOS process
58SM EECE 588 – Set 1: Introduction and Background
Small Signal Models - 1
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Small Signal Models 1
• Small signal model is an approximation of the large-signal modelaround the operation point.
• In analog circuits most MOS transistors are biased in saturation region.
• In general, ID is a function of VGS, VDS, and VBS. We can use this Taylor
series approximation:
59SMEECE 488 – Set 2: Background
BS mb
o
DS
GS m BS
BS
D
DS
DS
D
GS
GS
D
D
BS
BS
D DS
DS
DGS
GS
D D D
V gr
V V gV
V
I V
V
I V
V
I I
V V I V
V I V
V I I I
∆⋅+∆
+∆⋅=∆⋅∂
∂+∆⋅
∂
∂+∆⋅
∂
∂≈∆
+∆⋅∂
∂+∆⋅∂
∂+∆⋅∂
∂+= sorder termsecond:ExpansionTaylor 0
Small Signal Models - 2
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Small Signal Models 2
• Current in Saturation:
• Taylor approximation:
• Partial Derivatives:
( ) ( ) DS TH GS oxnTH GS oxn D V V V L
W C V V
L
W C I ⋅+⋅−≈−= λ µ µ 1
2
1 )(
'2
1 22
BS
BS
D DS
DS
DGS
GS
D D V
V
I V
V
I V
V
I I ∆⋅
∂
∂+∆⋅
∂
∂+∆⋅
∂
∂≈∆
( ) m DS TH GS oxn D gV V V
W C
I =⋅+⋅−⋅⋅⋅=
∂λ µ 1)(
60SMEECE 488 – Set 2: Background
( )
mbm
SBF
m
SBF
DS TH GS oxn
BS
TH
TH
D
BS
D
o
DTH GS oxn
DS
D
GS
ggV
g
V V V V
L
W C
V
V
V
I
V
I
r I V V
LW C
V I
=⋅=
+Φ⋅−⋅−=
+Φ⋅−⋅
⋅+⋅−⋅⋅⋅−=
∂
∂⋅
∂
∂=
∂
∂
=⋅≈⋅−⋅⋅⋅⋅=∂
∂
η γ
γ λ µ
λ λ µ
22
221)(
1)(21 2
Small Signal Models - 3
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Small Signal Models 3
• Small-Signal Model:
BS mb
o
DS
GS m D vgr
vvgi ⋅++⋅=
• Terms, gm
vGS
and gmb
vBS
, can be modeled by dependent sources.These terms have the same polarity: increasing vG, has the sameeffect as increasing vB.
• The term, vDS /ro can be modeled using a resistor as shown below.
61SMEECE 488 – Set 2: Background
Small Signal Models - 4
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Small Signal Models 4
• Complete Small-Signal Model with Capacitances:
62SMEECE 488 – Set 2: Background
• Small signal model including all the capacitance makes the intuitive(qualitative) analysis of even a few-transistor circuit difficult!
• Typically, CAD tools are used for accurate circuit analysis
• For intuitive analysis we try to find a simplest model that can represent
the role of each transistor with reasonable accuracy.
Circuit Impedance - 1
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C cu t peda ce
• It is often useful to determine the impedance of a circuit seen from aspecific pair of terminals.
• The following is the recipe to do so:
1. Connect a voltage source, VX, to the port.
2. Suppress all independent sources.
3. Measure or calculate IX.
63SMEECE 488 – Set 2: Background
X
X
X
I V R =
Circuit Impedance - 2
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p
Example:
• Find the small-signal impedance of the following currentsources.
• We draw the small-signal model, which is the same for both
circuits, and connect a voltage source as shown below:
64SMEECE 488 – Set 2: Background
o
X
X X
o
X
GS m
o
X
X
r i
v R
r
vvg
r
vi
==
=⋅+=
Circuit Impedance - 3
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p
Example:
• Find the small-signal impedance of the following circuits.
• We draw the small-signal model, which is the same for bothcircuits, and connect a voltage source as shown below:
65SMEECE 488 – Set 2: Background
mbm
o
mbm
o
X
X
X
X mb X m
o
X
BS mbGS m
o
X
X
ggr
ggr
iv R
vgvgr
vvgvg
r
vi
111
1 =
++
==
⋅+⋅+=⋅−⋅−=
Circuit Impedance - 4
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p
Example:
• Find the small-signal impedance of the following circuit. Thiscircuit is known as the diode-connected load, and is usedfrequently in analog circuits.
• We draw the small-signal model and connect the voltagesource as shown below:
66SMEECE 488 – Set 2: Background
m
o
m
o
X
X
X
m
o
X X m
o
X
GS m
o
X
X
gr
gr
i
v R
g
r
vvg
r
vvg
r
vi
1
1
1=
+
==
+⋅=⋅+=⋅+=
• If channel length modulation is ignored (ro=∞) we get:
mmm
o X
gggr R
111=∞==
Circuit Impedance - 5
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Example:
• Find the small-signal impedance of the following circuit. Thiscircuit is a diode-connected load with body effect.
X mb X m
o
X
BS mbGS m
o
X
X
v
vgvgr vvgvg
r vi
1
++⋅=
⋅+⋅+=⋅−⋅−=
67SMEECE 488 – Set 2: Background
mbm
o
mbm
o
mbm
o
X
X
X
mm
o
ggr
ggr
ggr
i
v R
r
111
1
1=
+=
++
==
• If channel length modulation is ignored (ro
=∞) we get:
mbmmbmmbmmbm
o X
ggggggggr R
11111=
+=
+∞=
+=
Equivalent Transconductance - 1
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• Recall that the transconductance of a transistor was a a figure ofmerit that indicates how well the device converts a voltage to current.
• It is sometimes useful to define the equivalent transconductance of acircuit as follows:
.Const V V
I g
DS GS
D
m
=∂
∂=
I G OUT
∂=
68SMEECE 488 – Set 2: Background
.Const V V OUT IN
m
=∂
• The following is a small-signal block diagram of an arbitrary circuitwith a Norton equivalent at the output port. We notice that:VOUT=Constant so vOUT=0 in the small signal model.
0==
OUT IN
OUT
m
vviG
Equivalent Transconductance - 2
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Example:
• Find the equivalent transconductance of an NMOS transistorin saturation from its small-signal model.
69SMEECE 488 – Set 2: Background
m
IN
OUT
m
IN mGS mOUT
gv
iG
vgvgi
==
⋅=⋅=
Equivalent Transconductance - 3
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Example:
• Find the equivalent transconductance of the following circuitwhen the NMOS transistor in saturation.
70SMEECE 488 – Set 2: Background
( )
( ) S S mbS mOO
Om
O
S
S mbS m
m
IN
OUT
m
IN m
O
S
S mbS mOUT
O
S OUT
S OUT mbS OUT IN m
O
S
BS mbGS mOUT
S OUT GS S GS IN
R Rg Rgr r
r g
r
R Rg Rg
g
v
iG
vgr
R Rg Rgi
r
Ri Rig Rivg
r
vvgvgi
Rivvvv
+⋅+⋅⋅+
⋅=
+⋅+⋅+
==
⋅=
+⋅+⋅+⋅
⋅−⋅−⋅+⋅−⋅=−⋅+⋅=
⋅+=+=
1
1
)(
Short-Channel Effects
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• Threshold Reduction
– Drain-induced barrier lowering (DIBL)
• Mobility degradation
71SMEECE 488 – Set 2: Background
• Velocity saturation
• Hot carrier effects
– Substrate current
– Gate current
• Output impedance variation
Threshold Voltage Variation in Short Channel Devices
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• The Threshold of transistors fabricated on the same chip decreases asthe channel length decreases.
72SMEECE 488 – Set 2: Background
• Intuitively, the extent of depletion regions associated with drain andsource in the channel area, reduces the immobile charge that must beimaged by the charge on the gate.
Drain-Induced Barrier Lowering (DIBL)
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When the channel is short, the drainvoltage increases the channel surfacepotential, lowering the barrier to flowcharge from source (think of increased
electric field) and therefore, decreasingthe threshold.
73SMEECE 488 – Set 2: Background
Effects of Velocity Saturation
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• Due to drop in mobility at high electric fields
74SMEECE 488 – Set 2: Background
• (a) Premature drain current saturation and (b) reduction in gm
Hot Carrier Effects
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• Short channel devices may experience high lateral drain-sourceelectric field
• Some carriers that make it to drain have high velocity (called“hot” carriers)
“ ” “ ”
75SMEECE 488 – Set 2: Background
impact ionization
• The resulting electron and holes are absorbed by the drain andsubstrate causing extra drain-substrate current
• Really “hot” carriers may be injected into gate oxide and flow outof gate causing gate current!
Output Impedance Variation
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Recall the definition of λ.
76SMEECE 488 – Set 2: Background
Output Impedance Variation in Short-Channel Devices