an5109 introduction application note · table 4. system’s low-power mode wakeup capabilities...

IntroductionSTM32MP15x lines devices are built on an Arm® Cortex®-A7 with single or dual-core MPU subsystem combined with an Arm®

Cortex®-M4 CPU.

STM32MP15x devices can be configured in various low-power modes in order to reduce power consumption when necessary.

This application note explains the various low-power modes of the STM32MP15x lines devices, and how to configure and exitfrom them. This document also presents some guidance to be considered when using low-power modes at system level, andwhen using an external STPMIC1x power regulator component.

Table 1. Applicable products

Type Product lines

STM32MP15x STM32MP151, STM32MP153, STM32MP157

In this document, "STM32MP15x", refers specifically to STM32MP151, STM32MP153 and STM32MP157 lines devices.

For further information on STM32MP15x lines devices, refer to the following documents and deliverables available onwww.st.com.• STM32MP1 Series reference manuals (see Table 2. STM32MP15x lines configuration for details)• STM32MP1 Series datasheets• STPMIC1x datasheet• Getting started with STM32MP1 Series hardware development (AN5031)• STM32MP1 Series and STPMIC1x hardware and software integration (AN5089)• STM32CubeMP1 package• STM32MP1 Series embedded software

STM32MP15x lines using low-power modes

AN5109

Application note

AN5109 - Rev 4 - November 2020For further information contact your local STMicroelectronics sales office.

www.st.com

http://www.st.com

http://www.st.com

1 Overview

This application note is applicable to all the devices of the STM32MP15x lines. The table below describes theirmain characteristics.Depending on the device’s part number, the system includes a Cortex-M4 and either a single-core or a dual-coreCortex-A7. In this document, the Cortex-A7 is called MPU and the Cortex-M4 is called MCU.The full featured system (see the table below) is partitioned in:• One MPU subsystem: dual Cortex-A7 with L2 cache• One MCU subsystem: Cortex-M4 with associated peripherals clocked according to CPU activity

The present document assumes a full featured device (for example STM32MP157).

Table 2. STM32MP15x lines configuration

Lines Referencemanual

Cortex-A7configuration Cortex-M4 GPU DSI FDCAN

STM32MP151 RM0441 Single-core Yes No No No

STM32MP153 RM0442 Dual-core Yes No No Yes

STM32MP157 RM0436 Dual-core Yes Yes Yes Yes

In this document MCU subsystems are sometimes referred to as “MCU” and MPU subsystems as “MPU” tofacilitate the reading of the document.This document applies to Arm®-based devices.

Note: Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

AN5109Overview

AN5109 - Rev 4 page 2/38

2 Glossary

Table 3. Glossary

Term Meaning

AHB Advanced high-performance bus

ATF Arm® trusted firmware

AVD Analog voltage detector

BKPSRAM Backup SRAM

BOR Brownout reset

BUCK Step down switched-mode power-supply converter

CSS Clock security system

DDR Double data-rate (SRAM)

DDRCTRL DDR controller

DDRPHYC DDR physical interface control

DSI Display serial interface

ETH Ethernet controller

FDCANController area network with flexible data-rate.

Could also support time triggered CAN (TT)

GPIO General purpose input output

GPU Graphic processing unit

HAL Hardware abstraction layer

HDP Hardware debug port

IRQ Interrupt request

IWDG Independent watchdog

LDO Low dropout regulator

LpDDR Low power DDR

LSE Low-speed external quartz oscillator

LSI Low-speed internal oscillator

MCU Microcontroller

MLAHB Multi layer AHB / AHB based interconnect

MPU Microprocessor

PLL Phase locked loop

PVD Programmable voltage detector

PWR Power control block

QSPI Quad data lanes serial peripheral interface

RCC Reset and clock control

RETRAM Retention memory

RTC Real time clock

SDMMCSecure digital and MultiMedia card interface.

Supports SD, MMC, eMMC and SDIO protocols

SMP Symmetric multiprocessing

AN5109Glossary

AN5109 - Rev 4 page 3/38

Term Meaning

SPL Secondary program loader

SRAM Static random access memory

STPMIC1x Power management integrated circuit. External circuit that provides various platform power supplieswith large controllability through signals and serial interface

SYSRAM System SRAM

SW Software

TEMP Temperature sensor

TEMPH-L Temperature sensor high-low monitoring

USART Universal synchronous asynchronous receiver transmitter

USB OTGUniversal Serial Bus (USB) on-the-go (OTG).

A standard USB interface able to become host or device

VBATH-L VBAT high-low monitoring

WFE Wait for event

WFI Wait for interrupt

AN5109Glossary

AN5109 - Rev 4 page 4/38

3 Power management concept

This section describes the STM32MP15x lines high-level power management concept.Refer to the corresponding reference manual for more details (see Table 2. STM32MP15x lines configuration).

3.1 STM32MP15x lines system architecture

The STM32MP15x devices are based on a main dual-core MPU subsystem and a MCU subsystem. The multiplecore architecture requires specific power modes both at system and at individual MPU and MCU subsystem level.Internal digital logic is supplied externally in STM32MP15x lines devices, this is different than most STM32MCUs which have an internal LDO (low dropout regulator) for such purpose. This key difference results in adifferent power-supply management for the STM32MP15x devices which require the use of external signalsand/or programming of the external regulator to control the desired voltage supplies.The power management features are spread between the RCC (reset and clock control) and the PWR (power)blocks of the STM32MP15x lines device.• The RCC block ensures the clock tree handling (PLLs, muxes, dividers, clock gating) and the resets (local

resets of the peripherals, Cortex-A7 reset, Cortex-M4 reset, platform reset)• The RCC block permits to select the power mode based on the respective power states of the MCU and

MPU subsystems• The PWR block is responsible for low-power entry/exit. It drives the control pins (PWR_ON, PWR_LP) to the

external regulator based on the power mode.

The figure below shows the STM32MP15x lines high-level system architecture.

Figure 1. STM32MP15x lines high-level system architecture

Cortex -M4(coprocessor)

STM32MP15xExternal power regulator

PWR_ON, PWR_LP control pins

supplies

External (Lp)DDR

(master)Dual Cortex-A7

MCU power state

MPU power state

PWR managerClock manager

3.2 System supplies (VDD and VDDCORE)

The STM32MP15x lines devices require many power supplies that are detailed in the corresponding datasheetand reference manual (see Table 2. STM32MP15x lines configuration). Among those power supplies, VDD andVDDCORE play a key role in the low-power mode configuration.• VDD power supply input for IOs and system analog such as reset, power management oscillators and PLLs.• VDDCORE digital core domain supply, dependent on VDD supply. VDD shall be present before VDDCORE.

The various power pins of the STM32MP15x devices can be supplied either by some external discrete suppliesor by using STPMIC1x as detailed in the reference design section of the application note Getting started withSTM32MP1 Series hardware development (AN5031).

AN5109Power management concept

AN5109 - Rev 4 page 5/38

The STPMIC1x has several part numbers. Find below the part numbers appropriate for the STM32MP15xdevices:• STPMIC1APQR for application using VDD = 3.3 V• STPMIC1BPQR for application using VDD = 1.8 V

Figure 2. Discrete supplies example 3.3V I/Os with DDR3L

Note: Several types of DDR are supported (LpDDR2, LpDDR3, DDR3), this impacts the low-power modemanagement. Refer to Figure 7. Available power state transitions.

AN5109System supplies (VDD and VDDCORE)

AN5109 - Rev 4 page 6/38

Figure 3. STPMIC1x example 3.3 V I/Os with DDR3L

The STPMIC1x provides the power distribution. It is driven by I²C and by control signals coming from theSTM32MP15x device. Control is done by the Cortex-A7 MPU subsystem core. The main benefit of using theSTPMIC1x versus using discrete regulator supplies is to have an integrated, smaller and cheaper solution. Referto application note STM32MP15x and STPMIC1x HW and SW integration (AN5089) for more details.

AN5109System supplies (VDD and VDDCORE)

AN5109 - Rev 4 page 7/38

4 Operating modes

This section describes the STM32MP15x lines various power modes and the ways of activating them.

4.1 Operating modes description

The operating modes allow the control of the clock distribution to the different system parts and the control ofthe power supplies of the system. The system operation mode is driven by the MPU subsystem and the MCUsubsystem.The power management controls the VDDCORE supply in accordance with the system operating modes.The table below presents the operating modes available for the system and for the MPU and MCU subsystems.The power mode at system level is dependent on the power modes at each subsystem level (MPU and MCU).

Table 4. Power modes

- Power mode Description Notes

System

Run VDDCORE power on, clock on -

Stop VDDCORE power on, clock off -

LP-Stop VDDCORE power on, clock off (1)

LPLV-Stop VDDCORE reduced power level and supply load, clockoff

(1)(2)

Standby VDDCORE power off, clock off -

VBAT VSW is supplied by battery, VDDCORE is off, RTC is stillactive clocked by LSE crystal

(3)

Power off All power supplies off -

MPU / MCU

CRun VDDCORE power on, clock on -

CSleep VDDCORE power on, CPU clock off, peripheral clockon/off

(4)

CStop VDDCORE power on, CPU subsystem clock off -

MPU CStandby VDDCORE power on or off, clock off (5)

1. There is no difference in the output control pins PWR_ON and PWR_LP between LP-Stop and LPLVStop (seeSection 4.3 External control signals PWR_ON, PWR_LP pins). While both LP-Stop and LPLV-Stop can be activatedusing STPMIC1x through programming of its internal register prior entering the targeted low-power mode (refer toSection 4.3.1 Using STPMIC1x power regulator), both modes may not be available using other external power regulators.

2. The main difference with Stop mode is that PWR_ON output signal is toggling to 0 when using STPMIC1x external powerregulator, enabling the possibility to take actions like powering off DDR termination resistance power supply.

3. To retain the content of the VSW domain (RTC, backup registers, backup RAM and retention RAM) when VDD is turned off,the VBAT pin can be connected to an optional standby voltage supplied from a battery or from another source.

4. The MCU/MPU subsystems allocated peripheral(s) clock operate according to RCC PERxLPEN. When the MPU entersCSleep with WFE (wait for event), the MPU subsystem allocated peripheral(s) clock operate as in MPU CRun mode,irrespective of RCC PERxLPEN.

5. In CStandby mode, the MPU is in power off only if the system mode is in Standby (when MCU is in CStop with PDDS=1).Refer to Table 6. Power-system mode versus sub-system mode summary.

The choice of which low-power mode to use is dependent on power saving target and it must be chosenaccording to which wakeup interrupts are needed/available in the chosen low-power mode and the expectedwakeup time duration.User should always make sure that the chosen low-power mode is consistent with the available wakeup sources.For instance LPLV-Stop or Standby modes have very limited wakeup source capabilities.

AN5109Operating modes

AN5109 - Rev 4 page 8/38

Also the wakeup duration is longer if power supplies voltage have been reduced or switched off by reducingVDDCORE, switching off DDR resistance termination supply with DDR in self refresh or switching off the full DDR(which may require reloading the firmware from the Flash memory). The system’s low-power mode wakeupcapabilities are presented in the below table.

Table 5. System’s low-power mode wakeup capabilities

System power mode Wakeup sources

Stop/LP-Stop DBG, PVD, AVD, USBH, OTG, CEC, ETH, MDIOS, USARTx, I2Cx, SPIx TEMP, LPTIMx,GPIOs

LPLV-Stop PVD, AVD, TEMP, GPIOs

Standby Six GPIO pins: PA0, PA2, PC1, PC13, PI8, PI11

All modes BOR, VBATH/VBATL, TEMPH/TEMPL, LSE CSS, RTC/auto wakeup, tamper pins, IWDGx

4.2 Low-power mode control

4.2.1 Low-power mode control registersThe control register bits presented below are related to the low-power modes (for description of low-power modessee Section 4 Operating modes).

PDDS bit in register PWR MPU control register (PWR_MPUCR)

0: Keeps Stop mode when MPU enters to CStop.1: Allows Standby mode when MPU enters to CStop.When CSTBYDIS = 0 allows MPU to enter CStandby mode.

PDDS bit in register PWR MCU control register (PWR_MCUCR)

0: Keeps Stop mode when MCU enters to CStop.1: Allows Standby mode when MCU enters to CStop.

CSTBYDIS bit in register PWR MPU control register (PWR_MPUCR)

0: MPU CStandby mode enabled.1: MPU CStandby mode disabled.

Both MPU and MCU can access the PWR_MPUCR and PWR_MCUCR. However the PWR_MPUCR can be setin secure mode (Linux case) to only allow MPU write access.MCU can write the PWR_MCUCR register bits using HAL_PWR_EnterStandbyMode() function.• The HAL function HAL_PWR_EnterStandbyMode() sets the MCU PDDS bit to '1' and enters the CStop

mode for the MCU subsystem through a WFI (wait for interrupt). The Standby mode is entered only once theMPU subsystem enters the CStop mode with PDDS=1 & CSTBYDIS=1 or the CStandby mode (see Section4.4: Low-power mode entry sequence)

AN5109Low-power mode control

AN5109 - Rev 4 page 9/38

The tables below detail the possible combinations of the power modes between system and MPU/MCUsubsystems and the system's low-power modes summary respectively.

Table 6. Power-system mode versus sub-system mode summary

-

MPU(1)

CRun CSleepCStop

(PDDS = 0)

CStop

(PDDS = 1

CSTBYDIS=1)

CStandby(2)

MCU

CRun Run Run Run Run Run(3)

CSleep Run Run Run Run Run(3)

CStop

(PDDS = 0)Run Run

Stop

LP-Stop

LPLV-Stop

Stop

LP-Stop

LPLV-Stop

Stop(3)

LP-Stop

LPLV-Stop

CStop

(PDDS = 1)Run Run

Stop

LP-Stop

LPLV-Stop

Standby(4) Standby(4)

1. Refer to Section 4.6.7 Exit from MPU CStop and CStandby for additional details on CStop and CStandby.2. CStandby mode on MPU is not supported in the STM32MPU OpenSTLinux Distributions. System standby is reached with

MPU in CStop mode (PDDS=1, CSTBYDIS=1).3. When exit from MPU CStandby with System in Run, Stop, LP-Stop or LPLV-Stop, program execution restarts with a local

MPU reset. This 'reboot' can affect MCU operation due to possible re-initialization of some peripheral registers by theBootROM when reloading MPU initialization code from external Flash.

4. When exit from MPU CStandby or CStop (PDDS=1, CSTBYDIS=1) with System in Standby, program execution restarts inthe same way as after a power on reset (option bytes loading, reset vector fetched, or other).

Table 7. System low-power modes summary

System MPU DDR(1) MCU Sys-oscillators(2) hclk4 PWR_LPPWR_ON

LPCFG =0

LPCFG =1

Run

CRun orCsleep

Active / Autorefresh CRun

orCSleep On On

1

1

1

CStop orCStandby Self refresh

CRun orCSleep

Active / Autorefresh CStop

Stop

(LPDS = 0)(3)

CStop orCStandby Self refresh CStop On/Off(4)

Off

LP-Stop

LPLV-Stop(3)

(LPDS = 1)0(5) 0(5)

Standby

CStandby or(CStop andMPU PDDS

= 1 and MPUCSTBYDIS =

1)

Off / Selfrefresh

CStopand

MCUPDDS =

1

Off 0(6) 0(6) 0(6)

1. The DDR operation state is only presented for information. For example, the DDR may be Off when the MPU is in CRun likewhen executing from BootROM.

AN5109Low-power mode control

AN5109 - Rev 4 page 10/38

2. The sys-oscillators are the HSI, HSE or CSI oscillators configured ON in RCC.3. At least 1 PDDS bit (MCU or MPU) selects Stop (PDDS = 0).4. When the system oscillator HSI, HSE or CSI is used, the state is controlled by the respective xxxKERON (HSIKERON,

HSEKERON or CSIKERON bits present in the RCC oscillator clock enable set register (RCC_OCENSETR) and the RCCoscillator clock enable clear register (RCC_OCENCLRR)), else the system oscillator is off.

5. Settings in PWR control register 3 (PWR_CR3) bits POPL have no impact on the LP-Stop and LPLV-Stop mode PWR_ONand PWR_LP pulse low time.

6. A guaranteed minimum PWR_ON and PWR_LP pulse low time can be defined in PWR control register 3 (PWR_CR3) bitsPOPL.

4.3 External control signals PWR_ON, PWR_LP pins

The two output pins PWR_ON and PWR_LP are related to the VDDCORE supply. They are used by externalcomponent/regulator to identify which voltage level should be applied on VDDCORE. Refer to Section 4 Operatingmodes for more details on PWR_ON, PWR_LP configuration.• PWR_ON: VDDCORE supply request

It is automatically generated by the hardware depending on the state of the STM32MP15x device and on thevalue of LPCFG (PWR_ON pin configuration) bit in PWR control register 1 (PWR_CR1).

• PWR_LP: VDDCORE low-power mode control (active low)It is automatically generated by the hardware depending on the state of the STM32MP15x device andthe value of LPDS (low voltage deepsleep LPLV-Stop mode selection) bit on PWR control register 1(PWR_CR1).

The table below indicates the PWR_ON, PWR_LP output pin values depending on the various configuration ofpower modes and LPDS, LPCFG, LVDS bits.• LPDS is PWR control register 1 (PWR_CR1) bit 0• LPCFG is PWR control register 1 (PWR_CR1) bit 1• LVDS is PWR control register 1 (PWR_CR1) bit 2

The table also shows the differences in the usage of pins PWR_ON and PWR_LP depending if the STM32MP15xdevice is to be used with STPMIC1x or with other external power supply components.The power modes are detailed in the PWR section of the corresponding reference manual (seeTable 2. STM32MP15x lines configuration).

AN5109External control signals PWR_ON, PWR_LP pins

AN5109 - Rev 4 page 11/38

Table 8. PRW_ON, PWR_LP levels according power modes, LPDS, LVDS and LPCFG bits

STM32MP15xstate LPDS/LVDS bits LPCFG bit PWR_ON PWR_LP VDDCORE

Startup (until VDDreaches PORthreshold level)

X/X X 0 0 Off

Run mode X/X X 1 1 On

Stop mode 0/X X 1 1 On

LP-Stop mode 1/00 1 0

On1(1) 0(2) 0(2)

LPLV-Stop mode 1/10(3) 1 0

On(4)

1(1) 0(2) 0(2)

Standby mode 0/0 X 0(2) 0(2) Off

VBAT mode (VDDpowered down) X/X X HiZ HiZ Off

1. Configuration used with STPMIC1x PWRCTRL pin connected to PWR_ON.2. There is no difference between LP-Stop, LPLV-Stop and Standby mode on the PWR_ON, PWR_LP output values '00' with

LPCFG bit=1.3. Depending on the external power regulator that is used, this configuration might not be available (not possible to reduce the

power supply level).4. VDDCORE supply level and power load can be decreased.

The figure below illustrates the relation between the system states and the PWR_ON, PWR_LP output pins forregulator control for STM32MP15x lines devices.

Figure 4. Power states and external regulator control

LP-StopLPLV-Stop

RunMAIN

PWR_ON = 1, PWR_LP = 1

StandbyPOWER DOWN


Standby mode Wakeup

reset

StopMAIN


LOW POWERPWR_ON = 1 when LPCFG = 0,PWR_ON = 0 when LPCFG = 1,

PWR_LP = 0

Stop mode


AN5109 - Rev 4 page 12/38

4.3.1 Using STPMIC1x power regulatorThe figure below shows the main differences at system level when using the STPMIC1x power regulator.

Figure 5. STM32MP15x lines high-level system architecture when using STPMIC1x

Cortex-M4(coprocessor)

Shared by A7S STM32MP15x

STPMIC1x

PWR_ON

supplies

External (Lp)DDR

(master)Dual Cortex-A7

PWR manager MCU power state

MPU power state

PWRCTRL

PONKEY_NRST_N NRST

Clock managerSDASCL

I2C ctrl

When using STPMIC1x power regulator, only PWR_ON output control pin from STM32MP15x is needed for thecontrol of the STPMIC1x power modes (through PWRCTRL pin). In that case, the user shall set the LPCFG bit ofthe PWR_CR1 register to '1'.Table 8. PRW_ON, PWR_LP levels according power modes, LPDS, LVDS and LPCFG bits highlights on the graycells that there is no difference between LP-Stop, LPLV-Stop and Standby mode on the PWR_ON, PWR_LPoutput values '00' with LPCFG bit=1.The STPMIC1x differentiates between those LP-Stop, LPLV-Stop and Standby low-power modes and apply thecorrect VDDCORE value thanks to STPMIC1x internal registers. Those registers programming is done via the I2Cinterface and not through the PWR_ON, PWR_LP pins values.When using STM32MPU OpenSTLinux Distributions, this programming is handled by the first stage bootloader(TF-A or OPTEE). Hence before entering LP-Stop, LPLV-Stop or Standby mode the application shall configure theSTPMIC1x internal registers to the desired system power supplies level (like VDDCORE, VDD_DDR, and others).When entering LP-Stop mode, despite the fact that VDDCORE level is not decreased (only in LPLV-Stop), it is stillpossible to program the STPMIC1x so that other power supplies are shut down if not needed (for example thepower supply of the DDR termination resistances).The STPMIC1x includes two 8-bit registers for each of the BUCK (1,2,3,4) and LDO (1,2,3,4,5,6):• A BUCKx/LDOx control register (HP mode) that stores the expected output voltage value during Run mode.• A BUCKx/LDOx control register (LP mode) that stores the expected output voltage during low-power mode.

Each of those registers have the following structure:

7 6 5 4 3 2 1 0

output value <5:0> hplp ena

Bits 7:2: output value: the output value on 6 bits corresponds to a specified voltage value (refer toSTPMIC1x datasheet).Bit 1: hplp: forces high/low load capability (allows more/less load on STPMIC1x output).

0: High load capability1: Low load capability

Note: hplp bit is applicable only for BUCKx registers, not for LDOx.Bits 0: ena: enable bit.


AN5109 - Rev 4 page 13/38

0: BUCK/LDO disabled1: BUCK/LDO enabled

The following tables show how the STPMIC1x could be programmed in Run mode and how STPMIC1x couldbe programmed before entering LP-Stop, LPLV-Stop and Standby modes respectively. Both tables list all powersupplies and not only the VDDCORE one and the settings used on them are in line with the example presented onSection 3.2 .

Table 9. STPMIC1x (HP mode) programming for Run mode

Supply name Control register (HP mode) /@ Run

VDDCORE BUCK1 / 0x20 0x61 (1.2 V)

VDD_DDR BUCK2 / 0x21 0x79 (1.35 V)

VDD BUCK3 / 0x22 0xD9 (3.3 V)

3V3 BUCK4 / 0x23 0xD9 (3.3V)

VREF_DDR VREFDDR / 0x24 0x1

VDDA LDO1 / 0x2A 0x51 (2.9 V)

VDD_USB LDO4 / 0x28 0x1 (3.3 V)

VDD_SD LDO5 / 0x29 0x51 (2.9 V)

VTT LDO3 / 0x27 0x7D (0.675 V)(1)

1. LDO3 output value is BUCK2 output /2 = 0.675 V for DDR3 use case.

Table 10. STPMIC1x (LP mode) programming for LP-Stop LPLV-Stop and Standby mode

Supply name Control register(LP mode) /@ LP-Stop LPLV-Stop Standby with

DDR SRStandby w/o DDR

SR

VDDCORE BUCK1 / 0x30 0x61 (1.2 V) 0x33 (0.9 V) 0x30 (off)

VDD_DDR BUCK2 / 0x31 0x79 (1.35 V) 0x7A (off)

VDD BUCK3 / 0x32 0xD9 (3.3 V)

3V3 BUCK4 / 0x33 0xD9 (3.3 V) 0xD8 (off)

VREF_DDR VREFDDR / 0x34 0x1 0x0 (off)

VDDA LDO1 / 0x3A 0x51 (2.9 V) 0x50 (off)

VDD_USB LDO4 / 0x38 0x1 (3.3 V) 0x0 (off)

VDD_SD LDO5 / 0x39 0x51 (2.9 V) 0x50 (off)

VTT LDO3 / 0x37 0x7C (off)

Note: Setting bit0 to '0' disables the corresponding BUCK/LDO, and its value is set to “off”.Example: VDDA = 2.9 V (0x51) when bit0='1' and is 'off' (0x50) when bit0='0'.Application note "STM32MP15x and STPMIC1x HW and SW integration” (AN5089) provides more details on howto use STPMIC1x.The NRST pin of the STM32MP15x lines can be activated by the STPMIC1x RST_N pin when the user is settingSTPMIC1x PONKEY_N pin to '0', hence resetting both the STPMIC1x and the STM32MP15x devices.


AN5109 - Rev 4 page 14/38

4.3.2 Using other external power suppliesWhen using external power supplies other than STPMIC1x , the use of both PWR_ON and PWR_LP outputcontrol pins is possible in order to control external power supply if low-power modes below Stop mode (such asLP-Stop, LPLV-Stop and Standby) are required by the application.When the STM32MP15x device goes to LP-Stop or LPLV-Stop mode, PWR_ON shall be set to '1'; when they areon Standby PWR_ON shall be set to '0'. To activate this usage, the user must set the LPCFG bit to '0'.

4.4 Low-power mode entry sequence

The STM32MP15x lines have dedicated power-modes at subsystems level (MPU, MCU) and at system level (seeSection 4 Operating modes). This section details how to enter those power modes at subsystem and at systemlevel.

MPU subsystem

The MPU subsystem’s low-power modes (CSleep, CStop and CStandby) are entered by the MPU when executingthe WFI (wait for interrupt) or WFE (wait for event) instructions. WFE being available only when enteringCSleep. In order for the MPU to enter the subsystem’s low-power modes, the RCC and PWR registers mustbe already correctly programmed (refer to Section 5.1 Peripheral assignment and allocation). When usingSTM32MPU OpenSTLinux Distributions those mechanisms are handled by the first stage bootloader (refer toSection 4.5 Power management under Linux).

MCU subsystem

MCU subsystem’s low-power modes (CSleep and CStop) are entered by the MCU when executing the WFI (waitfor interrupt), or WFE (wait for event) instructions, or when the SLEEPONEXIT bit in the Cortex®-M4 SystemControl register is set on Return from ISR.When using STM32CubeMP1 package on the MCU, several functions are defined for low-power modes. Thetable below describes each function defined in STM32CubeMP1 package according to its dedicated low-powermode.

Table 11. Low-power modes functions used on MCU within STM32CubeMP1 package

Low-powermode Function Argument Description

CSleep

HAL_PWR_EnterSLEEPMode

PWR_MAINREGULATOR_ON

PWR_LOWPOWERREGULATOR_ON

The regulator parameter is not used forSTM32MP15x lines devices and it is keptas parameter just to maintain compatibilitywith the lower-power families (like STM32LSeries)

PWR_SLEEPENTRY_WFI

PWR_SLEEPENTRY_WFESpecifies if SLEEP mode is entered withWFI or WFE instruction

HAL_PWR_EnableSleepOnExit None

Set SLEEPONEXIT bit of SCR register.

When this bit is set, the processor reentersSLEEP mode when an interruption handlingis over

HAL_PWR_DisableSleepOnExit None Clears SLEEPONEXIT bit of SCR register

CStop,

PDDS=0HAL_PWR_EnterStopMode

PWR_MAINREGULATOR_ON

PWR_LOWPOWERREGULATOR_ON

The regulator parameter is not used forSTM32MP15x devices and it is kept asparameter just to maintain compatibilitywith the lower-power families (like STM32LSeries)

PWR_STOPENTRY_WFI

PWR_STOPENTRY_WFESpecifies if Stop mode is entered with WFIor WFE instruction

AN5109Low-power mode entry sequence

AN5109 - Rev 4 page 15/38

Low-powermode Function Argument Description

CStop,

PDDS=1HAL_PWR_EnterStandbyMode None

This function makes the MCU to go toCStop (WFI) and puts the bit MCU PDDS= 1 allowing the system to go to Standbywhen the MPU is put in CStandby or in(CStop and MPU PDDS = 1 and MPUCSTBYDIS = 1)

System

The system may enter Stop, LP-Stop, LPLV-Stop or Standby when all the EXTI wakeup sources are cleared andwhen both the MPU and MCU are in CStop or CStandby mode.The system enters the Standby mode (power off, clock off) only when the MPU is in CStandby or in CStop withMPU PDDS=1 and MPU CSTBYDIS =1 and when MCU is in CStop with MCU PDDS = 1.Standby mode entering must be carefully managed by the MCU coprocessor firmware: allowed via MCU “CStopwith PDDS=1” only if it is able to manage the Standby state, so at least if it can lose the MCU SRAM contentduring this period.It is possible to switch off the MCU clock and peripherals allocated to the MCU (equivalent to a CStop mode) byusing the HOLD_BOOT feature. This feature is controlled by the MPU via the BOOT_MCU bit located into theRCC global control register (RCC_MP_GCR). It allows the system to be put in Stop, LPLV-Stop or Standby mode.This feature is activated after a reset of the MCU (when MPU is setting MCURST bit of RCC global reset controlset register (RCC_MP_GRSTCSETR)).It is also possible to only run code on MPU (MCU in CStop equivalent mode) simply by having MPU not loadingany code on MCU side, hence by default when starting the system the MCU is kept inactive (except when bootmode BOOT[2:0] = 0b100).

Note: When entering LPLV-Stop, if VDDQ_DDR is not shutdown, to avoid overconsumption on VDDQ_DDR, the DDRmemory must be put in SelfRefresh and DDR PHY must be set in retention mode (setting bit DDRRETEN: DDRretention enable of PWR control register 3 (PWR_CR3) register).

AN5109Low-power mode entry sequence

AN5109 - Rev 4 page 16/38

4.5 Power management under Linux

Linux power management is done through the software framework shown in the figure below.

Figure 6. Linux power management software framework

Secure monitor

Kernel

Software component Hardware component

Device drivers Suspend driver PM driver

genPD PSCI library

PSCI library Clock driverPmic driverI2C driver

PWR RCCHW IPsPMIC

The Linux suspend framework is used to enter the low power modes. It relies on:• genPD (generic power-domain) framework which allows the definition of power domains and allow the

mapping of IPs on those power domains• PSCI standard to perform the low-level power management process

Additional information can be found on the Power overview wiki article.The secure monitor regulator framework is used to configure the external power-regulator voltages for eachpower mode and it relies on an ST STPMIC1x (PMIC) driver and an I2C driver.

4.5.1 Linux power commands mapping to STM32MP15x lines power modesWhen using Linux operating system, power mode commands are predefined and this section explains how theyare mapped to the STM32MP15x lines hardware low-power modes. It also explains the low-power mode controlusing the MCU coprocessor.Under Linux, the user can ask the system to enter into low-power mode with the following direct input command:To enter in Standby mode with DDR off:

'shutdown -h 0'

or to reach any low-power mode among Stop variants and Standby, with DDR in Self-refresh:

echo 'mem' > /sys/power/state

The 'disk', 'freeze' and 'standby' commands are not supported on STM32MP15x lines.

The Cortex®-A7 is put in WFI (wait for interrupt) when entering a low-power mode. However, the system onlyreaches the targeted low-power mode after the MCU subsystem has been previously configured in theexpected low-power mode.For instance the Linux 'mem' command puts the system in Standby mode only if the MCU has been previously setto CStop mode allowing Standby (for example using HAL_PWR_EnterStandbyMode() function).The list of available wakeup sources is not the same for all low-power modes, so a software mechanism isimplemented through the genPD framework to ensure that the low-power mode and the activated wakeup sourceare consistent.

AN5109Power management under Linux

AN5109 - Rev 4 page 17/38

The strategy is to allow the MPU to enter the deepest low-power mode available according to the currentlyactivated wakeup source(s).

Example 1

The user activates the UART4 as wakeup source. The UART is powered by VDDCORE, so all low-power modesthat are modifying VDDCORE are automatically forbidden.Then, calling echo mem > /sys/power/state results in the MPU entering CStop allowing Stop or LP-Stop.

Example 2

The user selects the RTC as wake-up source. The RTC is always powered, whatever the low-power mode status.Then, calling echo mem > /sys/power/state results in the MPU entering CStop allowing Standby.This mechanism ensures that a blocking situation such as activating UART4 as wakeup source and requestingSoC Standby can never happen.

The system’s power mode is the result of both MPU and MCU power states.The table below lists the deepest possible power mode according to wakeup source groups and lists theequivalence between Linux standard low-power modes and STM32MP15x lines system low-power modes,including the external (Lp)DDR power state (on, off, self refresh (SR)) as it is implemented in the STM32MPUOpenSTLinux Distributions BSP provided environment.Systems using 32-bit DDR3 interface most likely use external resistance termination on address and commandsignals. Those systems shall be powered by a resistance termination power supply (VTT) that can be a significantcontributor to the overall system consumption during low-power modes.Hence, by using STPMIC1x, it is possible to switch off this power supply when PWR_ON signals are pulled down(LP-Stop, LPLV-Stop, Standby) and it is preferred to use LP-Stop rather than Stop mode, because LP-Stop modedoes not toggle PWR_ON in such use case.

Table 12. Deepest power mode per wakeup source group and equivalence between Linux andSTM32MP15x lines

Wakeupsource

Linuxcommand

STM32MP15xsystem

deepest powermode

SystemDDR

Linuxkernelstate

Powerconsuming

Wakeuptime

Comment / Applicationguideline

Group 1:USB,CEC, ETH,USART,I²C, SPI,LPTIM

"mem" Stop or LP-StopSR

(VTT off)"Suspend-

to-ram" Medium Medium

LP-Stop: driving externalPWR_LP/PWR_ON permitsto design custom strategy

for external regulator. Typicalapplication is to switch-offDDR3 termination supply

(VTT) in DDR3 32 bit design

Group 2:PVD, AVD,IWDG,GPIO

"mem" LPLV-StopSR

(VTT off)"Suspend-

to-ram" Low Medium

LPLV-Stop: save powerthanks to power retention.

Can be suitable forapplications with aggressive

power constraints andtolerant with limitations ofwakeup source (refer to

Table 5. System’s low-powermode wakeup capabilities )

Group3:BOR,Vbat mon,Temp mon,LSE CSS,RTC,TAMP,Wakeuppins

"mem" Standby SR "Suspend-to-ram" Low Medium

Standby saves more powerat the expense of wakeup

time

"shutdown" Standby or Off/VBAT Off Shutdown Very low High

Wakeup sequence andapplicative impact guide thechoice between Standby and

Off


AN5109 - Rev 4 page 18/38

Note: This table assumes that Cortex®-M4 is in CStop mode for all expected Stop, LP-Stop, LPLV-Stop system powermodes and in CStop with PDDS=1 for Standby system power mode.The following figure shows the power state transitions that are available in the system. The same definitions foreach wakeup source group used in the table above are considered in this figure. Group 3 wakeup sources arealso functional with Group 2 and Group 1 sources. Group 2 is also compatible with Group 1.If several wakeup sources are activated in different groups, the low-power mode is chosen by respecting thehierarchy stated in the table above. the choice between Stop or LP-Stop is done through settings in the tree of thesecure monitor device tree.

Figure 7. Available power state transitions

Cortex-M4

(Lp)DDR VTT

Cortex-A7Cortex-A7

Cortex-M4

(Lp)DDR VTT

Cortex-A7Cortex-A7

Cortex-A7Cortex-A7

Cortex-M4

(Lp)DDR VTT

Cortex-A7Cortex-A7

Cortex-M4

(Lp)DDR VTT

Cortex-M4

VTT

Cortex-A7Cortex-A7

(Lp)DDR

Cortex-A7Cortex-A7

Cortex-M4

(Lp)DDR VTT

Power off / Standby Run

Run

Standby

LPLV-Stop

Stop / LP-Stop

Linux cmd = shutdown

Power_on_reset

Linux cmd = memgenPD

Group 1WU source

Group 2WU source

Group 3WU source

Do not care

Supply off

Supply on and clock on

Supply on and clock off

Supply retention and clock off

4.5.2 Controlling MCU power modes under LinuxThere are two possible ways to have the MCU control the power modes under Linux; either using “rpmsg” throughinter process communication (IPC) or using “independent clusters”.

“rpmsg” through inter process communication (IPC)

The MPU can be seen as the master and the MCU as a coprocessor. Communication between both processorsis done using rpmsg. A Linux kernel is running on the dual core MPU in SMP mode, and a free-rtos is running onthe MCU.Some IPs are shared between the processors and a protection is set in place to ensure the registers consistency.When a core needs to access an IP which is under the responsibility of the other core, it sends a request throughrpmsg to get the action done.


AN5109 - Rev 4 page 19/38

Regarding entering/exiting into/from Standby state, before MPU “CStop with PDDS=1 CSTBYDIS=1” state, Linuxnotifies the MCU that the IPC link is suspended. When waking up from system Standby state with MCU_BEN, theMCU firmware does not communicate with Linux via the IPC. It is only able to send an event (SEV instruction) tothe MPU when it needs to wake it up. Then, Linux establishes again the IPC link with the MCU.

Independent clusters

The MCU may manage its low-power mode states in its SW code (no need for rpmsg from MPU).

4.6 Low-power mode exit sequence

Exit from low-power mode (except Standby) can be triggered by interrupt or event depending on how thelow-power mode was entered (WFI or WFE). Exit from Standby on MPU can only be triggered by an applicationreset (like NRST, IWDG), WKUPx pins event or an RTC event.On exit from low-power mode, it is possible to wake up only MPU, only MCU or both.• On exit from low-power mode (except Standby) waking up of MPU, MCU or both depends on how the IRQ

detection was programmed (visible on MPU, MCU or both).• On exit from Standby, it is done by setting the two bits MPU_BEN and MCU_BEN in RCC boot control

register (RCC_MP_BOOTCR). This configuration is used by the BootROM during the wakeup from Standby.The BootROM then wakesup MPU, MCU or both.

Note: When using STM32MPU OpenSTLinux Distributions, the system always boots only one subsystem: we assumethat MCU_BEN and MPU_BEN are exclusive to avoid race conditions that may occur during a parallel start up ofboth subsystems.• As a consequence, the MCU should be able to interpret some wake up sources that target the MPU

subsystem. For instance, if the wake up is due to an RTC alarm (expected by Linux) then the MCU shouldwake up the MPU.

When the STM32MP15x devices exit from low-power modes, it is important to make sure all external regulatorsoutput voltage are setup to the appropriate level and stable before the Run mode can be applied.

4.6.1 Exit from system power-resetOn system power-reset, the STM32MP15x device monitors the VDD until it reaches its specified VBOR threshold.Also, the STM32MP15x device monitors VDDCORE until it reaches the minimum voltage detector threshold(VPVDCORE_0) after which it is expected that the VDDCORE is correctly established before the tVDDCORETEMPOdelay when the internal STM32MP15x device reset signal is deactivated.In order to find the value of tVDDCORETEMPO, refer to the table “Embedded reset and Power Control blockcharacteristics” in the STM32MP15x datasheet (tVDDCORETEMPO minimum value is 200 us). It is expected that theexternal Flash power supply is ready before STM32MP15x device enters Run mode and reads data from Flash toboot.• When using STPMIC1x, this is automatically handled since the STPMIC1x does not release the

STM32MP15x device NRST pin until all supplies are at their expected value.• When using a discrete regulator component, the design should make sure those constraints are correctly

handled.

AN5109Low-power mode exit sequence

AN5109 - Rev 4 page 20/38

Figure 8. Wakeup sequence from system reset

System power reset

tVDDCORETEMPO

Run modeAccess to external Flash or other

Internal reset

VDDCORE

VPVDCORE_0

VDDCORE Run mode min value

Flash supply

Flash supply Run mode min value

4.6.2 Exit from Stop modeOn exit from Stop mode, the voltages are not changed so there is no issue. However, note that while the PLL1and PLL2 settings are restored thanks to the hardware "clock restore" automatic feature, other PLL have to bereconfigured if needed. MCU is restarted on HSI clock (HSI clock frequency setting is kept similar to the settingprior entering Stop mode). This also applies for all other “Stop” modes (LP-Stop, LPLV-Stop).

4.6.3 Exit from LP-Stop modeOn exit from LP-Stop mode, VDDCORE is not changed, however other voltages at system level might have beenswitched off or reduced and may need to be set back to their Run mode value.For example the DDR3/DDR3L (x32-bit bus width) termination resistance power supply VTT can be switchedoff during LP-Stop. The STM32MP15x device waits a programmable delay (PWRLP_TEMPO) in RCC PWR_LPdelay control register (RCC_PWRLPDLYCR) to allow external regulators Run mode value recovery.• When using STPMIC1x, the exit from LP-Stop mode is notified from STM32MP15x device by the PWR_ON

pin which toggles back to 1 thus requesting changing supply level on STPMIC1x output supplies. TheSTPMIC1x ensures that the PWRLP_TEMPO can be set to a minimum value of around 1000 us (typicalcondition).– The STM32MP15x maximum output voltage rise time is given by the formula:

For BUCK output: Max {100 us; V2-V1/3.6 10-3 us} (typical)with V2: minimum Run mode voltage V1: voltage during low-power mode.

– For LDO output: ramp-up time is defined by the current limit and total amount of capacitance on LDOoutput. For 10 μF total output capacitance on LDO3, ramp-up time is 20 μs typical.

– For a VDD_USB of 3.3 V (from BUCK output), the max rise time would be 3.3/3.6 10-3 = 917 us(typical).

– Exact values in worst case condition must be computed from STPMIC1x datasheet but if wakeup timeis not critical it is recommended to use some reasonable margin (for example 5 ms).

• When using discrete external regulator components, the hardware should set the required power supplies totheir Run mode value within the PWRLP_TEMPO delay.


AN5109 - Rev 4 page 21/38

Figure 9. Wakeup sequence from LP-Stop

PWR_ON

Wake-up request

Programmable delay PWRLP_TEMPO

Regulators state Run valueLow power value

4.6.4 Exit from LPLV-Stop modeOn exit from LPLV-Stop mode, on top of power supplies changed like in LP-Stop mode, the VDDCORE voltage thathas been reduced during LPLV-Stop, needs to be set back to its Run mode value.The STM32MP15x device waits a tSEL_VDDCORETEMPO delay during which VDDCORE is expected to reach itsminimum Run mode value. After this tSEL_VDDCORETEMPO delay, the STM32MP15x device waits a programmabledelay (PWRLP_TEMPO) in RCC PWR_LP delay control register (RCC_PWRLPDLYCR) to allow other externalregulators Run mode value recovery (as for LP-Stop mode exit sequence described above).In order to find the value of tSEL_VDDCORETEMPO refer to the table “Embedded reset and power control blockcharacteristics” of the corresponding STM32MP15x device datasheet (tSEL_VDDCORETEMPO minimum value is 234us).• When using STPMIC1x, the exit from LP-Stop mode is notified from STM32MP15x by the PWR_ON

pin which toggles back to 1, thus requesting changing supply level on STPMIC1x output supplies. TheSTPMIC1x ensures that VDDCORE output supply reaches its minimum Run mode value in less thantSEL_VDDCORETEMPO delay and that PWRLP_TEMPO can be set to a minimum value defined by the sameformula provided in Section 4.6.3 Exit from LP-Stop mode.– If during LPLV-Stop VDDCORE power supply (from BUCK output) is reduced to 0.9 V then V1= 0.9 V,

V2= 1.2 V so maximum rise time is 0.3 / 3.6 10-3 = 83 us (typical). The worst condition value should becomputed from the STPMIC1x datasheet and should be less than tSEL_VDDCORETEMPO (234 us).

– Same formula to be used for other power supplies that should have rise time (in worst condition) lessthan PWRLP_TEMPO.

– If wakeup time is not critical it is recommended to use reasonable margin (for example 5 ms).• When using discrete external regulator components, the hardware should be able to set the VDDCORE supply

to its minimum Run mode value within the tSEL_VDDCORETEMPO delay and should set the other requiredpower supplies to their Run mode value within the PWRLP_TEMPO delay.

Figure 10. Wakeup sequence from LPLV-Stop

tSEL_VDDCORETEMPO

VDDCORE

VDDCORE Run mode min value

Wake-up request

VDDCORE LPLV-Stop mode value

Programmable delay PWRLP_TEMPO

PWR_ON

Regulators state Run valueLow power value

Run mode


AN5109 - Rev 4 page 22/38

4.6.5 Exit from Standby modeOn exit from Standby mode, on top of power supplies changed like in LP-Stop mode, VDDCORE voltage (that hasbeen turned Off during Standby mode) needs to be switched On and set to its Run mode value.During Standby the VDD supply is kept active and so at wakeup from Standby, the pin PWR_ON is set back to 1(part of the digital logic in the PWR controller is supplied by VDD and so can drive PWR_ON pin).The STM32MP15x device waits a tVDDCORETEMPO delay during which VDDCORE is expected to reach its minimumRun mode value. The STM32MP15x device then waits a programmable delay (EADLY[2:0]) in RCC resetduration and LSI control register (RCC_RDLSICR), before the BOOTROM performs any access to the externalmemories to allow all required external power regulators Run mode value recovery (external Flash power suppliesor other).In order to find the value of tVDDCORETEMPO refer to the table “Embedded reset and power control blockcharacteristics” in the corresponding STM32MP15x device datasheet (tVDDCORETEMPO minimum value is 200us).• When using STPMIC1x, the exit from Standby mode is notified from STM32MP15x device by the PWR_ON

pin which toggles back to 1 thus requesting changing supply level on STPMIC1x output supplies. TheSTPMIC1x device ensures that VDDCORE output supply reaches its minimum Run mode value in less thantVDDCORETEMPO delay and that the EADLY[2:0] delay can be set to a minimum value defined by the sameformula provided in Section 4.6.3 Exit from LP-Stop mode. It is recommended to use a reasonable marginof 5-10 ms for EADLY[2:0].

• When using discrete external regulator components, the hardware should be able to set the VDDCORE supplyto its minimum Run mode value within the tVDDCORETEMPO delay and should handle the setting of therequired power supplies to their Run mode value within the programmed EADLY[2:0] delay.

Figure 11. Wakeup sequence from Standby

tVDDCORETEMPO

VDDCOREVDDCORE Run mode min

value

Wake-up request Programmable delay

EADLY[2:0]

PWR_ON

Regulators state Run valueLow power

value

Run mode(BOOTROM access to

Flash, etc..)

Many system configuration are reset after a wake up from Standby:• The clock tree is back to HSI source, so the retention firmware (if present) should always use the HSI as

kernel clock for the peripherals that it needs to use.• It is recommended that the retention firmware stays on HSI in order to avoid clock tree conflict with Linux (if

used).

4.6.6 Exit from VBAT modeWhen the STM32MP15x device is in VBAT mode, only the VSW supply is maintained by an external VBATsupply.The available wakeup sources (TAMP, RTC) can activate PC13 pin to inform external regulator about the wakeuprequest. The external regulator then restarts the power sequencing like for a system power reset.


AN5109 - Rev 4 page 23/38

4.6.7 Exit from MPU CStop and CStandbyThe difference between MPU CStop (PDDS=1, CSTBYDIS=1) and CStandby is that the exit mode is different(see Table 6. Power-system mode versus sub-system mode summary).When exit from MPU CStandby with System in Run, Stop, LP-Stop or LPLV-Stop, program execution restartswith a local MPU reset. This "reboot" can affect MCU operation due to possible reinitialization of some peripheralregisters by the BootROM when reloading MPU initialization code from external Flash. Refer to Table 6. Power-system mode versus sub-system mode summary.This "reboot" cannot be correctly executed in case the external Flash memory is in a mode not expected by theBootROM (for example if the SD-Card has been set in UHS-I mode while BootROM is expected to be in standardmode). For those reasons, it is usually preferably to use the MPU CStop mode rather than the MPU CStandbymode. Note that MPU Cstandby mode is not used in the ST Linux distribution.When exit from MPU CStandby or CStop (PDDS=1, CSTBYDIS=1) with System in Standby, program executionrestarts in the same way as after a power on reset (such as option bytes loading or reset vector fetched). Refer toTable 6. Power-system mode versus sub-system mode summary. In such exit mode it is expected that the MCUrestarts from reset and that there is no impact from MPU reboot.

Note: MPU CStandby is not used on ST Linux distribution since its wake up is not deterministic (CStandby exit is donewithout power cycle whereas Standby exit implies a power cycle).Refer to the application note Getting started with STM32MP1 Series hardware development (AN5031) for moredetails on hardware constraints.When exit from MPU CStop with system in Stop, LP-Stop or LPLV-Stop mode, program execution restartsthrough the interrupt handler, (if the WFI (wait for interrupt) instruction or Return from ISR was used to enter intolow-power mode) or restarts from the instruction following WFE (wait for event) (if the WFE instruction is usedto enter into low-power mode). This is the recommended mode to ensure independent MCU behavior if MPU isrestarted before system Standby entry.


AN5109 - Rev 4 page 24/38

5 STM32MP15x lines peripherals configuration for low-power

STM32MP15x lines implement many peripherals. Their configuration can play an important role in the powerconsumption. This section describes how to configure the relevant peripherals.

5.1 Peripheral assignment and allocation

There are three available context during Run time:• Cortex-A7 secure• Cortex-A7 non-secure• Cortex-M4

Each peripheral can be “assigned” to one or several (shared) of those contexts. This is done by the ExtendedTrustZone protection controller (ETZPC).Each peripheral is assigned at reset time (A7, A7 secure, M4 or shared) according to the Referencemanual register content, or during boot time when using STM32MPU OpenSTLinux Distributions (seeFigure 13. STM32MP15x lines peripheral assignment using opentSTLinux distribution). The software can laterupdate this default configuration during runtime.When one of the context wants to use a peripheral assigned to it, it has to ensure the peripheral is clocked. Soprior to use a peripheral, the MPU or MCU has to enable it, also it can define if this peripheral remains active inCSleep mode. This clocking enabling is done by the RCC and is called “allocation” of peripheral to a processor.• The MPU can allocate or deallocate a peripheral for itself and for the MCU.• The MCU can allocate or deallocate a peripheral for itself but not for the MPU.

Enabling a peripheral is done by setting the dedicated PERxEN bit on register RCC_MP_xxxxENSETR on MPUside and register RCC_MC_xxxxENSETR on MCU side.Disabling a peripheral is done by setting the dedicated PERxEN bit on register RCC_MP_xxxxENCLRR on MPUside and register RCC_MC_xxxxENCLRR on MCU side.Activating a peripheral during CSleep is done by setting the dedicated PERxLPEN bit on registerRCC_MP_xxxxLPENSETR on MPU side and register RCC_MC_xxxxLPENSETR on MCU side.Disabling a peripheral during CSleep is done by setting the dedicated PERxLPEN bit on registerRCC_MP_xxxxLPENCLRR on MPU side and register RCC_MC_xxxxLPENCLRR on MCU side.When using STM32Cube_FW_MP1 the user can allocate the peripheral and control the peripheral clocks inCSleep mode through the dedicated function defined in STM32MP15xx_hal_rcc.h:

__HAL_RCC_xxxx_CLK_ENABLE();__HAL_RCC_xxxx_CLK_SLEEP_ENABLE();

On the MPU side, the IP drivers enable their clocks by making the allocation. Refer to the sections“Peripheral allocation” and “General clock concept overview” of the corresponding reference manual (seeTable 2. STM32MP15x lines configuration ) for more details.For most of the peripherals, once 'allocated' to a processor, it is possible for the application to control theactivation/deactivation of their kernel and bus interface clocks.The peripheral allocation is used by the RCC to automatically control the clock gating according to the CPUsmodes.Depending on the operating power supply range, some peripheral may be used with limited functionality andperformance. For more details refer to the section “General operating conditions” in the corresponding datasheet.The figure below gives an example of peripheral allocation with the following considerations:• The MPU enabled the ETH, SDMMC3, SRAM3 and RETRAM. Note that SYSRAM, DDRC, DDRPHYC and

IWDG1 are implicitly allocated to MPU. The group composed by the MPU, bus matrix 1, bus matrix 2, andperipherals allocated via RCC_MP_xxxx registers are forming the MPU peripheral domain (MPU_DOM).

• The MCU enabled SYSRAM, QSPI, USBO and USART1. The group composed by the MCU, bus matrix 1,bus matrix 2 and peripherals allocated via RCC_MC_xxxx registers are forming the MCU peripheral domain(MCU_DOM).

AN5109STM32MP15x lines peripherals configuration for low-power

AN5109 - Rev 4 page 25/38

Note: PWR and RCC are common resources and implicitly allocated to both MPU and MCU. SRAM1, SRAM2,SRAM3 and SRAM4 are also implicitly allocated to both MPU and MCU because the MLAHB bridge is enabledif one of the processor is in CRun. RETRAM is also implicitly allocated to both MPU and MCU in order to allowaccesses when the system exits from Standby.

Note: The BKPSRAM has a dedicated enable bit in order to gate the bus interface clock. Prior to use the enable bit,the BKPSRAM needs to be enabled.

Figure 12. Peripheral allocation example

MPU

SDMMC1

ETH

PER...

...

MCU

SDMMC3

USBO

PER...

...

MPU_DOM

Peripherals implicitly allocated to MPU

I2C4

PER...

...

MCU_DOM

IWDG1

Peripherals implicitly allocated to MCU

Peripherals implicitly allocated to bothMPUs

RCC

PWR

DDRC

PER...SAI4Bu

s M

atrix

2 (i

nclu

ding

MLA

HB,

AH

B1,2

,3,4

, APB

1,2,

3)

USART1

SYSRAM

QSPI

SPI6

MPU Sub-System MCU Sub-System

BKPRAM

SRAM1

SRAM2

SRAM3

RETRAMIWDG2

Bus

Mat

rix 1

(inc

ludi

ng A

XI, A

HB5

,6, A

PB4,

5)

AXI Sub-System

DDRPHYC

MPU_DOMMCU_DOM

If using ST Linux distribution, the figure below shows the list of peripherals and their possible assignment toCortex-A7 secure, Cortex-A7 non-secure, Cortex-M4 or Shared context.

AN5109Peripheral assignment and allocation

AN5109 - Rev 4 page 26/38

Figure 13. STM32MP15x lines peripheral assignment using opentSTLinux distribution

RTC

FMC

CRC1CRYP1

RNG1

DCMI

I2C (x4)

USART (x3) UART (x4 )

ADCDFSDM

DACVREFBUF

OTG(USB OTG)

ETH

SDMMC3

LPTIM (x5)TIM (x14)

DMAMUX

MDMA

GPIOZ

MCU SRAM3/4(128KB)

SYSRAM(256KB)

EXTI

IPCC

Low-speed interfaces

I2C4

Timers

Cortex-M4(co-processor)

Analog

VisualGPU DSI LTDC

IWDG1

USART1

I2C6

WWDG

RETRAM(64KB)DDR

USBH(Host)

High speed interfaces

Security

CRC2CRYP2

RNG2 HASH2

RCC

BSEC

TAMP

DebugHDP STM

Watchdog

RAM

IOs

DMA

MCU SRAM1/2(256KB)

ETZPC

TZC

Interrupts

NVIC

STGEN

Cortex-A7(master)Cortex-A7

(master)

DTSPWR

Dual QSPI

CEC

FDCAN

HASH1

SDMMC1/2

IWDG2

GPIOA -K

Shared by A7S & A7NS & M4

Shared byA7S & A7NS

Assigned to A7 Non Secure

Assigned to M4

Assigned to A7 Secure (TZ)

Shared byA7NS & M4

Assignedto A7NS or M4

Shared IP

Assigned IP

Assigned to A7S or A7NS

Power & Thermal

Coprocessor

Mass storage

Networking

DBGMCU

Core

SPI6

STGEN

SYSCFG GIC DMA1 DMA2

BKPSRAM(4KB)

SPI (x2)

SAI (x4)SPI I2S (x3)

AudioSPDIFRX

Assigned to A7S or A7NS or M4

Assigned to A7S or Shared by A7NS & M4

AN5109Peripheral assignment and allocation

AN5109 - Rev 4 page 27/38

5.2 Peripheral clock distribution

The peripheral clocks are the clocks provided by the RCC to the peripherals. Two kinds of clock are available:• The bus interface clocks.• The kernel clocks.

The following figure describes the peripheral clock distribution on the STM32MP15x devices.

Figure 14. Peripheral clock distribution

PERxSRC

clocks from oscillatorsclocks from external PADs

clocks from other peripherals

D

clocks from PLLs ......

...

Kernel_clock

PKCS

PERx

Kernel clock(s)

Bus clock(s)

Peripheral clocks

Kernel clock request(s)

Bus_clockPeriph_Enable

AHB / APB / AXI clock

RCC

A kernel clock allows the peripheral to use a different clock frequency for the peripheral function (compared to theperipheral bus clock).When using STM32CubeMP1 package kernel clock of the peripheral can be chosen by using the dedicatedfunction defined in stm32mp1_xx_hal_rcc_ex.h file:

__HAL_RCC_PERx_CONFIG (__PERxCLKSource__);

On MPU side, the Linux clock driver offers a 'clk_set_parent' service able to select the kernel clock.For more details about kernel clock distribution and peripheral clock gating refer to the section “Peripheral clockgating control” of the corresponding reference manual (see Table 2. STM32MP15x lines configuration).

5.3 Stop, LP-Stop, LPLV-Stop peripheral allocation

In Stop, LP-Stop mode, the peripherals using the LSI or the LSE clock and peripherals having a kernel clockrequest selecting a clock source in the RCC which is able to run in Stop mode, are still able to operate.In order to allow the I2Cs or U(S)ARTs to work in CStop or system Stop, LP-Stop mode, the user must selectan oscillator as kernel clock: hse_ker_ck, hsi_ker_ck or csi_ker_ck according to RCC PERxEN. The selectedoscillator(s) is provided to the peripheral when the peripheral generates a kernel clock request.The oscillator(s) remain activated in Stop, LP-Stop mode if the xxxKERON=1, allowing immediate delivery of theclock on wakeup from Stop, LP-Stop or on peripheral kernel clock request.Refer to Table: Functionalities depending on system operating mode in the corresponding reference manual (seeTable 2. STM32MP15x lines configuration).In LPLV-Stop mode, the external power supply is expected to lower its voltage level. As a result, only a limitednumber of peripheral are still functional (BOR, PVD, AVD, VBATH-L monitoring, TEMPH-L monitoring, LSI, LSE,LSE CSS, RTC, IWDG), additionally some can wake up the system (TEMP, GPIO). Refer to Table: Functionalitiesdepending on system operating mode in the corresponding reference manual (see Table 2. STM32MP15x linesconfiguration).

AN5109Peripheral clock distribution

AN5109 - Rev 4 page 28/38

6 Debug tips

This section describes how to use the debug features in low-power modes.

6.1 Enabling debugging in low-power mode: low-power mode emulation

When entering a low-power mode, the clock of the processors, the subsystem clocks or the core power supplymay be switched off. This action prevents debug accesses to the related un-clocked domains. The STM32MP15xlines devices support a low-power mode emulation that keeps debug capability while in low-power mode. This iscontrolled by DBGSLEEP, DBGSTOP and DBGSTBY bits in DBGMCU configuration register (DBGMCU_CR).

Note: DBGMCU set of registers applies to both MPU and MCU subsystem. The naming DBGMCU has been kept forconsistency with legacy STM32 MCU products.Comprehensive information can be found in the following parts of the corresponding STM32MP15x devicereference manual (see Table 2. STM32MP15x lines configuration):• Low-power emulation mode in RCC chapter.• Microcontroller debug unit (DBGMCU) in the Debug support chapter.

Note: Using low-power emulation modes has a significant impact on the power savings (various clocks and powersupply being kept on). Such modes should only be used for debugging purposes. Power consumptionmeasurements are not relevant while using low-power mode emulation.

Table 13. HAL debug function

Function Description

HAL_DBGMCU_EnableDBGSleepMode()

HAL_DBGMCU_DisableDBGSleepMode()Enable/disable the Debug module during CSleep mode

HAL_DBGMCU_EnableDBGStopMode()

HAL_DBGMCU_DisableDBGStopMode()Enable/disable the Debug Module during Stop modes

HAL_DBGMCU_EnableDBGStandbyMode()

HAL_DBGMCU_DisableDBGStandbyMode()Enable/disable the Debug Module during Standby mode

6.2 Using HDP for debugging the low-power modes

The hardware debug port (HDP) allows the observation of internal signals that can be used to debug the entry inand the exit from low-power modes. Those signals can be output on some pins of the STM32MP15x device andeasily monitored (though a scope or a logic analyzer). See the Hardware debug port section in the correspondingSTM32MP1 Series reference manual (see Table 2. STM32MP15x lines configuration) for the comprehensive listof signal and their mixing configuration.HDP and associated GPIOs should be disabled in the final application in order to reach a lower powerconsumption.The most important signals for power-mode debugging are described in the tables below.

Table 14. Monitoring the CSleep modes

Signal Description

CA7 STANDBYWFI0 (HDP7, HDP_MUX=0)

CA7 STANDBYWFI1 (HDP6, HDP_MUX=0)

CA7 STANDBYWFE0 (HDP7, HDP_MUX=1)

CA7 STANDBYWFE1 (HDP6, HDP_MUX=1)

The CA7 STANDBYWFI0 and CA7 STANDBYWFI1 (in caseof WFI) or CA7 STANDBYWFE0 and CA7 STANDBYWFE1(in case of WFE) signals can be used to monitor the CA7CSleep mode.

Those signals indicate whether a core is in WFI or WFE state.

CM4 SLEEPING (HDP4, HDP_MUX=1) The CM4 SLEEPING signal can be used to monitor the CM4CSleep mode (WFI or WFE).

AN5109Debug tips

AN5109 - Rev 4 page 29/38

Table 15. Monitoring the entry in CStop modes and in Stop mode

Signal Description

RCC pwrds_mcu (HDP2, HDP_MUX=6)

RCC pwrds_mpu (HDP1, HDP_MUX=6)The RCC pwrds_mcu (or RCC pwrds_mpu) signal can beused to monitor the CM4 CStop mode (or CA7 CStop mode).

RCC pwrds_sys (HDP3, HDP_MUX=6) The RCC pwrds_sys signal can be used to monitor theSTM32MP15x device Stop mode.

Table 16. Monitoring the exit from Stop mode

Signal Description

pwrwake_sys (HDP0, HDP_MUX=0) The pwrwake_sys signal can be used to monitor that the EXTIhas received a wakeup interrupt from a peripheral.

pwrwake_mpu (HDP2, HDP_MUX=0)

pwrwake_mcu (HDP1, HDP_MUX=0)

The pwrwake_mpu (or pwrwake_mcu) signal can be usedto monitor that the CA7 subsystem (or CM4 subsystem) isrequested to return to CRun mode.

Refer to http://wiki.st.com/stm32mpu/wiki/HDP_Linux_driver for an example of HDP usage.

AN5109Using HDP for debugging the low-power modes

AN5109 - Rev 4 page 30/38

https://wiki.st.com/stm32mpu/wiki/HDP_Linux_driver

Bare metal HDP initialization sample code

void HPDConfig(void) {GPIO_InitTypeDef GPIO_InitStruct;/** HDP AF2 (AF0)* 0 PI12 (PA4)* 1 PI13 (PC6)* 2 PJ5 (PE13)* 3 PJ6 (PE15)* 4 PK1 (PC7)* 5 PK2 (PD3)* 6 PK5 (PB8)* 7 PK6 (PB9)*/

/* Clock GPIOI GPIOJ and GPIOK */__HAL_RCC_GPIOI_CLK_ENABLE();__HAL_RCC_GPIOJ_CLK_ENABLE();__HAL_RCC_GPIOK_CLK_ENABLE();/*** Route HDP outputs to GPIOs ***//* AF2,PI12 -> HDP0 *//* AF2,PI13 -> HDP1 */GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_13;GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;GPIO_InitStruct.Pull = GPIO_NOPULL;GPIO_InitStruct.Alternate = GPIO_AF2_HDP;HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);

/* AF2,PJ5 -> HDP2 *//* AF2,PJ6 -> HDP3 */GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6;HAL_GPIO_Init(GPIOJ, &GPIO_InitStruct);

/* AF2,PK1 -> HDP4 *//* AF2,PK2 -> HDP5 *//* AF2,PK5 -> HDP6 *//* AF2,PK6 -> HDP7 */GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_5|GPIO_PIN_6;HAL_GPIO_Init(GPIOK, &GPIO_InitStruct);

/* Clock HDP */__HAL_RCC_HDP_CLK_ENABLE();

/*** Select signals for HDPx outputs ***//* Select CM4 SLEEPDEEP signal as the HDP0 output */MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX0, (HDP_MUX_MUX0_1 ));/* Select RCC pwrds_mpu signal as the HDP1 output */MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX1, (HDP_MUX_MUX1_6 ));/* Select RCC pwrds_mcu signal as the HDP2 output */MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX2, (HDP_MUX_MUX2_6 ));/* Select RCC pwrds_sys signal as the HDP3 output */MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX3, (HDP_MUX_MUX3_6 ));/* Select CM4 SLEEPING signal as the HDP4 output */MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX4, (HDP_MUX_MUX4_1 ));/* Enable HDP */SET_BIT(HDP->HDP_CTRL, HDP_CTRL_EN);}

AN5109Using HDP for debugging the low-power modes

AN5109 - Rev 4 page 31/38

6.3 Linux debug hints

Checking clock summary using: cat /sys/debug/kernel/clk/clk_summary.• It displays the clock tree in a hierarchical way with frequency and state.

Monitoring the power status flags using ‘devregs’ command.• PWR_MPUCR: contains the Stop flags for MPU.• PWR_MCUCR: contains the Stop flags for MCU.• RCC_MP_RSTSR: contains the reset reasons including Standby and Cstandby.

If the system does not wakes up, check that at least one wakeup source is enabled, that wakeup peripherals areclocked from HSI or HSE clock and that wakeup pin polarity and pull up/pull down have been set.If the system does not enter low-power:• Check that a wakeup event is not already pending when calling the mode.• cat /proc/interrupts can give an indication of such events.• Check EXTI setup.

If overall power consumption is too high:• Check that clocks are released when a peripheral is not used. This can be checked thanks to clk_summary

command.

AN5109Linux debug hints

AN5109 - Rev 4 page 32/38

Revision history

Table 17. Document revision history

Date Version Changes

30-Jan-2019 1 Initial release.

11-Feb-2019 2

Updated:• Section Linux power commands mapping to STM32MP15x lines power

modes• Table Deepest power mode per wakeup source group and equivalence

between Linux and STM32MP15x lines

18-Feb-2019 3 Updated Table System low-power modes summary

03-Nov-2020 4

Updated:• Replaced "STM32MP1 Series" for "STM32MP15x lines" in the whole

document to refer to the applicable products of this application note.• Document's title and cover page.• Section 3.2 System supplies (VDD and VDDCORE)• Figure 2. Discrete supplies example 3.3V I/Os with DDR3L• Figure 3. STPMIC1x example 3.3 V I/Os with DDR3L• Table 5. System’s low-power mode wakeup capabilities• Section 4.3 External control signals PWR_ON, PWR_LP pins• Section 4.5 Power management under Linux• Section 4.5.1 Linux power commands mapping to STM32MP15x lines

power modes• Section 6.2 Using HDP for debugging the low-power modes

AN5109

AN5109 - Rev 4 page 33/38

Contents

1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

2 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

3 Power management concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

3.1 STM32MP15x lines system architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3.2 System supplies (VDD and VDDCORE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

4 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

4.1 Operating modes description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4.2 Low-power mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.2.1 Low-power mode control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.3 External control signals PWR_ON, PWR_LP pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.3.1 Using STPMIC1x power regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.3.2 Using other external power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.4 Low-power mode entry sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.5 Power management under Linux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.5.1 Linux power commands mapping to STM32MP15x lines power modes . . . . . . . . . . . . . . 17

4.5.2 Controlling MCU power modes under Linux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.6 Low-power mode exit sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.6.1 Exit from system power-reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.6.2 Exit from Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.6.3 Exit from LP-Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.6.4 Exit from LPLV-Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.6.5 Exit from Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.6.6 Exit from VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.6.7 Exit from MPU CStop and CStandby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5 STM32MP15x lines peripherals configuration for low-power . . . . . . . . . . . . . . . . . . . . . . .25

5.1 Peripheral assignment and allocation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.2 Peripheral clock distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.3 Stop, LP-Stop, LPLV-Stop peripheral allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6 Debug tips. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

AN5109Contents

AN5109 - Rev 4 page 34/38

6.1 Enabling debugging in low-power mode: low-power mode emulation . . . . . . . . . . . . . . . . . . 29

6.2 Using HDP for debugging the low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.3 Linux debug hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

List of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

List of figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

AN5109Contents

AN5109 - Rev 4 page 35/38

List of tablesTable 1. Applicable products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Table 2. STM32MP15x lines configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Table 3. Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Table 4. Power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Table 5. System’s low-power mode wakeup capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Table 6. Power-system mode versus sub-system mode summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Table 7. System low-power modes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Table 8. PRW_ON, PWR_LP levels according power modes, LPDS, LVDS and LPCFG bits . . . . . . . . . . . . . . . . . . . . . 12Table 9. STPMIC1x (HP mode) programming for Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Table 10. STPMIC1x (LP mode) programming for LP-Stop LPLV-Stop and Standby mode. . . . . . . . . . . . . . . . . . . . . . . . 14Table 11. Low-power modes functions used on MCU within STM32CubeMP1 package. . . . . . . . . . . . . . . . . . . . . . . . . . 15Table 12. Deepest power mode per wakeup source group and equivalence between Linux and STM32MP15x lines. . . . . . 18Table 13. HAL debug function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29Table 14. Monitoring the CSleep modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29Table 15. Monitoring the entry in CStop modes and in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30Table 16. Monitoring the exit from Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30Table 17. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

AN5109List of tables

AN5109 - Rev 4 page 36/38

List of figuresFigure 1. STM32MP15x lines high-level system architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Figure 2. Discrete supplies example 3.3V I/Os with DDR3L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Figure 3. STPMIC1x example 3.3 V I/Os with DDR3L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Figure 4. Power states and external regulator control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Figure 5. STM32MP15x lines high-level system architecture when using STPMIC1x . . . . . . . . . . . . . . . . . . . . . . . . . . 13Figure 6. Linux power management software framework . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Figure 7. Available power state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Figure 8. Wakeup sequence from system reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21Figure 9. Wakeup sequence from LP-Stop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Figure 10. Wakeup sequence from LPLV-Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Figure 11. Wakeup sequence from Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Figure 12. Peripheral allocation example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Figure 13. STM32MP15x lines peripheral assignment using opentSTLinux distribution . . . . . . . . . . . . . . . . . . . . . . . . . 27Figure 14. Peripheral clock distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

AN5109List of figures

AN5109 - Rev 4 page 37/38

IMPORTANT NOTICE – PLEASE READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to STproducts and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. STproducts are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design ofPurchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or servicenames are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

© 2020 STMicroelectronics – All rights reserved

AN5109

AN5109 - Rev 4 page 38/38

http://www.st.com/trademarks

an5109 introduction application note · table 4. system’s low-power mode wakeup capabilities...

Documents