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AN 836: RapidIO II ReferenceDesign for Avalon-ST Pass-ThroughInterface

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Contents

1 RapidIO II Reference Design for Avalon®-ST Pass-Through Interface............................. 31.1 Introduction...........................................................................................................31.2 Requirements.........................................................................................................4

1.2.1 Software Requirements............................................................................... 41.2.2 Hardware Requirements.............................................................................. 41.2.3 Features of the RapidIO II Reference Design for the Avalon-ST Pass-

Through Interface......................................................................................41.3 Downloading and Installing the Reference Design........................................................41.4 Walkthrough.......................................................................................................... 6

1.4.1 Hardware Setup......................................................................................... 71.4.2 Programming the FPGA................................................................................91.4.3 Running the Design...................................................................................101.4.4 System Console User Interface Commands...................................................131.4.5 Register Address Map................................................................................ 14

1.5 Document Revision History for RapidIO II Reference Design for the Avalon-ST Pass-Through Interface............................................................................................. 17

Contents

AN 836: RapidIO II Reference Design for Avalon-ST Pass-Through Interface2

1 RapidIO II Reference Design for Avalon®-ST Pass-Through Interface

1.1 Introduction

The RapidIO II reference design for the Avalon Streaming (Avalon-ST) pass-throughinterface demonstrates the use of the Avalon-ST pass-through interface to implementNWRITE transactions using the RapidIO II IP.

You can use the Avalon-ST pass-through interface of the RapidIO II IP to implementRapidIO transaction types not available by our logical layer (for example, messagepassing and data streaming). Additionally, you can use this interface to implementcustom functions not specified by the RapidIO protocol but applicable to a specificsystem.

The Avalon-ST pass-through interface is an optional interface that is generated whenyou select the Avalon-ST pass-through interface in the Transport andMaintenance page of the RapidIO II IP parameter editor.

Figure 1. RapidIO II Avalon-ST Pass-Through Interface Reference Design BlockDiagram

Ava

lon-M

M Traffic

Generator

StatisticsModule

JTAG

Ava

lon-M

MAv

alon-

ST

SystemConsole

Pass-

Thro

ugh

Regis

ter-A

ccess

Status Packet

Error-MonitoringSignals RX/TX

Serial

Trans

ceive

r A

ccess

Traffic Checker

ClientDecode

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Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartusand Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or othercountries. Intel warrants performance of its FPGA and semiconductor products to current specifications inaccordance with Intel's standard warranty, but reserves the right to make changes to any products and servicesat any time without notice. Intel assumes no responsibility or liability arising out of the application or use of anyinformation, product, or service described herein except as expressly agreed to in writing by Intel. Intelcustomers are advised to obtain the latest version of device specifications before relying on any publishedinformation and before placing orders for products or services.*Other names and brands may be claimed as the property of others.

ISO9001:2008Registered

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The RapidIO II reference design for Avalon-ST pass-through interface includes a trafficgenerator. The traffic generator initiates NWRITE RapidIO transactions and drives theRapidIO II IP Avalon-ST source. The design also includes a traffic checker which sinksthe RapidIO transactions and is connected to the RapidIO II IP Avalon-ST sink.

Related Links

RapidIO II IP Core User Guide

1.2 Requirements

1.2.1 Software Requirements

• Intel Quartus Prime Pro Edition 17.1

• RapidIO II IP License

Note: You need the license only if you compile the design or target the design toyour device. Alternatively, you can use the free Intel FPGA IP EvaluationMode feature to evaluate licensed Intel FPGA IP cores in simulation andhardware before purchase.

1.2.2 Hardware Requirements

• Intel Stratix 10 GX FPGA Development Board (1SG280LU3F50E3VGS1 with L-Tiletransceivers(1))

• FMC Loopback Card

• Intel FPGA Download Cable II

• Power Supply

Related Links

Intel Stratix 10 FPGA Development Kit

1.2.3 Features of the RapidIO II Reference Design for the Avalon-STPass-Through Interface

The reference design has the following features:

• 4x Mode

• 6.250 Gbaud

• 156.25 MHz Reference Clock

• Avalon-ST Pass-Through Interface

1.3 Downloading and Installing the Reference Design

You can download the reference design from the Design Store. You must have amyAltera account to gain access to the Design Store.

(1) You can target a different device but this will require you to make modifications to the .qsffile.


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1. Download the platform archive file srio2_s10_avst_6g_de.par from the Design Store to your chosen directory.

2. Open the Intel Quartus Prime software, click File ➤ Open Project.

3. Browse to select the srio2_s10_avst_6g_de.par file.

4. Click Open.

5. The Open Design Template window appears. For Project name, entersrio2_s10_avst_6g_de.

Figure 2. Open Design Template

6. Click OK.

After you open the srio2_s10_avst_6g_de.par file in the Intel Quartus Primesoftware, you can see the following directory structure.

Figure 3. Directory Structure for the Reference Design Example<location of the downloaded .par file>

Components ip

client_decode

rtl

xcvr_rst_ctl

basic.tcl

lpbk_ctl.tcl

sri2_s10_avst_6g_de.sof

system_console

top_srio.v

traffic_gen.v

traffic_chk.v main_run.tcl

srio_task.tcl

atx_pll.ip

xcvr_rest_ctl.ip

client_decode.qsys

atx_pll

ip

srio.ip

srio

stats.v

top_srio.sdc

srio2.stp

srio2_s10_avst_6g_de.par

srio2_s10_avst_6g_de.qpf

srio2_s10_avst_6g_de.qsf

jtag_timing_template.sdcoutput_files

Table 1. Reference Design Files

File Name Description

srio2_s10_avst_6g_de.qpf Intel Quartus Prime project file containing the list of all therevisions in the project.

srio2_s10_avst_6g_de.qsf Intel Quartus Prime settings file containing the assignmentsand settings for the project.

jtag_timing_template.sdc Defines the timing constraints for JTAG.

srio2_s10_avst_6g_de.sof Pre-generated programming file.

continued...


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https://cloud.altera.com/devstore/platform/17.1.0/Pro/stratix-10-rapidio-ii-avalon-st-pass-through-interface/

File Name Description

top_srio.v Top-level design file.

traffic_gen.v Traffic generator module.

traffic_chk.v Traffic checker module.

stats.v Statistics collecting module.

top_srio.sdc Top-level timing constraints file.

srio2.stp Pre-populated Signal Tap file.

ip/srio RapidIO II IP sub folder contains all of the requiredsynthesis files for the core.

srio.ip RapidIO II IP variation file that contains theparameterization of an IP core in your project.

components/atx_pll Contains all the necessary synthesis files for the ATX PLL.

components/xcvr_rst_ctl Contains all the necessary synthesis files for the TransceiverReset Controller.

components/client_decode Contains all the necessary synthesis files for the ClientDecode Platform Designer based subsystems.

components/ip Contains all of the Client Decode underlying sub IP block IPvariation files. Created during the Client Decode systemgeneration and this file is required to compile the design.

atx_pll.ip Intel Stratix 10 ATX PLL IP variation file.

xcvr_rst_ctl.ip Intel Stratix 10 Transceiver Reset Controller IP variation file.

client_decode.qsys Platform Designer subsystems contains a JTAG Master andseveral Avalon-MM bridges used to decode the JTAG Avalon-MM address for the different Avalon-MM slave interface.

basic.tcl Defines basic register read and write procedures.

lpbk_ctl.tcl Defines TX to RX PMA buffer serial loopback control.

main_run.tcl Contains main call to the other .tcl files.

srio_tasks.tcl Defines the majority of the RapidIO II related functions andprocedures for controlling the traffic generator/checker andthe statistics collector.

1.4 Walkthrough

To run the design, you must have the Intel Stratix 10 GX FPGA development kit andyou must have installed the Intel Quartus Prime Pro Edition 17.1 software to yourcomputer.


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Follow these steps to run the design:

1.4.1 Hardware Setup

Perform the following steps to setup the hardware for the reference design:

1. Insert the FMC Loopback Card to the FMC port on the Intel Stratix 10 GX FPGAdevelopment board.

2. Connect the Intel FPGA Download Cable II to the Intel Stratix 10 GX FPGAdevelopment board and to your host computer.

3. Connect the power adapter shipped with the development board to the powersupply jack.

4. Set the DIP switches of the Intel Stratix 10 GX FPGA development board asspecified below:

Table 2. DIP Switch Control Settings

DIP Switch Schematic Signal Name Setting

SW8 1 I2C_SDA ON

2 I2C_SCL ON

3 FPGA_PWRGD OFF

SW4 1 RZQ_B2M OFF

2 SI516_FS OFF

SW3 1 CLK0_OEn OFF

2 CLK0_RSTn OFF

3 FACTORY_LOAD OFF

SW2 1 PCIE_PRSNT2n_x16 OFF

2 PCIE_PRSNT2n_x8 OFF



SW6 1 S10JTAG_BYPASSn OFF

2 M5JTAG_BYPASSn OFF

3 FAJTAG_BYPASSn ON

SW1 1 MSEL2 ON

2 MSEL1 ON


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Figure 4. DIP Switches Bottom View

Figure 5. DIP Switches Top View

ON

5. Turn on the power for the Intel Stratix 10 GX FPGA development board.

The hardware systems is now ready for programming.


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Figure 6. Reference Design Hardware Setup

FMC Loopback Card

Intel FPGA Download Cable II

Power Cable

Related Links

• Intel Stratix 10 FPGA Development Kit

• Default Switch and Jumper Settings

1.4.2 Programming the FPGA

You can program the FPGA by using any of the following methods:

1.4.2.1 Using a Nios® II Command Shell

Perform the following steps to program the FPGA using a Nios® II command shell:

1. On the Windows start menu, click All Programs > Quartus installationdirectory > NIOS II Command Shell <vesrion number>, to start a Nios IIcommand shell.

2. Type the following command at the Nios II command shell:

nios2-configure-sof -c “USB-BlasterII [USB-1]” -d 2 sri02_s10_avst_6g_de.sof

1.4.2.2 Using the Programmer

Perform the following steps to program the FPGA using the Programmer:

1. Launch the Intel Quartus Prime software.

2. Before you begin the FPGA configuration, ensure the following:

a. The Intel FPGA Download Cable II driver is installed on the host computer.

b. The board is powered.


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c. No other application is accessing the JTAG chain.

3. Connect the Intel FPGA Download Cable II between your host computer USB portand the USB port on the development board.

4. On the Tools menu, click Programmer.

5. Click Auto Detect to display the devices in the JTAG chain and select a device.

6. Right click and select Change File. Then, select thesrio2_s10_avst_6g_de.sof file from the project directory and click Open.

7. Turn on the Program/Configure option for the srio2_s10_avst_6g_de.soffile.

8. Click Start to download the srio2_s10_avst_6g_de.sof file to the FPGA.Configuration is complete when the progress bar reaches 100%.

1.4.3 Running the Design

When the board is set up and the FPGA is programmed, you can start running thedesign:

1. Invoke the system console. This can be done at the Nios II command shell or fromthe Intel Quartus Prime software GUI.

2. In the command window, change your directory to system_console by typingthe following command :

cd system_console

3. Execute the following commands at the system console:

source main_run.tclcfiglinkcstatsstatsstartstats

4. The traffic generator module starts to generate RapidIO NWRITE transactions witha default payload of 64 bytes. The default number of NWRITE transactions is0xFFFFFFFF (4,294,967,295 decimal). You can stop the traffic generator byentering the stop command. The generated RapidIO transactions are beingreceived at the traffic checker module since all the traffic is looped back throughthe FMC Loopback Card.

You can view the transactions transmitted and received counts as well as otherstatistics by entering the link and the stats commands at the system console.


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Figure 7. Link Command Execution


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Figure 8. Stats Command Execution

5. Use Signal Tap to view the packet exchange. This reference design includes theSignal Tap file srio2.stp which monitors the gen_tx and the gen_rx interfacesof the RapidIO Avalon-ST pass-through interface. The figures below shows theSignal Tap activity.

Figure 9. auto_signaltap_1


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Figure 10. auto_signaltap_2

Related Links

System Console User Interface Commands on page 13

1.4.4 System Console User Interface Commands

Please refer to the below table for the description of the user interface commands:

Table 3. System Console User Interface Commands

Command Description

r Toggles the RapidIO II IP reset input signal. Resets theRapid IO II IP core.

rc Toggles the Transceiver Reset Controller reset input signal.Resets the transceiver PCS and PMA.

ds Disables the scrambler and descrambler in the RapidIO II IPcore. Use for diagnosis purpose.

es Enables the scrambler and descrambler.

link Reports the status of the RapidIO link.

cfig Enables the Input and Output ports and disables DestinationID checking, randomly accepting all incoming requestpackets.

start Programs the number of packets to be transmitted to0xFFFFFFFF and enables the traffic generator. The generatorstops after transmitting 0xFFFFFFFF packets.

stop Stops the traffic generator.

send Takes an integer value representing the number of packetsto send. For an example, send 100: Generates 100packets.

cstats Clear statistics counters.

stats Report statistics counters.

reinit Toggles the PORT_DIS bit of register 0x15C causing aninternal re-initialization of the RapidIO II IP. Helps indiagnosing link up issues.

f4x Forces the RapidIO II IP into 4x mode.

continued...


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Command Description



lps Loop back set, programs the transceivers into serialloopback, TX to RX at the PMA output buffers.

lpc Clears loop back.

lpt Clears the transceiver loopback and then sets it again,toggling serial loopback in the PMA output buffers.

1.4.5 Register Address Map

Table 4. Register Address Map

Module Base Address Offset Description

Transceiver ReconfigurationPort at RapidIO II IP

0x0000_0000 Full transceiver PCS andPMA registers

Please refer to the LogicalView Register Map of L-Tiletransceivers.

Traffic Generator 0x0004_0000 0x0000 Main control[0]- Start traffic[4]- Stop traffic

0x0004 Packet size[31:0]- Payload byte size.The default value is 64.

0x0008 Header size[31:0]- Packet header sizein bytes. The default value is12.

0x000c IPG size[31:0]- Intel Packet Gap incycles. IDLE cycles insertedbt the Traffic Generatorbetween the packets at theAvalon-ST interface. Thedefault value is 8.

0x0010 Packets to transmit[31:0]- Packets to begenerated.

0x0014 Source ID[15:0]- Source ID value tobe used in composedpackets. The default value is0xCCCC.

0x0018 Destination ID[15:0]- Destination ID valueto be used in composedpackets. The default value is0x5555.

0x001c Starting address[31:0]- Starting address usefor NWRITE transactions tobe generated.

0x0020 Priority

continued...


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[1:0]- Priority to be used forNWRITE transactions to begenerated.

0x0024 RapidIO II IP Reset Control.[0]- Resets the RapidIO IIIP.

0x0028 Transceiver PCS/PMA ResetControl[0]- Resets the transceiverPCS/PMA.

Statistics Module 0x0005_0000 0x0000 Main Control[0]- Clears statistics

0x0004 Transmitted packet count

0x0008 Packets cancelled bytransmit side

0x000c Packet Accepted ControlSymbols transmitted

0x0010 Packets-Retrys ControlSymbols transmitted

0x0014 Packets-Not-AcceptedControl Symbols transmitted

0x0018 Packet Accepted ControlSymbols received

0x001c Packet Retrys ControlSymbols received

0x0020 Packets-Not-AcceptedControl Symbols received

0x0024 Packet CRC Errors received

0x0028 Packets dropped by theTransport Layer

0x002c Control Symbol Errors

0x0030 Base Device ID (small)programmed

0x0034 Base Device ID (large)programmed

0x0038 Port Initialized

0x003c Link Initialized

0x0040 Port Ok

0x0044 Port Error

0x0048 Four Lanes aligned

0x004c Two Lanes aligned

0x0050 TX Analogreset (one bit perlane)

0x0054 TX Digitalreset (one bit perlane)

continued...


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0x0058 RX Analogreset (one bit perlane)

0x005c RX Digitalreset (one bit perlane)

0x0060 RX is LockedToData (one bitper lane)

0x0064 RX Sync Status

0x0068 RX Signal Detect

0x006c Reset Controller TX Ready(one bit per lane)

0x0070 Reset Controller RX Ready(one bit per lane)

Traffic Checker 0x0006_0000 0x0000 Main control[0]- Clears statistics

0x0004 NREADs count

0x0008 NWRITEs count

0x000c NWRITE_Rs count

0x0010 SWRITEs count

0x0014 Flow Control Types count

0x0018 Maintenance Read Requesttypes

0x001c Maintenance Write Requeststypes

0x0020 Maintenance Read Responsetypes

0x0024 Maintenance Write Responsetypes

0x0028 Maintenance Port Writes

0x002c Data Stream Types count

0x0030 Doorbell Request Types

0x0034 Message Type count

0x0038 Response Types No Payload

0x003c Message Response Types

0x0040 Response Types with Payload

RapidIO II IP RegisterAccess

0x0007_0000 Please refer to the SoftwareInterface section in theRapidIO II IP core userguide

Related Links

• Software Interface

• Logical View of the L-Tile ES-1 Transceiver Registers


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1.5 Document Revision History for RapidIO II Reference Design forthe Avalon-ST Pass-Through Interface

Date Version Changes

December 2017 2017.12.18 Initial release.


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