pbiw-sparc decoding -...

PBIW-SPARC decoding

Márcio Afonso Soleira Grassi

Orientador: Prof. Dr. Ricardo Ribeiro dos Santos

LSCAD - Laboratorio de Sistemas Computacionais de Alto Desempenho

Universidade Federal de Mato Grosso do Sul

Campo Grande - MS

Brasil

PBIW

PBIW

Número de registradores de leitura e

escrita;

Número e tamanho de imediatos;

Tamanho da tabela de padrões;

Operandos permanecem na instrução;

Sinais de controle e ponteiros para

operandos são armazenados no padrão;

This is SPARC!!!!!!

Formulated at Sun Microsystems based

on designs engineered at the University of

California at Berkeley

RISC

Load/store

Big endian

SPARC instructions

Leon3 Decode Stage

Leon3 Decode Stage

Leon3 Decode Stage

Leon3 Decode Stage

Leon3 Decode Stage

Leon3 Datapath with Decoder

Decoder Circuit

Instruction Encoding

Instructions Patterns

Decoder Circuit – Format 1

Decoder Circuit – Format 2

Decoder Circuit – Format 3

Processor Leon3

SPARC V8 instruction set

Advanced 7-stage pipeline

Hardware multiply, divide and MAC units

Separate instruction and data cache

(Harvard architecture)

AMBA-2.0 AHB bus interface

High Performance: 1.4 DMIPS/MHz, 1.8

CoreMark/MHz (gcc -4.1.2)

Processor Leon3

Highly configurable

Processor Leon3

Number of windows – 8

Branch prediction

i-cache – 2 sets of 8kbytes

D-cache – 2 sets of 4kbytes

Jtag and uart

Memory management unit

Trace buffer

Tools

Quartus II: Synthesis and Place and Route

ModelSim : Simulation

GRMON : Debug monitor interface

FPGA ALTERA DE2 EP2C35F672C6

Simulation

Area

Integer unit Logical elements

Without decoder 4678

With decoder 5472

Decoder circuit 44

Area +16,97%

Area

Processador Leon3 Logical elements

Without decoder 12170

With decoder 13685

Area +12,44%

Problems

Instructions : 16-bit or 24-bit

Compilers – Grtools

GRMONRCP

Nexts tasks

Validation decoder with GRMON

Power and performance characterization

The end

Killer Questions?????