mirror adder

Lecture 16, ECE 124A, VLSI Principles Kaustav Banerjee

ECE 124AECE 124AVLSI PrinciplesVLSI Principles

Lecture 16Lecture 16

Prof. Kaustav BanerjeeElectrical and Computer Engineering

E-mail: kaustav@ece.ucsb.edu

A Generic Digital ProcessorA Generic Digital Processor

MEMORY

DATAPATH

CONTROL

Lecture 15Static, Dynamic MemoryLatch, RegisterTiming, Stability

Interconnect

Sequential Circuit

Today……

DATAPATHDATAPATHThe core of a digital ProcessorDatapath consists

Logic Blocks– Combinational Logic Functions (AND, OR, XOR….)

Arithmetic Blocks– Addition– Multiplication– Comparison– Shift

An Intel MicroprocessorAn Intel Microprocessor9-

CARRYGEN

SUMGEN+ LU

1000um

sum sumb

LU : LogicalUnit

to Cachenode1

Fetzer, Orton, ISSCC’02

Itanium has 6 integer execution units like this

Intel Itanium®

Integer Datapath

BitBit--Sliced DesignSliced Design

Bit 32

……

Control

Design a single bit datapath and repeat for all bits

AddersAdders

DDeesign an Addersign an AdderFundamental Arithmetic Building BlockPerformance

Logic Level Optimization– Optimize Boolean Functions– Carry Lookahead

Circuit Level Optimization– Transistor Sizing

Power Consumption

HalfHalf--Adder ImplementationsAdder ImplementationsHalf-Adder X

Half-Adder

FullFull--AdderAdder

Cin Fulladder

in inin in in

out in in

S A B C ABC ABC ABC ABCC AB BC AC= ⊕ ⊕ = + + +

Express Sum and CarryExpress Sum and Carry

Generate (G) = AB

Propagate (P) = A ⊕ B

Delete (D) = A B

Co = G + PCi

S = P Ci⊕Truth Table for Full Adder

G11111G10011P10101P01001P10110P01010D01100D00000

statusCoSCiBA

Complimentary Static CMOS Full AdderComplimentary Static CMOS Full Adder

28 Transistors

0( )in i i

o in in

S A B C ABC C A B CC AB BC AC= ⊕ ⊕ = + + +

The RippleThe Ripple--Carry AdderCarry Adder

Propagation Delay is linearly proportional to Ntcarry dominates the propagation delay

Worst case delay: linear with the number of bits td = O(N)

tadder = (N-1)tcarry + tsum

Inverting PropertyInverting Property

( , , ) ( , , )

S A B C S A B C

C A B C C A B C

Inverting all inputs to FA results in inverted values for all outputs

Minimize Critical Path by Reducing Inverting StagesMinimize Critical Path by Reducing Inverting Stages

Exploit Inversion Property

FA FA FA

Even cell Odd cell

Ci,0 Co,0 Co,1 Co,3Co,2

Mirror Adder (1)Mirror Adder (1)

G11111

G10011

P10101

P01001

P10110

P01010

D01100

D00000

statusCoSCiBA

A B Ci

Truth Table for Full Adder

G11111

G10011

P10101

P01001

P10110

P01010

D01100

D00000

statusCoSCiBA

A B Ci

Mirror Adder (2)Mirror Adder (2)Sum

Truth Table for Full Adder

Stick Diagram

A Ci Co Ci A B

Mirror Adder ImplementationMirror Adder Implementation

Mirror Adder SummaryMirror Adder Summary24 Transistors

The NMOS and PMOS chains are completely symmetrical

A maximum of 2 series transistors in carry-generation circuitry

The transistors connected to Ci should be closest to the output

Carry-Stage transistors have to be optimized for speed

Sum-Stage transistors can be optimized for area

The most critical issue is to minimize the capacitance at Co

Co is composed of 4 diffusion capacitances, 2 internal gate

capacitances, and 6 gate capacitances in the connecting adder cell

Sum Generation

Carry Generation

This implementation has similar sum and carry output delay

Transmission Gate Full AdderTransmission Gate Full Adder

VDD CoCi

Manchester CarryManchester Carry--ChainChainManchester Carry Gates

Static Implementation Dynamic Implementation

G3Ci,0

P1 P2 P3

C3C2C1C0

44--Bit Manchester CarryBit Manchester Carry--ChainChain

Pi + 1 Gi + 1 φ

Inverter/Sum Row

Propagate/Generate Row

Pi Gi φ

Ci - 1Ci + 1

Stick Diagram

Manchester CarryManchester Carry--Chain ImplementationChain Implementation

Design for Long Word LengthDesign for Long Word Length

Propagation delay of chain style design is quadratic in the number of bits

Chain style design is NOT practical for long word length (e.g. 32 bits)

FA FA FA FA

P0 G1 P0 G1 P2 G2 P3 G3

Co,3Co,2Co,1Co,0Ci,0

FA FA FA FA

P0 G1 P0 G1 P2 G2 P3 G3

Co,2Co,1Co,0Ci,0

BP=PoP1P2P3

Idea: If (P0 and P1 and P2 and P3 = 1)then Co3 = C0, else “kill” or “generate”.

CarryCarry--Bypass AdderBypass AdderCarry-Skip Adder

Carrypropagation

SetupBit 0–3

M bits

tsetup

Carrypropagation

SetupBit 4–7

tbypass

Carrypropagation

SetupBit 8–11

Carrypropagation

SetupBit 12–15

tadder = tsetup + Mtcarry + (N/M-1)tbypass + (M-1)tcarry + tsum

1616--bit Carrybit Carry--Bypass AdderBypass Adder

N=16 M=4

Carry Ripple versus Carry BypassCarry Ripple versus Carry Bypass

For smaller N, bypass adder is not preferred due to the overhead of bypass multiplexer

Ripple Adder

Bypass Adder

Depends on technology

"0" Carry Propagation

"1" Carry Propagation

Multiplexer

Sum Generation

Co,k-1 Co,k+3

Carry Vector

Linear CarryLinear Carry--Select AdderSelect Adder

Both situations are evaluated

~ 30 % Hardware overhead

Sum Generation

Multiplexer

1-Carry

0-Carry

Ci,0 Co,3 Co,7 Co,11 Co,15

S0–3

Bit 0–3 Bit 4–7 Bit 8–11 Bit 12–15

Sum Generation

Multiplexer

1-Carry

0-Carry

S4–7

Sum Generation

Multiplexer

1-Carry

0-Carry 0-Carry

S8–11

Sum Generation

Multiplexer

1-Carry

S12–15

tadder = tsetup + Mtcarry + (N/M)tmux + tsum

1616--bit Linear Carrybit Linear Carry--Select AdderSelect Adder

N=16 M=4

"0" Carry

"1" Carry

Multiplexer

Sum Generation

"0" Carry

"1" Carry

Multiplexer

Sum Generation

"0" Carry

"1" Carry

Multiplexer

Sum Generation

"0" Carry

"1" Carry

Multiplexer

Sum Generation

Bit 0-1 Bit 2-4 Bit 5-8 Bit 9-13

S0-1 S2-4 S5-8 S9-13

(4) (5) (6) (7)

(3) (4) (5) (6)

S14-19

Bit 14-19

SquareSquare--Root CarryRoot Carry--Select AdderSelect Adder

22 3 ...... ( 1) 2

PN P= + + + + ≅

N bits P stages First Stage has M bitsFor example: 2P N=

tadder = tsetup + Mtcarry + (N/M)tmux + tsum= tsetup + Mtcarry +Ptmux + tsum

Adder Delays Adder Delays -- Comparison Comparison

Square root select

Linear select

Ripple adder

20 40N

t p(in

AN-1, BN-1A1, B1

• • •

• • • SN-1

PN-1Ci, N-1

P0Ci,0 Ci,1

A0, B0

Expanding Lookahead equations:

All the way:

C0,k=Gk+PkC0,k-1

C0,k=Gk+Pk(Gk-1+Pk-1C0,k-2)

C0,k=Gk+Pk(Gk-1+Pk-1(……+P1(G0+P0Ci,0))))))

LookLook--Ahead Ahead -- Basic IdeaBasic Idea

Carry DeterminationCarry DeterminationCo,0=G0+P0Ci,0

Co,1=G1+P1Co,0=G1+P1(G0+P0Ci,0)=G1+P1G0+P1P0Ci,0

Co,2=G2+P2G1+P2P1G0+P2P1P0Ci,0

Co,3=G3+P3G2+P3P2G1+P3P2P1G0+P3P2P1P0Ci,0

44--bit Lookbit Look--Ahead Ahead

Large stack

Poor Performance

Co,0=G0+P0Ci,0

Co,1=G1+P1Co,0

Co,2=G2+P2C0,1

Co,3=G3+P3Co,2

A6A5A4A3A2A1

tp∼ log2(N)

tp∼ N

(g”,p”) (g’,p’)

g=g”+g’p”p=p’p”

Hierarchically DecompositionHierarchically Decomposition

Logarithmic LookLogarithmic Look--Ahead AdderAhead Adder

2logpt N∝

Kogge-Stone tree(A

S 0 S 1 S 2 S 3 S 4 S 5 S 6 S 7 S 8 S 9 S 10 S 11 S 12 S 13 S 14 S 15

MultipliersMultipliers

The Binary MultiplicationThe Binary Multiplication

Partial products

Multiplicand

Multiplier

Result

1 0 1 0 1 0

1 1 1 0 0 1 1 1 0

0 0 0 0 0 0

1 0 1 0 1 0

1 0 1 1

Reduce Partial ProductsReduce Partial Products

Partial products can be reduced by multiplier transformation(Booth’s Recording)

Reduce number of partial products is equivalent to reducing the number of additions

X3 X2 X1 X0

Z3Z6Z7 Z5 Z4

4X4 Bit4X4 Bit--Array MultiplierArray Multiplier

Critical PathCritical Path Y0

X3 X2 X1 X0

Z3Z6Z7 Z5 Z4

For MXN Bit-Array Multiplier

tmultiplier = [ (M-1) + (N-2) ] tcarry + (N-1) tsum + tand

CarryCarry--Save MultiplierSave Multiplier

HA HA HA HA

FAFAFAHA

FAHA FA FA

FAHA FA HA

Vector Merging Adder

tmultiplier = (N-1) tcarry + tand + tmerge

Carry is saved for the next adder stage

Multiplier Multiplier FloorplanFloorplan

SCSCSCSC

Z3Z4Z5Z6Z7

X0X1X2X3

Vector Merging Cell

HA Multiplier Cell

FA Multiplier Cell

X and Y signals are broadcastedthrough the complete array.( )

Carry-Save Multiplier

Rectangular shape is easy for integration

6 5 4 3 2 1 0 6 5 4 3 2 1 0

Partial products First stage

Bit position

6 5 4 3 2 1 0 6 5 4 3 2 1 0Second stage Final adder

(a) (b)

(c) (d)

Partial Products TransformationPartial Products Transformation

WallaceWallace--Tree MultiplierTree MultiplierPartial products

First stage

Second stage

Final adder

FA FA FA

z7 z6 z5 z4 z3 z2 z1 z0

x3y2x2y3

x1y1x3y0 x2y0 x0y1x0y2

x2y2x1y3

x1y2x3y1x0y3 x1y0 x0y0x2y1

Wallace Tree MultiplierWallace Tree MultiplierPros:

Substantial hardware savingReduce propagation delay

Cons:Irregular structureCustomized layout

ShiftersShifters

The Binary ShifterThe Binary Shifter

Right Leftnop

Bit-Slice i

Widely used for floating point units, multiplications by constant numbers

This binary shifter is extremely slow for multi-bit applications

The Barrel ShifterThe Barrel Shifter

Sh3Sh2Sh1Sh0

: Control Wire

: Data Wire

Area Dominated by Control Wiring

Decoder Control Signal

4x4 barrel shifter4x4 barrel shifter

BufferSh3S h2Sh 1Sh0

Widthbarrel ~ 2 pm M

Logarithmic ShifterLogarithmic ShifterSh1 Sh1 Sh2 Sh2 Sh4 Sh4

00--7 bit Logarithmic Shifter7 bit Logarithmic Shifter

mirror adder

Documents

what are a half adder and a full adder

two-operand addition adder...

fpga implementation of borrow save adder under threshold...

ΗΜΥ 307 ΨΗΦΙΑΚΑ ΟΛΟΚΛΗΡΩΜΕΝΑ...

parallel adder

adder presentation

7alu, half-full adder, ripple carry adder

adders - university of richmond · adder with n 1-bit...

chapter # 1: digital circuits - labri · adder half adder...

ee 466/586 vlsi design - washington...

computer arithmetic : adder · computer arithmetic : adder...

ee5311- digital ic design · ee5311- digital ic design ......

implementation of carry skip adder using ptl · pdf...

cse477 vlsi digital circuits fall 2002 lecture 20: adder...

laxmi institute of technology , sarigam · half and full...

skp engineering college -...

power minimization of10tfull adder using sub ... · the...

teaching guide: basic electronics - diism.unisi.it ·...

vlsi l13 adder designs - vlsicad.ucsd.edu l13 adder... ·...

adder, half adder & full adder