lec 6 -- copyright @ 2014 regents of the uc -- page 1ee143/fa14/... · ee 143: microfabrication...
Post on 25-Aug-2020
11 Views
Preview:
TRANSCRIPT
EE 143: Microfabrication Technology CTN 9/16/14
Lecture 6: Process Integration
Lecture in 180 Tan Hall today and from now
on -- ETS can record from this room
•
ETS recording today•
I have Lecture 1 (with poor sound) and
Lecture 5 recorded -- will transfer to ETS
for posting on YouTube
•
Announcements:
------------------------------------------
Example NMOS Process (finish this)•
Masks & Alignment•
Design Rules•
Lecture Topics:
------------------------------------------
Started NMOS process flow•
Last Time:
Lec 6 -- Copyright @ 2014 Regents of the UC -- Page 1
EE 143: Microfabrication Technology CTN 9/16/14
Lec 6 -- Copyright @ 2014 Regents of the UC -- Page 2
EE 143: Microfabrication Technology CTN 9/16/14
Lec 6 -- Copyright @ 2014 Regents of the UC -- Page 3
EE 143: Microfabrication Technology CTN 9/16/14
Lec 6 -- Copyright @ 2014 Regents of the UC -- Page 4
EE 143: Microfabrication Technology CTN 9/16/14
Lec 6 -- Copyright @ 2014 Regents of the UC -- Page 5
EE 143: Microfabrication Technology CTN 9/16/14
Lec 6 -- Copyright @ 2014 Regents of the UC -- Page 6
EE 143: Microfabrication Technology CTN 9/16/14
Lec 6 -- Copyright @ 2014 Regents of the UC -- Page 7
EE 143: Microfabrication Technology CTN 9/16/14
Lec 6 -- Copyright @ 2014 Regents of the UC -- Page 8
EE 143: Microfabrication Technology CTN 9/16/14
Example: NMOS Process
Layout:
Silicon oxidation: target = 100nm1.
LPCVD Si3N4: target = 100nm2.
Lithography: Mask I (active area)3.
Etch Si3N4 to clear it in field areas4.
Field isolation implant: B+ (p-type)5.
Remove PR6.
Grow 1mm of SiO2 by thermal oxidation
(LOCOS oxidation)
7.
Blanket etch all Si3N4 in hot phosphoric acid
wet etchant
8.
Threshold voltage implant: B+ (no mask)9.
Process Flow:
Lec 6 -- Copyright @ 2014 Regents of the UC -- Page 9
EE 143: Microfabrication Technology CTN 9/16/14
Remove 100nm of damaged oxide via a timed
wet etch in hydrofluoric acid (HF)
10.
Grow 100nm of gate thermal oxide in an
ultra-clean furnace
11.
LPCVD situ phosphorous-doped gate polysilicon12.
Lithography: Mask II (gate polysilicon)13.
Dry etch polysilicon to clear the field areas14.
Remove PR15.
D/S ion implantation: P or As (n-type)16.
Oxidize a bit (10nm) and anneal at 1050oC to
activate dopants and drive-in diffusion
17.
LPCVD PSG: target = 1m18.
Reflow PSG (& a little bit of diffusion) at
950oC
19.
Lithography: Mask III (contact hole)20.
Dry/wet etch SiO2 down to n+ S/D regions21.
Sputter Al: target = 1m22.
Lithography: Mask IV (metal)23.
Dry etch Al24.
Deposit via LTO or PECVD Si3N4 to serve as
passivation
25.
Lithography: Mask V (bond pad contacts)26.
Etch passivation layer down to metal27.
(optional) spin double-thick PR over the front
side
28.
Etch backside layers via successive wet
processes (to allow biasing of the substrate)
29.
Through step 2:
Lec 6 -- Copyright @ 2014 Regents of the UC -- Page 10
EE 143: Microfabrication Technology CTN 9/16/14
Through step 5:
Through step 12:
Lec 6 -- Copyright @ 2014 Regents of the UC -- Page 11
EE 143: Microfabrication Technology CTN 9/16/14
Through step 16:
Through step 21:
Lec 6 -- Copyright @ 2014 Regents of the UC -- Page 12
EE 143: Microfabrication Technology CTN 9/16/14
Lec 6 -- Copyright @ 2014 Regents of the UC -- Page 13
EE 143: Microfabrication Technology CTN 9/16/14
Lec 6 -- Copyright @ 2014 Regents of the UC -- Page 14
EE 143: Microfabrication Technology CTN 9/16/14
Lec 6 -- Copyright @ 2014 Regents of the UC -- Page 15
top related