lead frame package design flow using cds … · the world leader in high performance signal...
Post on 30-Jul-2018
230 Views
Preview:
TRANSCRIPT
The World Leader in High Performance Signal Processing Solutions
Lead Frame Package Design flow
using CDS Electronics Packaging
Designer (EPD) and Cadence Chip
Package Design tools
—Analog Devices Confidential Information— 1
Take away from this paper
CAD Design Software’s - Electronics Packaging Designer (EPD) provides the means to bring the lead frame packages into Cadence System in Package (SIP) tools.
SIP tools are integrated with various EM field solvers which provide designers the flexibility to run analysis on an entire package design.
Potential solution for connectivity management.
Empowers the designer to run the analysis on her/his own.
—Analog Devices Confidential Information— 2
3
Virtuoso Layout Chip Top
Allegro AMS Simulator
PSpice
SiP RF Layout
Allegro Design Entry HDL
Pa
ck
ag
e la
yo
ut
Sym
bo
l
Agilent,Sigrity
EPD
Virtuoso Platform
Allegro Platform
3rd Party
SiP
RF
A
rch
itect
Logical Design
Physical Design IC Design Package Design
SiP Design Flow
Automatic Test-bench Generation
Alleg
ro
Lib
rari
an
E
xp
ert
(PD
V)
chip
Bac
k
an
no
tati
on
Co-Design Die
Die.txt
Netlis
tFile
s
Alleg
ro
Lib
rari
an
E
xp
ert
(PD
V)
Die
.txt fi
le
Electronic Package Designer (EPD)
EPD is from the third party vendor CAD Design Software.
EPD is built on AutoCAD tool; it adds intelligence to the package by adding the pin numbers on the package, tack points for wire bond connections and via-type connections at the Gull wings. The Gull wings connect to the PCB substrate.
EPD converts the AutoCAD .dxf file as an input and translates, and instantiates it in a SIP database.
The intelligence built on the lead frame package by EPD facilitates integration with system level electrical simulation tools.
—Analog Devices Confidential Information— 4
The EPD software is built on AutoCAD tools.
It adds extra menu options to the AutoCAD interface; for the
recognition and manipulation of package input files.
—Analog Devices Confidential Information— 5
CDS Menu is
added to the
AutoCAD
menus and
contains
commands to
process Lead
Frame
Designs
User interface to select an existing technology file built on
Custom Environment and Default Design Settings ….
—Analog Devices Confidential Information— 6
The .TCH or ‘Technology File’
contains default settings that
can be shared with other
users. After initial setup, the
New Design Environment and
Settings can be saved to a
configuration file to be used
again.
Create or Modify a Technology file.
—Analog Devices Confidential Information— 7
Set the Environment for
Measurement Units, Design
type, number of Layers and
the Material Stack-up.
Setting the Material Stack-up is
used when Describing the Level
Thickness, and Material Type that
will be used in Cadence. Built-in
and Custom Material Types are
available.
Once the settings with units, material stack-up, thickness
and tolerance is captured the following package drawing
will be loaded into the Design environment.
—Analog Devices Confidential Information— 8
AutoCAD line or Polylines
were used in the DXF to draft
the design. Using Automatic
the EPD tools, the design is
first cleaned up and the
polylines will be ‘Joined’ and
‘Closed’.
Lead Frame Intelligence
software can now analyze the
drawing to make intelligent for
processing and also make
ready for Export to Cadence.
After the cleanup (Join and Closed polylines) and
intelligizing, the package name and pin numbers are
assigned.
—Analog Devices Confidential Information— 9
By specifying which entities
are to be assigned as Metal,
Nets, lead assignments etc,
the LFINTEL command will
block and create the Lead Tips
and Paddels.
The tack points are added for the wire bond attachments
from the die to the package
—Analog Devices Confidential Information— 10
Single or Multiple Tack points
can be automatically added to
the Intelligent Lead Tips.
Additional points may be
added manually.
Translation of the Lead Frame Package and instantiation in
a SIP database
Using the EPD2SKL conversion utility the Lead frame package is converted to the SKILL file.
So <Package_name>.il and EPD2SKL.scr files are available to play.
The lead frame Package appears in the SIP layout XL
—Analog Devices Confidential Information— 11
Lead Frame Package imported into SIP.
—Analog Devices Confidential Information—
The pin numbers are
highlighted in red.
The tack points at
end of the leads for
wirebond
connection from the
die.
The gull wings at the
backend of the Lead
connects to the substrate
Lead Frame Package with the die placed in the package
—Analog Devices Confidential Information— 13
Die Placed in newly
imported Lead Frame
Lead frame Package with the die and the wire bonds
attached. Once the Package is in SIP, bring the Die from the
schematic front end, place the die in the package and start
wire bonding to the package.
—Analog Devices Confidential Information— 14
Connectivity (Method 1)
The netlist file is generated from SIP. For smaller Packages the net names for the wirebonds and the connectivity between the die and the package can be checked.
—Analog Devices Confidential Information— 15
Connectivity (Method 2)
—Analog Devices Confidential Information— 16
Schematic symbol for the die
and the package.
Die and the Package in SIP
with rats-nest attached.
Connectivity Driven Bonding diagram
—Analog Devices Confidential Information— 17
3D Viewer in SIP
—Analog Devices Confidential Information— 18
Assembly rules in SIP
—Analog Devices Confidential Information— 19
Constraint Manager in SIP
—Analog Devices Confidential Information— 20
Reports generated in SIP
—Analog Devices Confidential Information— 21
Export to Agilent ADS Momentum and
Sigrity tools
—Analog Devices Confidential Information— 22
Lead Frame Package in ADS Momentum
—Analog Devices Confidential Information— 23
Cookie cutter section of the
package in ADS. Full package in ADS
Summarize advantages of bringing
Leadframe Package in SIP
Connectivity management for the Die and the package.
Ability to generate the connectivity driven bonding diagram.
3D capability enhances the view of wire loops, vertical and
horizontal separations of wire bonds.
Access to assembly rules checker with about 40 assembly
rule checks
Wire bond reporting with Net Name, Pin numbers, Finger
Name, wire angle etc
Robust constraint management tool for all physical and
spacing constraints
Ability to export the Die and the Package data to Simulation
tools
—Analog Devices Confidential Information— 24
Conclusion
The Sub-Contractors changing the design on is a biggest issue at present which can be avoided if we have greater control and verify everything at our end, before it goes to the sub-contractor
This solution gives ADI greater control of the design database from early design exploration, through physical implementation to functional verification - by providing access to connectivity management, constraint management, simulation tools, and assembly rules checks.
The control over design database is extremely important through out the design cycle to avoid many iterations with the Sub-Contractors
—Analog Devices Confidential Information—
Conclusion Continued…
The entire design process flow is less error prone due to the efficiency gained in this solution.
This solution not ONLY offers greater control of the design database to the business units/product lines, it also considerably reduces design cycle time, improves efficiency and overall product delivery to the ADI customer; thereby improving the Time to Market.
—Analog Devices Confidential Information—
top related