latch versus register latch stores data when clock is low d clk q d q register stores data when...
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Latch
stores data when clock is low
D
Clk
Q D
Clk
Q
• Register
stores data when clock rises
Clk Clk
D D
Q Q
In
clk
In
Out
Positive Latch
CLK
DG
Q
Out
Outstable
Outfollows In
In
clk
In
Out
Negative Latch
CLK
DG
Q
Out
Outstable
Outfollows In
• N latch is transparentwhen = 0
• P latch is transparent when = 1
NLatch
Logic
Logic
PLatch
t
CLK
t
D
tc 2 q
tholdtsu
t
Q DATASTABLE
DATASTABLE
Register
CLK
D Q
Vi1 Vo2
Vo2 =Vi1
Vo1 =Vi2
Vo1
Vi2
5Vo1
Vi2
5Vo1
Vi1
A
C
B
Vo2
Vi1=Vo2
Vo1 Vi2
Vi2=Vo1
Gain should be larger than 1 in the transition region
A
C
d
B
Vi2
5V
o1
Vi1 5Vo2
A
C
d
B
Vi2
5V
o1
Vi1 5Vo2
CLK
CLK
CLK
D
Q D
CLK
CLK
D
Converting into a MUXForcing the state(can implement as NMOS-only)
Use the clock as a decoupling signal, that distinguishes between the transparent and opaque states
5.8
Cascade connection of pass transistors
V V V V
V Vo
R
C
R
C
R
C
R
C
= RC • n(n+1)/2, n: number of stages(transistors) 1/2 • n2 • RC
Vo can reach up to V-VTN
V
V
V
V Vo
Vo(high) = V-3VTN
Output of pass transistor better not be used as control variable for another gate.
Cases where pass tr. is appropriate Multiplexer
A
B
S
S
S
5.10
4-input Multiplexer using CMOS switch concept
Removing contacting & interconnecting wire segments saves space.
Y
•A conducting path must not exist between twodifferent inputs which could take different logiclevels.
•If there is an overlap between 1 and 2, the
intermediate node “y” will take an undefined
potential, located between the 1 and 0.
•This potential will give rise to an erratic behavior
of the logic, although it may not be detected by a
switch-level simulator
This problem can be solved by designing control
signal with a mutual exclusion feature
Rules for transmission gate logic construction 1
X1
X1
1
2
5.12
Rules for transmission gate logic construction 2
•When a branch has several transmission-gates in series, internal nodescan behave as a dynamic memory
•Such a gate cannot be considered as a pure static combinational logic gate,because the memory effect can give rise to false outputs, according to thehistory of successive inputs and control levels, Moreover, the output couldbe at high impedance if no buffer has been provided.•This behavior dramatically increases the simulation and test problems
5.13
Rules for transmission gate logic construction 3
1
a
a
aa
1
0
X1
X2
X1
X2
•To avoid undesired high impedance states, care should be taken toalways provide at least one conducting path between an input andthe output•The input variable sources must be low-impedance sources for thesame reason
Ex) 1-to-2 decoder
wrong good
Negative latch(transparent when CLK= 0)
Positive latch(transparent when CLK= 1)
CLK
1
0D
Q 0
CLK
1D
Q
InClkQClkQ InClkQClkQ
CLK
CLK
CLK
D
Q
CLK
CLK
CLK
CLK
QM
QM
NMOS only Non-overlapping clocks
1
0D
CLK
QM
Master
0
1
CLK
Q
Slave
QM
Q
D
Two opposite latches trigger on edgeAlso called master-slave latch pair
QM
Q
D
CLK
T2I2
T1I1
I3 T4I5
T3I4
I6
Multiplexer-based latch pair
Combinational logic circuit
Basic LatchBoth circuit are
the sameThe only feedback
path is the red line
Reset
Set
Qa
Qb
Reset
SetQb
Qa
Basic LatchConsider Set = 0, Reset =0
Reset
Set
Qa
Qb
0
0
Qb’ = Qa
Qa’ = Qb
Basic LatchConsider S = 1, R =0
As S=1, NOR1 output must be 0As NOR1 ouput = 0 and R =0, NOR2
output must be 1
NOR2
NOR 1
Reset
Set
Qa
Qb
0
1
1
0
Basic LatchConsider S = 0, R =1
As R = 1, NOR2 output must be 0
NOR2
NOR 1
Reset
Set
Qa
Qb
1
0
0
Basic LatchConsider R = 1 and S =1
As R = 1, NOR2 output must be 0As S = 1, NOR1 output must be 0
NOR2
NOR 1
Reset
Set
Qa
Qb
1
1
0
0
Level sensitive and edge sensitiveFor a latch and flip-flop (FF), it can be level
sensitive or edge sensitiveLevel sensitive means the latch / FF will copy
input D to output Q when Clk = 1Edge sensitive means that the latch / FF will
only copy input D to output Q when Clk change from 0 -> 1 (positive edge trigger) / 1 -> 0 (negative edge trigger)
Level sensitive
Clk
D
Q
Edge sensitive
Clk
D
Q
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