k.c.ravindran,grapes-3 experiment,ooty 1 development of fast electronics for the grapes-3 experiment...

K.C.RAVINDRAN,GRAPES-3 EXPERIMENT,OOTY 1

Development of fast electronics for the

GRAPES-3 experiment at Ooty

K.C. RAVINDRAN

On Behalf of GRAPES-3 Collaboration

K.C.RAVINDRAN,GRAPES-3 EXPERIMENT,OOTY 2

• 8 Channel Discriminator • 8 Channel Combined Amplifier and

discriminator• 32 Channel Time to Digital Converter (TDC)• 32 Channel High Performance TDC (HPTDC)• 4 Fold Logic Unit

GENERAL• Quad Gated Scaler • JTAG protocol in Parallel port

FAST Electronics DEVELOPMENT AND PERFORMANCE

K.C.RAVINDRAN,GRAPES-3 EXPERIMENT,OOTY 3

Basic elements for each scintillation detector

Philips TDC

GRAPES TDC

Needs JTAG

K.C.RAVINDRAN,GRAPES-3 EXPERIMENT,OOTY 4

8 Channel discriminator module development

• Dual comparator by Analog Devices (AD96687)

• Characteristics– Propagation delay = 2.5 ns,– Dispersion = 50 ps (for overdrive 100mV - 1V)– ECL outputs– Power dissipation: 118 mW per channel

K.C.RAVINDRAN,GRAPES-3 EXPERIMENT,OOTY 5

Performance of discriminator

Muon

Philips TDC

Model- 7186

TDC Resolution- 25ps

K.C.RAVINDRAN,GRAPES-3 EXPERIMENT,OOTY 6

Time distribution with muon trigger

FWHM=4.9ns

K.C.RAVINDRAN,GRAPES-3 EXPERIMENT,OOTY 7

Relative time distribution of 2 channels of GRAPES discriminator

K.C.RAVINDRAN,GRAPES-3 EXPERIMENT,OOTY 8

Relative time distribution between Lecroy and GRAPES discriminator

K.C.RAVINDRAN,GRAPES-3 EXPERIMENT,OOTY 9

K.C.RAVINDRAN,GRAPES-3 EXPERIMENT,OOTY 10

SUMMARY

• The timing error 125 -135 ps with muon trigger– represents combined statistical widths of two separate

distributions– Timing error due to intrinsic width of GRAPES discriminator

is ~ 100 ps• Intrinsic double pulse resolution of GRAPES

discriminator is 4 ns

• Future Upgrade• Maxim comparator MAX9693EPE

• Propagation delay =1.2ns

• Delay dispersion = 150ps (for overdrive: 10mv-100mv)

• ECL outputs

• 350mW per channel

• Sample IC is being tested , same pin configuration

• Cost effective & expect better performance

K.C.RAVINDRAN,GRAPES-3 EXPERIMENT,OOTY 11

GRAPES Discriminator Module

K.C.RAVINDRAN,GRAPES-3 EXPERIMENT,OOTY 12

Development of Fast Amplifiers

Specifications AD8350-20 LMH6626

Manufacturer Analog National

Bandwidth at Gain=10 700 MHz. 200 MHz

Slew Rate 2000V / μs 350V / μs

Input Impedance 200 Ω 4.6 kΩ

Output Impedance 200 Ω 10 mΩ

K.C.RAVINDRAN,GRAPES-3 EXPERIMENT,OOTY 13

Performance of Combined GRAPES Amplifier & Discriminator Module

Muon

K.C.RAVINDRAN,GRAPES-3 EXPERIMENT,OOTY 14

Performance: Timing response to Muons

σ =3ns σ =3.1ns σ =3ns

Philips Philips GRAPES-8350 GRAPES-LMH6626

K.C.RAVINDRAN,GRAPES-3 EXPERIMENT,OOTY 15

Intrinsic timing response using Muons

σ=128ps σ=178ps

Difference distribution

Philips & GRAPES-8350

Difference distribution

Philips & GRAPES-LMH6626

K.C.RAVINDRAN,GRAPES-3 EXPERIMENT,OOTY 16

Summary

• Fast intrinsic timing response of ~125 ps– Timing response comparable to commercial module

• Standard NIM Module• Highly customized (but still modular) to GRAPES

needs– On-board NIM/TTL converter with monoshots– Multiple buffered outputs as per our experimental

requirement

• Highly cost effective• No delays in repair• Low power consumption

– Almost half compared to commercial modules

• Amplifier and Discriminator in same module– Cost saving on connectors

K.C.RAVINDRAN,GRAPES-3 EXPERIMENT,OOTY 17

8-Channel GRAPES LMH6626 Amplifier & Discriminator Module

K.C.RAVINDRAN,GRAPES-3 EXPERIMENT,OOTY 18

Time to Digital Converter (TDC) Development

Based on TDC32 ASIC ChipDeveloped by Micro Electronics Group of

CERN, GenevaTrigger mode operation Multi-hit capability Number of channels: 32 + 1 Common start Time resolution = 520ps @60MHz Dynamic range: 21 bits Double pulse resolution: 15ns

K.C.RAVINDRAN,GRAPES-3 EXPERIMENT,OOTY 19

Block Diagram of Calibration SetupCalibration Module

40MHz

32MHz

25MHz

20MHz

16MHz

10MHz

Selection of CrystalNumber of SamplesInterval between samplesMax Delay

Control Signals from Computer

START

STOP

PHILLIPS TDC Module

START

Ch. 1Ch. 2

Ch. 16

FANOUT Module

FANOUT Module

GRAPES TDC Module

START

Ch. 1Ch. 2

Ch. 32

K.C.RAVINDRAN,GRAPES-3 EXPERIMENT,OOTY 20

Non-linearity of TDC

Phillips

GRAPES TDC

K.C.RAVINDRAN,GRAPES-3 EXPERIMENT,OOTY 21

GRAPES and PHILLIPS TDCs with real data!

EAS DATA OF SAME CHANNEL

K.C.RAVINDRAN,GRAPES-3 EXPERIMENT,OOTY 22

GRAPES TDC32 Module

K.C.RAVINDRAN,GRAPES-3 EXPERIMENT,OOTY 23

Further TDC Upgrade plansTDC32 Resolution

depends on clock- max 60 MHz At 60 MHz 520 ps

86 pin PLCC package TTL standard Power: 5 V 127 bits of data in

JTAG protocol

HPTDC

Basic clock 40 MHz In built PLL-programable resolution programmable to

24 ps (8 ch), 98 ps, 195 ps & 781 ps

225 pin BGA package LVDS & LVTTL Power: 2.5 V and 3.3 V ~1K bits of data to program Highly flexible

programming complexity

K.C.RAVINDRAN,GRAPES-3 EXPERIMENT,OOTY 24

Development of Logic Unit• Flexible Four fold logic unit

– Logic AND/OR operation

• Low propagation delay(16ns)

• Multiple NIM outputs with either polarity

• Provision of Veto

• Inputs: switch selectable

K.C.RAVINDRAN,GRAPES-3 EXPERIMENT,OOTY 25

QUAD gated scalar• Four independent, 8 digit

channels• Maximum input frequency=3 MHz• Operation with TTL or NIM inputs• Gated timer mode operation• Selectable timer 1-9999 s• Carry available for cascading the

counters

K.C.RAVINDRAN,GRAPES-3 EXPERIMENT,OOTY 26

R&D work in progress• HPTDC work PCB ready 225 pin BGA chip mounted & PCB wired - start

testing • Testing the Amplifier with LMH6703 and

integrating with discriminator MAX9693 Amplifier tested in wired board - bandwidth 400

MHz measured at gain 10 Test MAX9693 Design and fabricate PCB and avoid Lemo

connectors• QDC development in progress

K.C.RAVINDRAN,GRAPES-3 EXPERIMENT,OOTY 27

THANKS

K.C.RAVINDRAN,GRAPES-3 EXPERIMENT,OOTY 28

PCI Interface card• The PC’s which are available now does not have ISA

bus support• ALS systems manufactures prototyping PCI cards• The local address bus , data bus and control signals like

read and write are available to user• We could read data at 1 µs / word using this card in our

DAS• A common PCI Interface card designed and wired and

used in all our DAS at Grapes-3• This card costs around Rs 5,500/- and the card from

Japan PCI-7200 which is a PCI, I/O card costs around Rs 12,000/-

K.C.RAVINDRAN,GRAPES-3 EXPERIMENT,OOTY 29

K.C.RAVINDRAN,GRAPES-3 EXPERIMENT,OOTY 30

THANKS

K.C.RAVINDRAN,GRAPES-3 EXPERIMENT,OOTY 31

CABLE ATTENUATION/100 m

100 METER CABLE COMPARISION

-45

-40

-35

-30

-25

-20

-15

-10

-5

0

0 100 200 300 400 500

Frequency in MHz

Att

n. in

dB

5D2V

RG58/U

K.C.RAVINDRAN,GRAPES-3 EXPERIMENT,OOTY 32

K.C.RAVINDRAN,GRAPES-3 EXPERIMENT,OOTY 33

Comparison of power requirement for Phillips and CRL module

Power supply Voltage

Philips 16 ch Amp 776

Current mA

Phillips 16 ch Disc.706

Current mA

CRL 8 Ch Amp-Disc

Current mA

+6 320 400 700

-6 320 450 500

+12 150 50

-12 150 165

+24 - 80

-24 - 80

K.C.RAVINDRAN,GRAPES-3 EXPERIMENT,OOTY 34

Trigger Rate at Grapes-3 with ~400 scintillation detectors

• Level-0 ~ 100 Hz

• Level-1 ~ 28 Hz

• Calibration ~ 5 Hz

• Pedestal ~ 1 Hz