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ICEPT Short Course on Heterogeneous IntegrationICEPT Short Course on Heterogeneous Integration
Heterogeneous Integration Roadmap WorkshopDriving Force and Enabling Technology for Systems of the Future
Presented by Dr. W. R. Bottoms
Co-Chair, Heterogeneous Integration Roadmapbill_bottoms@3mts.com
eps.ieee.org/hir
ICEPT Short Course on Heterogeneous Integration
Objectives of the Course
Introduce the Heterogeneous Integration Roadmap to an audience that has not been broadly engaged in Technology Roadmapping processes.
Increase the participation of technology leaders in academia and industry from the region in developing future editions of the HIR.
Recruit new participants in the Technical Working Groups to ensure that we maintain a world wide perspective on issues that impact the pace of progress in the post “Moore’s Law” world.
Stimulate Conversations during and after ICEPT 2019 on Roadmapping and how it can be used to accelerate progress in region
ICEPT Short Course on Heterogeneous Integration
Hong Kong is Investing to support growth of the Microelectronics Sector
Hong Kong’s Government is now building a series of initiatives to help revive Hong Kong’s microelectronics eco-system.
The Hong Kong government has committed HK$2Bn to build cleanrooms for microelectronics.
ICEPT Short Course on Heterogeneous Integration
Course OutlinePart One
Introduction and brief history of Semiconductor technologyHeterogeneous Integration is the path forwardHeterogeneous Integration in the smartphoneHeterogeneous integration in high performance applicationsIntroduction to the Heterogeneous Integration RoadmapSummary
ICEPT Short Course on Heterogeneous IntegrationICEPT Short Course on Heterogeneous Integration
Introduction and brief history of the Semiconductor technology
ICEPT Short Course on Heterogeneous Integration5
Point Contact Transistor 1947Shockley, Brattain and Bardeen
1st Integrated Circuit 1958 Jack Kilby
1st FinFet 1998 Hiamoto et al
11 years
First CMOS IC 1963Frank Wanlass
5 years
Moore’s Law 1965
2 yrs
33 years???????3D Heterogeneous system integration
at the package level
Our Industry has reinvented itself many times
ICEPT Short Course on Heterogeneous Integration
54 Years After Moore’s Law The World Has Changed...
CMOS Scaling Is no longer Driving The Pace Of ProgressThe ITRS Is Over
We are entering a period of technology chaos driving new ideas that increase the pace of innovation
….the world has evolved and is
changing in ways never imagined.
ICEPT Short Course on Heterogeneous Integration
40 Year DRAM Memory Capacity IncreaseJohn Hennessy at DARPA ERI Conference July 2018
Progress in functional density has slowed
ICEPT Short Course on Heterogeneous Integration
40 Years Of Progress In ComputingJohn Hennessy at DARPA ERI Conference July 2018
Progress in performance has slowed
ICEPT Short Course on Heterogeneous Integration
2006• Exxon Mobil
• General Electric
• Gazprom
Microsoft
• Citicorp
• Bank of America
• Royal Dutch Shell
• BP
• Petro China
• HSBC
2018Apple
Amazon
Alphabet (Google)
Microsoft
Alibaba
• Berkshire Hathaway
Tencent Holdings
• JP Morgan Chase
• ExxonMobile
Companies In The Increasingly Connected WorldWorld’s 10 largest Companies Sources: The Economist, Statista
Change is driven by explosive growth in data generated & global network traffic
Structure of the economy has changed
ICEPT Short Course on Heterogeneous Integration
Technology Roadmapping History1991World’s first Open Source Technology Roadmap, the National Technology Roadmap for Semiconductors (NTRS) sponsored by the US Semiconductor Industry Association 1998NTRS expanded forming the first Global Technology Roadmap. Europe, Japan, Taiwan, and Korea joined. It was renamed International Technology Roadmap for Semiconductors (ITRS).
2014 The benefits of Moore’s Law scaling were diminishing and decision was made to end ITRS.
2016The last edition of the ITRS was published July 8, 2016
ICEPT Short Course on Heterogeneous Integration
Technology Roadmapping History
In March of 2015 the ITRS Heterogeneous Integration Focus Team signed a Memorandum of
Understanding with the IEEE CPMT Society initiating the formation of the Heterogeneous
Integration Roadmap
ICEPT Short Course on Heterogeneous Integration
With Moore’s Law Scaling Benefits Slowing,The US Semiconductor Industry Association Introduced Heterogeneous Integration To
The ITRS in Bad Nauheim, Germany In 2014
A Focus Team for Heterogeneous Integration was established
ICEPT Short Course on Heterogeneous Integration
Selected Slides from the 2014 presentation in Bad Nauheim
ICEPT Short Course on Heterogeneous Integration
A Quote from Gordon Moore’s 1965 Paper“Cramming more components into integrated circuits”
Gordon Moore, Electronics, April 19, 1965
“It may prove to be more economical to build large systems out of smaller functions, which are separately packaged and interconnected. The availability of large functions, combined with functional design and construction, should allow the manufacturer of large systems to design and construct a considerable variety of equipment both rapidly and economically.”
Was Gordon Moore thinking & talking about SiP & Heterogeneous Integration?
BB1
Slide 15
BB1 chect Chappels ERI presentationBill Bottoms, 8/8/2019
ICEPT Short Course on Heterogeneous Integration
Heterogeneous Integration refers to the integration of separatelymanufactured components into a higher level assembly system-in-package (SiP) that, in the aggregate, provides enhancedfunctionality and improved operating characteristics.
Source ITRS 2.0
Heterogeneous Integration Defined
In this definition, components should be taken to mean any unit whether individual die, MEMS device, passive component, assembled package or sub-system that are integrated into a single package. The operating characteristics should also be taken in its broadest
meaning including characteristics such as system level performance and cost of ownership.
ICEPT Short Course on Heterogeneous Integration
Drivers For Progress & Innovation Are Changing
Migration of Data, Logic and Applications to the Cloud
The Internet of Everything
Consumerization of IT with the rise of Social Media
Revolution in our Mobile Devices
The Internet of Things
Big Data and Artificial Intelligence
ICEPT Short Course on Heterogeneous Integration
Drivers For Progress & Innovation Are Changing
Migration of Data, Logic and Applications to the Cloud
The Internet of Everything
Consumerization of IT with the rise of Social Media
Revolution in our Mobile Devices
The Internet of Things
Big Data and Artificial Intelligence
Imagination is a required Characteristic for RoadmappingBut it must be informed by technical expertise
ICEPT Short Course on Heterogeneous Integration
Key Factors Limiting Future Progress
Cost Thermal density Co-Design and simulation Power requirements Cross talk Physical density of bandwidthWarpage
ICEPT Short Course on Heterogeneous Integration
Key Factors Limiting Future Progress
Cost Thermal density Co-Design and simulation Power requirements Cross talk Physical density of bandwidthWarpage
The solutions to each of these problems involves new arechitectures, new materials, new
processes and new equipment
ICEPT Short Course on Heterogeneous IntegrationICEPT Short Course on Heterogeneous Integration
Heterogeneous Integration is the path forward
ICEPT Short Course on Heterogeneous Integration
Semiconductor Research Opportunities“An Industry Vision & Guide”
“The path forward is not as clear as it was during theMoore’s Law era. However, there is enormous potentialfor economic and societal benefits—some that areenvisioned and others yet to be imagined.”
SIA & SRC March 2017
ICEPT Short Course on Heterogeneous Integration
Heterogeneous Integration Has Replaced Moore’s Law Scaling As The “Low Hanging
Fruit” In The Drive To Maintain The Pace Of Progress
ICEPT Short Course on Heterogeneous IntegrationICEPT Short Course on Heterogeneous Integration
Heterogeneous Integration in the smartphone
ICEPT Short Course on Heterogeneous Integration
SiP Modules in Smart Phone Heterogeneous Integration
RF/FEM
Sensor
StorageCPU/MCUWireless
MEMS
Power Management
DC/DC PMIC
ComboWiFi, BT, GPS, FM
BroadbandWiMAX
Integration / MiniaturizationOptimization / Simplification
FEMPAM Tx/Rx
Camera Module Biometric Sensor
Component FlashMicro SSDHigh BW PoP 2.5D/3D TSV
Source: IOT Fuse Conference-2016 –Gerber ASE
ICEPT Short Course on Heterogeneous Integration
The Definition of Heterogeneous IntegrationDie 1
28nm/Fab 1Logic
Die 240nm/Fab 2
Analog
Die 320nm/Fab 3Memory
Silicon active Components
SawFilter
Die 414nm/Fab4Power
Compound active Components
MEMS Sensor
Mechanical active Components
Passive Components
+
+
+
Die 128nm/Fab 1
Logic
Die 240nm/Fab 2
Analog
Die 320nm/Fab 3Memory
SawFilter
Die 414nm/Fab4Power
MEMS SensorIntegration
Heterogeneous by material, component type, circuit type, node and bonding/interconnect method
ICEPT Short Course on Heterogeneous Integration
1970 1980 1990 2000 2010 2020 2030
10 um
1 um
3 um
0.35 um
90 nm
28 nm7 nm
3 nm
0.8 um
DIP
QFP
BGAFC BGA
SiP
System Innovation and Heterogeneous IntegrationSiP: Package Integration
SOC : Chip Integration
System Integration
HeterogeneousIntegration
Techno
logy Nod
e Co
mplexity
1 nm
ICEPT Short Course on Heterogeneous Integration
Purpose and Theme of The Heterogeneous Integration Roadmap
Maintain the pace of progress needed for electronic systems today and tomorrow by integration of separately manufactured
components into a higher level assembly that provides enhanced functionality and improved operating characteristics.
ICEPT Short Course on Heterogeneous IntegrationICEPT Short Course on Heterogeneous Integration
Heterogeneous Integration in the smartphone
ICEPT Short Course on Heterogeneous Integration
Apple iPhone X Main Board
Main processor A11 in PoP 8 other SiPs
11 WLCSPs
Teardowns of APPLE’S XSMax, Samsung Galaxy S9+ and Huawei 20 Pro all show similar adoption of leading edge Heterogeneous Integration
Source Prismark Partners
ICEPT Short Course on Heterogeneous IntegrationICEPT Short Course on Heterogeneous Integration
Heterogeneous Integration in High Performance Applications
ICEPT Short Course on Heterogeneous Integration
System Advantages of AMD 2.5D Heterogeneous Integration
Advanced node ASICHigh Bandwidth memory stacksAdvantages of Smaller size, lower power, and higher bandwidth
ICEPT Short Course on Heterogeneous Integration
Heterogeneous Integration enables Higher Yield
As nodes shrink and die size increases yield drops. Heterogeneous integration of smaller tightly coupled die instead of a large monolithic ICs may increase yield and bandwidth. It was first demonstrated by Xilinx partitioning an FPGA into multiple die which were integrated on a silicon interposer.
ICEPT Short Course on Heterogeneous Integration
Two Generations of the AMD EPYC Server Processor
Left is large die split into 4 “chiplets” tightly coupled on an organic substrate (14Ƞm)
Right are 4 groups of 2 “chiplets” (7Ƞm) on each side of larger I/O die (14Ƞm) tightly coupled on an organic substrate
ICEPT Short Course on Heterogeneous Integration
Intel’s Embedded Multi-die Interconnect Bridge
EMIB is high bandwidth link between multiple die of different nodes and circuit types on organic substrate
EMIB example: Intel Kaby Lake G card with Intel CPU, AMD GPU and 4GB HBM2.
ICEPT Short Course on Heterogeneous IntegrationICEPT Short Course on Heterogeneous Integration
Introduction to the Heterogeneous Integration
Roadmap
The Heterogeneous Integration Roadmap Established Institutional Sponsorship in 2016
Founded with Initiative from the IEEE Societies, SEMI and ASME EPPD
Embracing innovation wherever it arises and promoting pre-competitive collaboration whenever possible to accelerate progress.
The International Technology Roadmap for Wide Bandgap Power Semiconductors (ITRW) has been a collaborating partner since 2016.
HIR Global Advisory Council Ajit Manocha - President and CEO of SEMI. Former CEO of GlobalFoundries
and served as chair of SIA. Also served in executive roles at Philips/NXP & Spansion.
Nicky Lu - Founder and Chairman of Etron Technology in Taiwan. Served as chair of TSIA and WSC and is a member of the US National Academy of Engineering.
Babak Sabi - Intel Corporation Corporate Vice President, General Manager, Assembly Test Technology Development.
Hubert Lakner - Board of Directors Chairman, Fraunhofer Microelectronics Group and Founding Director of Fraunhofer Institute of Photonic Microsystems (IPMS) in Dresden.
HIR International Roadmap Committee
– William (Bill) Chen, ASE Fellow & Senior Technical Advisor, (Chair)– W. R Bottoms, Chairman 3MTS (Co-Chair representing EPS)– Subramanian Iyer, Distinguished Professor UCLA (representing EDS)– Amr Helmy, Chair Professor , U Toronto (Representing Photonics) – Tom Salmon, VP SEMI Collaboration Platform (Representing SEMI)– Ravi Mahajan, INTEL Fellow (Representing ASME EPPD)– Gamal Refai-Ahmed, Distinguished Engineer Xilinx (ASME EPPD alternate)
ICEPT Short Course on Heterogeneous Integration
HI for Market Applications Mobile IoT Medical, Health & Wearables Automotive High Performance Computing & Data Center Aerospace & Defense
Heterogeneous Integration Components Single Chip and Multi Chip Packaging
(including Substrates) Integrated Photonics Integrated Power Electronics MEMS & Sensor integration RF and Analog Mixed Signal
Cross Cutting topics Materials & Emerging Research Materials Emerging Research Devices Interconnect Test Supply Chain Security Thermal Management
Integration Processes SiP 3D +2.5D WLP (fan in and fan out)
Design Co‐Design & Simulation – Tools & Practice
HIR’s 23 Technical Working Groups
ICEPT Short Course on Heterogeneous Integration
HIR 2019 Event Schedule 1. Heterogeneous Integration Roadmap Symposium Milpitas, CA 2/21/20192. SEMICON China, Shanghai, China CSTIC 3/18-19/20193. EuroSimE Hannover, Germany 3/24-27/20194. ICEP Niigata 4/17-20/20195. ECIO Ghent, Belgium 4/24-26/20196. Advanced Semiconductor Manufacturing Conference 5/6-9/195.8. ECTC & ITherm Las Vegas, NV 5/28-31/20199. NordPac Denmark 6/11-13/201910. Palo Alto Workshop, Palo Alto, CA, July 8, 201911. SEMICON West San Francisco, CA 7/9-11/201912. ICEPT Hong Kong 8/11-15/201913. Electronics Packaging Symposium Niskayuna, NY 9/201914. HIR Workshop with EPS Japan, JIEP & SEMI Japan Tokyo, Japan TBD15. IMAPS Boston, MA 10/1-3/201916. International Test Conference Washington D.C., 11/12-14/201917. INTERPACK 2019 Anaheim, CA 10/7-9/201918. IMPACT Taiwan 10/24-26/201919. SEMICON Europa Germany 11/12-15/201920. ICSJ Kyoto, Japan 11/18-20/201921. IEDM, CA 12/9-11/2019
ICEPT Short Course on Heterogeneous Integration
ConclusionThere are many difficult challenges to be overcome to realizethe potential for 3D System in Package architecture withHeterogeneous Integration.
The Heterogeneous Integration Roadmap exists to identify thesechallenges and potential solutions, if they are known, well inadvance to stimulate precompetitive collaboration.
This new era will support a “Moore’s Law” rate of progress orbetter for decades to come.
ICEPT Short Course on Heterogeneous Integration
SummaryI leave you with three summarizing thoughts
1. Progress paced by Moore’s Law with focus on CMOS is reaching its economic end.
2. There is immense need for pre-competitive technology roadmaps addressing future vision, difficult challenges, & potential solutions
3. HIR is focused on system level integration at the package level addressing emerging markets and enabling continued progress at the rate of Moore’s Law for decades to come.
ICEPT Short Course on Heterogeneous Integration
Part IISystem Level Integration Will Drive
Fundamental Change in Manufacturing
ICEPT Short Course on Heterogeneous Integration
Early Semiconductor Manufacturing
Initially focus was on improving performance and decreasing size and power of ICs.
Processes were:– Thermal evaporation for metal– Thermal oxidation for insulators– Lithography used Rubylithe contact masks– Thermal diffusion for doping
Manufacturing data collection was manualDesigns had no standards and bipolar
transistors dominated.Bob Noyce, Gordon Moore and Andy GroveWith rubylithe IC mask pattern
ICEPT Short Course on Heterogeneous Integration
As Transistor Count Changed from 10s to 1,000,000s Everything Changed
Focus shifted to changes in clean rooms, particle control and new processes and materials to support progress at the pace of Moore’s Law.
Processes were:– Sputtering for metal– Thermal oxidation and spin-on dielectrics– Automated mask making equipment and non-contact
masks for lithography– Ion implantation for doping
Manufacturing data was collection automatically Designs were more standard and CMOS
transistors dominated.
ICEPT Short Course on Heterogeneous Integration
As the benefits of Moore’s law scaling begin to slow a new path to maintain progress is needed.
The solution is to move all system electronic components as close together as possible and
interconnect with other systems through integrated photonics.
ICEPT Short Course on Heterogeneous Integration
Heterogeneous Integration Products Have Been Shipping For Years
ICEPT Short Course on Heterogeneous Integration
Xilinx’s Heterogeneous Integration Example with Si Interposer
Silicon interposer with TSVs to handle communication between HBM stack and FPGA
Source: Xilinx.
ICEPT Short Course on Heterogeneous Integration
3D integration of image sensors, memory and logic– In production today
3D memory stacking– HBM2 in production today at Samsung and SK Hynix– HBM from Micron by next year
Intel’s Foveros TSMC’s CoW, WoW, and SoIC
– System on Integrated Chip (SoIC) 3D stack using CoW process to handle <10µm bond pitch between chips
– Two-die stack face-to-face (F2F) and a three die stack
– Use of hybrid bonding New forms of 3D stacking (die-to-die
interconnects) are coming– Die-to-die attach– Die-to-wafer attach– Wafer-to-wafer attach
3D Integration Is Here Today
Source: TSMC.
WoW
Source: Intel.
Foveros
ICEPT Short Course on Heterogeneous Integration
FO-WLP On SubstrateASE’s Fan-Out Chip on Substrate (FOCoS)
– RDL with 2µm/2.5 L/S– Up to 3 RDLs plus UBM– High I/O (>1,000)– Production for Hi-Silicon since 2016, new customers expected
TSMC Integrated Fan-Out WLP on Substrate (InFO_oS)– RDL with 2µm L/S– Up to 3 RDLs plus UBM– In production or MediaTek Switch (homogeneous integration)– InFO_MS next for heterogeneous solution
Amkor’s Silicon Wafer Integrated Fan-out Technology (SWIFT®) – RDL with 2/2µm L/S– Up to 3 RDLs plus UBM– Potential customers in 2019 Source: ASE.
ICEPT Short Course on Heterogeneous Integration
A Path To Maintain The Pace Of Progress
There will continue to be some progress with scaling CMOS but it cannot maintain the pace of progress.
Progress at the CMOS IC level is approaching its end but we can apply the “CMOS scaling” approach for decreasing power requirements while expanding performance and functional density at the product level.
Start with the system and change everything by moving to system level integration to the package.
ICEPT Short Course on Heterogeneous Integration
Convergence to Complex 3D SiP
Wafer Bumping
WLCSP
Flip Chip Assembly
Wafer Level MEMS
Fan Out
Fan Out 3D
2.5D Interposer
Conformal Shielding
Fan Out Multidie
Coreless Substrate
Antenna on Package
3D FOSystem in Package
Source: John Hunt, ASE
ICEPT Short Course on Heterogeneous Integration
DARPA’s Electronic Resurgence InitiativeThe Electronic Resurgence Initiative (ERI) will invest is
$500-$800 million ERI calls for 3D to overcome the current weakest link in
computers – the memory wall.
Objectives are:– 3DSoC technology demonstrated at
the end of the program (3.5 Years)– > 50X the performance at power
compared with 7nm 2D CMOS
ICEPT Short Course on Heterogeneous Integration
Sony DBI Package is in Galaxy S7Next generation will include stacked memory for 5X speed improvement and is projected to improve future robotics technology and support robotics manufacturing
ICEPT Short Course on Heterogeneous Integration
Sony DBI Package is in Galaxy S7Next generation will include stacked memory for 5X speed improvement and is projected to improve future robotics technology and support robotics manufacturing
ICEPT Short Course on Heterogeneous Integration
The DARPA CHIPS Program
An Important part of DARPA’s Electronic Resurgence Initiative
The Common Heterogeneous Integration and Intellectual Property IP Reuse Strategies Program (CHIPS) vision is an ecosystem of discrete modular, IP blocks, to be assembled into a system using existing and emerging integration technologies.
Modularity and reusability of such IP blocks will require electrical and physical interface standards supported by the CHIPS ecosystem.
ICEPT Short Course on Heterogeneous Integration
SiP Heterogenous Integration & New Architectures Allow Functional Component Upgrade Rapidly At Low Cost
We can add, subtract and replace layers with cost and time efficiency using the best
available for each active component
ICEPT Short Course on Heterogeneous Integration
System Requirements To Maintain The Pace Of Progress Higher bandwidth density Lower latency Increased performance Lower power Expanded data storage Heterogeneous Integration Ensured reliability Improved security
All at no increase in cost
ICEPT Short Course on Heterogeneous Integration
Packaging Is Facing A Revolution
To Maintain the pace of progress at the system level we must:– Design must start with the system– Co-design of electrical, photonic, mechanical, thermal management and
interconnect components– Design and simulation must then be partitioned into standard components
and processes where possible. This process requires full knowledge of the supply chain
ICEPT Short Course on Heterogeneous Integration
Change Everything In The New Product EcosystemFrom Design through Production and Final System Level Testing
Start With The System
EcosystemDesign
Materials
Equipment
IDM/Foundry OSAT
Fabless
EMS/PCB Assembly
System-OEM
ICEPT Short Course on Heterogeneous Integration
Change Everything In The New Product EcosystemFrom Design through Production and Final System Level Testing
Start With The System
EcosystemDesign
Materials
Equipment
IDM/Foundry OSAT
Fabless
EMS/PCB Assembly
System-OEM
This packaging revolution is underway today but in its infancy
ICEPT Short Course on Heterogeneous Integration
One ExampleDesign COST
The greatest limiting factor may be thedirect cost and time to market indirect costof Co-design and simulation.
ICEPT Short Course on Heterogeneous Integration
Design Cost Escalation Is Not Sustainable
This can not continue! 3D-SiP Packaging is growing in complexity resulting in NRE including co-design and co-simulation becoming the limiting factor
Small volume products cannot support the cost
Chip design cost is >$600M
ICEPT Short Course on Heterogeneous Integration
Co-Design And Simulation Impact NRE
We are designing systems in a package and both time to market and non-recurring engineering cost will not allow “build-characterize-modify” cycles to develop consumer product. The future cycle must be:
Product level design• Operating characteristics• Component selection• Materials selection• Process flow definition• Packaging design• Co-design of all characteristics• Electrical/optical/thermal/mechanical
Product Modeling and simulation• Verify all system characteristic in the
computer
Release for Production
Recycle through design
Fail
Pass
ICEPT Short Course on Heterogeneous Integration
Co-Design And Simulation Require Accurate Materials Properties, including thin-interface
dominated layers
Optimizing product characteristics in the computer saves time and money
We can’t do it today due to lack of software tools and unknown materials and interface properties
for thin layers
ICEPT Short Course on Heterogeneous Integration
Another Example Stress In Complex Heterogeneous 3D-SiP Is A
Primary Challenge To Reliability Differential CTE of materials Fragility of compound semiconductors relative to Si Thinner layers High processing temperatures Warpage for thin, large area die and packages Increasing thermal density Etc…..
These problems can be resolved with what we know today
ICEPT Short Course on Heterogeneous Integration
Another Example
Stress For Ever Thinner Layers Causes Warpage
Solutions for warpage are known and demonstrated but not integrated for production
Reduced CTE Copper Low modulus dielectrics No underfill Direct interconnect bonding All joining processing done at or near use case temperature
ICEPT Short Course on Heterogeneous Integration
Composite Cu PropertiesThis material should resolve stress due to CTE differences
Measured Properties show: The strength of the Cu-SWCNT composite is more than 2X pure Cu Ductility is significantly lower. Coefficient of thermal expansion ranges between 4 to 5.5x10-6/°C vs
17x10-6/°C for pure Cu.
ICEPT Short Course on Heterogeneous Integration
Low temp Cu Nano-solderReflow solder at low temp (<150C)Consistent with Direct Interconnect BondingThermal/electrical conductivity 10-15X that of SAC
ICEPT Short Course on Heterogeneous Integration
Direct Bond Interconnect Is Now In High Volume Production Samsung’s Galaxy S7 is the first high volume use of of
the Ziptronix’s DBI technologyBonding force is distributed over dielectric and
conductor interfacesNear use case temperature processing (<150C)No under fill required
Chipworks cross-section of CMOS image sensor shows DBI
for Copper pad connections
ICEPT Short Course on Heterogeneous Integration
The Warpage Problem For Ever Thinner Packaging is Resolved
Warpage problem is resolved No stress built in due to joining by soldering or thermal
compression bonding at temperatures well above “use case” temperature Limited stress induced due to differential CTE
The materials and processes needed have been demonstrated but not yet integrated
ICEPT Short Course on Heterogeneous Integration
Heterogeneous Integration in Photonic/Electronic SystemsComponents that will be assembled into complex 3D-SiPs may include: Monolithic photonic ICs (incorporating photonics, electronics and plasmonics) Other discrete optical components that are not integrated in the Silicon/photonic integrated circuits (SiPh-ICs). Si based logic and memory ICs MEMS devices LEDs, MicroLEDs and other optical emitters Plasmonic Components Sensors (including a growing list of photonic sensors) GaN power controller circuits RF circuits Compound (direct bandgap) semiconductor lasers Optical interconnects to and from the outside world Electrical interconnects to and from the outside world Passive components (including integrated passive devices) New devices and new materials that will be invented over the next 15 years
Many have unique thermal, electrical, mechanical characteristics that will require specialized materials and system integration (packaging)
processes and equipment
ICEPT Short Course on Heterogeneous Integration
New Device Types We Can Imagine TodayThese Devices And Their Packaging Will Use New Materials
Spin torque devices(2 magnetic junction pillars)
MEMS Photonic switchVertical coupler
Plasmomic emission Source(quantum dots and plasmons)
ICEPT Short Course on Heterogeneous Integration
New Device Types We Can Imagine Today
Integrated Photonics for quantum Info
processing Harvard Jan 2019
Nanoscale Vacuum Components; low standby THz transistors The latest in Spying Drones 2018
Photonic Devices for nanoelectromechanical metamaterials on-chip
acoustic at 10s MHx Cal Tech Jan 2019
ICEPT Short Course on Heterogeneous Integration
Data Collection In Semiconductor ManufacturingSemiconductor manufacturing in the fab leads all other
industries in data collectionAnn Kellehere, Senior VP of the Technology and Manufacturing Group at Intel, observed that “data is powering the fourth industry revolution. Today, fabs collect more than 5 billion sensor data points each day. The challenge is to turn massive amounts of data into valuable information”
The potential benefits of these data is only partially used today but increases in computer power and artificial technology is changing this. Autonomous real-time process optimization is coming.
ICEPT Short Course on Heterogeneous Integration
DataMining
Semiconductor Manufacturing Process data Manufacturing Monitoring “Other Data”
Real-Time Manufacturing OptimizationReal-Time Manufacturing Optimization
HyperStructureWork Flow Automation
YieldAnalysis
Energy dataAnalysis
EnvironmentalData Analysis
AI Driven Advanced Correlation
Knowledge Base
UserInterface
Management
Engineering• Reaction Design• Process• Product• Equipment• Yield• Energy USE• Environmental
Impact
• Reports• Visualization• Alarms
Real-time Optimization
ICEPT Short Course on Heterogeneous Integration
ConclusionsThe Resources to maintain the pace of progress are available New Materials New Device types New Interconnect structures New Computer and Communication Systems Data driven real-time optimization New architectures for logic, sensors and memory Heterogeneous Integration Technology HIR roadmap identifying future challenges today stimulating precompetitive
collaboration
The most critical ingredient may be our imagination which will usethese resources to maintain the pace of progress for decades to come.
ICEPT Short Course on Heterogeneous Integration
New System Architectures & System Integration
Technologies are needed To Meet Future Market
Demand
ICEPT Short Course on Heterogeneous Integration
Today’s Multi-die Packaging Integration Spectrum
Copyright 2017 Intel Corporation
Organic FCXGAA, FCCSP
IO/mm/lyr = 28‐34IO/mm2 = 83‐123
Bump Pitch = 110‐90µm
IO/mm = N/AIO/mm2 = 625
Bump Pitch = 40µm
High Density Organic Interposer
IO/mm/lyr = 100+*IO/mm2 = 331
Bump Pitch = 55µm
Si Interposer,
IO/mm/lyr = 250IO/mm2 331
Bump Pitch 55µm
Package Stacking
2D/2.5D (Side by Side MCPs) 3D (Die &/Or Package Stacking)
3/3 L/S
PoP Pitch 0.27mm
Many Package Options Exist!!Designers Pick the Optimal Solution for a Specific System
Die Stacking
Intel EMIB
* Oi et. al. 2014 ECTC report 2m L/S, 25m pad
Source: Babak Sabi, Intel Corporate VP, Semicon West SEMI & IEEE EPS Session July 11, 2017
ICEPT Short Course on Heterogeneous Integration
GPU and Stacked Memory HBM Integration (2.5D)Source: ASE
6
Decoupling capacitor
Decoupling capacitor
stiffener Stacked memory GPU stiffener
Package Substrate
Stacked memory
GPU dieStacked memoryHBM Stacked memory
HBM
ICEPT Short Course on Heterogeneous Integration
Selected ExamplesIntel Embedded Multi-die Interconnect Bridge
Intel Introduced the next generation of EMIB at Hot Chips 2017 Many die in one piece without large area interposer Components of different nodes in one piece Rapid deployment of advanced nodes Heterogeneous integration
Available to 14Ƞm Foundry Customers now
ICEPT Short Course on Heterogeneous Integration
GPU die
Micro bumps
Interposer
C4 bumps
Laminated chip carrier
BGA balls
Future Interconnect For HI 3D-SiP Is Here TodaySystem Level packaging For More Complex Products Is On The Way
ICEPT Short Course on Heterogeneous Integration
GPU die
Micro bumps
Interposer
C4 bumps
Laminated chip carrier
BGA balls
Complex 3D-SiP in volume production with high yield and reliability without known good die while
transistors wear out.This requires Intelligent redundancy, continuous test
while running, dynamic self-repair, and graceful degradation.
This has not yet been done with product that includes photonics but it is in process
Future Interconnect For HI 3D-SiP Is Here TodaySystem Level packaging For More Complex Products Is On The Way
ICEPT Short Course on Heterogeneous Integration
Complex 3D-SiP in volume production with high yield & reliability without known good die while transistors wear out.
This requires Intelligent redundancy, continuous test while running, dynamic self-repair, and graceful degradation.
This has not yet been done with product that includes photonics but it is in process
Future Interconnect For HI 3D-SiP Is Here TodayNew Emerging Test Challenges
ICEPT Short Course on Heterogeneous Integration
Light Detection and Ranging Demand is GrowingVolume is limited by cost & cost limited by volume
Lidar sensor for extended range: 64 beams, >200m range, priced at only $3,500 – least expensive high-performance sensor on the market.
Source: Ouster
ICEPT Short Course on Heterogeneous Integration
Light Detection and Ranging Demand is GrowingVolume is limited by cost & cost limited by volume
Lidar sensor for extended range: 64 beams, >200m range, priced at only $3,500 – least expensive high-performance sensor on the market.
Source: Ouster
Developers Project $50-$60 as volume rises and development continues in the next 5 years
ICEPT Short Course on Heterogeneous Integration
The comparison with standard product is dramatic even with conventional PCB assembly and standard off-the-shelf components Small size allows photonics to remain at rack unit edge
One ExampleMicro-server System Level Packaging Can Enable
Power, Cost and Performance Gains
40% faster with 70% of Intel Xeon E3-1230l power yields 2X the operations per watt
Source: Ronald P. Luijten MIT workshop ~ 10X size reduction
The only change was adoption of heterogeneous system integration
ICEPT Short Course on Heterogeneous Integration
40% smaller with 16Gb high bandwidth memory 4096 bit memory interface 512GB/s memory bandwidth Si interposer with TSV & µbump to package substrateLower power
What Could We Do with 3D packaging?
592mm2 ASIC 1011mm2
interposer
55mm
55m
m
~ 25X size reduction from convention PCB
ICEPT Short Course on Heterogeneous Integration
Photo source: Prismark/Binghamton University
A Second ExampleApple Watch Series 2: S2 SiP
WLCSP, FCCSP, QFN and passives in SiP PVD based EMI 2 compartment shield 98-layer substrate, 340µm thick 35-40µm vias
Source:
ICEPT Short Course on Heterogeneous Integration
Brain Implants Are Here Now With Far Reaching Implications For The Future
Brain wave control of an artificial arm
Source: Darpa Brain Program
Motor Cortex
ConnectionToday Tomorrow
Electrode Array implanted through the Skull
Electrode Array inserted through blood vessels
ICEPT Short Course on Heterogeneous Integration
Part IIISelected Roadmap Chapters
ICEPT Short Course on Heterogeneous Integration
Chapter 1Overview, Executive Summary, and
AcknowledgmentsTWG Leaders
Dr. William T. Chen, Chair of HIRDr. W. R. Bottoms, Co-Chair of HIR
This chapter is not yet released. It will be completed when all chapters of the2019 Edition of the Heterogeneous Integration Roadmap have completedpeer review and are released for publication.
ICEPT Short Course on Heterogeneous Integration
Executive SummaryElectronics are deeply embedded into the fabric of our society, changing the way we live, work and play while bringing new efficiencies to global lifestyle, industry, and business. We are entering the era of digital economy and myriad connectivity. The market forces driving data growth are:
Migration of data, logic, & applications to the cloud
Consumerization of IT with rise of Social Media
Revolution in our Mobile Devices
5 G together with Internet of Things to Internet of Everything
Artificial Intelligence with Virtual Reality(VR) & Augmented Reality (AR)
Autonomous Vehicles
ICEPT Short Course on Heterogeneous Integration
Chapter 2High Performance Computing and
Data Centers
This Chapter is published and can be downloaded from the HIR website.You can access it with the link below.
eps.ieee.org/hir
ICEPT Short Course on Heterogeneous Integration
High Performance Computing & Data Centers This chapter rationalizes the need for heterogeneous system integration realizing systems-in-a-package (SiPs) components targeting HPC and data center markets. We identify challenges that that must be overcome in developing these SiPs.
The processor-memory performance gap remains a key challenge but new factors for surmounting power dissipation, power delivery, security and package IO constraints.
In the 15-year term of the HIR new technologies such as quantum, neuromorphic, analog and other components into the data centers and high-performance information technology systems of the future.
Many of the issues are addressed in greater detail in other chapters.
ICEPT Short Course on Heterogeneous Integration
Future System in Package
ICEPT Short Course on Heterogeneous Integration
Future System in Package
Components and materisl discussed in more detail in other TWGs will be essential to realize this Vision
ICEPT Short Course on Heterogeneous Integration
Chapter 5Automotive Applications
This Chapter is published and can be downloaded from the HIR website.You can access it with the link below.
eps.ieee.org/hir
ICEPT Short Course on Heterogeneous Integration
Automotive Applications
This chapter provides a summary of key disruptivetrends in automotive electronics in the upcomingyears. The increased emphasis on autonomousdriving as well as electrification of vehicles hasresulted in enormous changes for semiconductorsand batteries used and their packaging andheterogeneous integration in next-generationautomobiles.
ICEPT Short Course on Heterogeneous Integration
Functional Blocks of Autonomous Vehicles
ICEPT Short Course on Heterogeneous Integration
Functional Blocks of Autonomous Vehicles
The Autonomous vehicle must have environmental awareness with a latency compatible with approach
velocities of 200 miles/hour
ICEPT Short Course on Heterogeneous Integration
Chapter 6Aerospace and Defense
This Chapter is published and can be downloaded from the HIR website.You can access it with the link below.
eps.ieee.org/hir
ICEPT Short Course on Heterogeneous Integration
Aerospace and DefenseThe mission of the HIR Technology Working Group (TWG) for Aerospace andDefense (A-D) is to identify challenges, provide guidance, and recommendsolutions to the A-D profession (industry, academia, and government) withsufficient lead time that they do not become roadblocks that prevent thecontinued implementation of leading-edge electronics in Aerospace and Defensesystems.
ICEPT Short Course on Heterogeneous Integration
Aerospace and Defense
ICEPT Short Course on Heterogeneous Integration
Chapter 8Single & MultiChip Integration
This Chapter is published and can be downloaded from the HIR website.You can access it with the link below.
eps.ieee.org/hir
ICEPT Short Course on Heterogeneous Integration
Single Chip and MultiChip IntegrationThis Single and Multichip Integration Chapter covers basic knowledge-base and physical manufacturing infrastructure tools across all market segments. IC devices start with wafers from foundries, thinned and singulated into “chips”. Wirebond remains the workhorse of the industry for interconnect but there will be very strong growth in dollar value for Flip Chip (BGA-CSP) and WLCSP, and high rapid dollar-value growth for advanced packages such as 2.5D and FO WLP/PLP.The “tool box” for device packaging will continue to evolve with new materials and processes enabling future generations of packaging meeting increasing demand for performance, miniaturization and cost per function
ICEPT Short Course on Heterogeneous Integration
Improvements in Materials and Processes Keep Older Packaging Viable
Driven by demand for smaller size, higher performance and lower power this will change dramatically by the
2034 end of this HIR edition.
ICEPT Short Course on Heterogeneous Integration
Foveros: Intel’s new 3D Stacking Technology From Greek word meaning “unique and special”
ICEPT Short Course on Heterogeneous Integration
Chapter 12RF, Analog Mixed Signal, and 5G
This Chapter is published and can be downloaded from the HIR website.You can access it with the link below.
eps.ieee.org/hir
ICEPT Short Course on Heterogeneous Integration
RF, Analog Mixed Signal and 5G
5G mobile communication represents a new opportunity for IC packagingthat is significantly different from previous generations of cellular-basedmobile wireless technologies. This roadmap identifies 5, 10, and 15-yearchallenges and provides for guidance for potential solutions. This will be aperpetual work-in-progress until the full vision for 5G is fully realized andit be updated as capabilities improve and new requirements arise.
Many challenges must be met including antennas, signal penetration, power requirement, integration with point-to-
point communication standards, etc.
ICEPT Short Course on Heterogeneous Integration
5G: A platform for Future Innovation
ICEPT Short Course on Heterogeneous Integration
Goals are known but Many Challenges Remain
ICEPT Short Course on Heterogeneous Integration
Chapter 14Modeling and Simulation
This Chapter is published and can be downloaded from the HIR website.You can access it with the link below.
eps.ieee.org/hir
ICEPT Short Course on Heterogeneous Integration
Modeling and Simulation
The Modeling and Simulation Chapter considers challenges and potential solutions for modeling and simulation tools in the following areas:
Electrical Analysis
Thermo-Mechanical Analysis
Mechanical and Multi-Physics Analysis
Molecular Modeling
Reliability and Prognostics
ICEPT Short Course on Heterogeneous Integration
Modeling and Simulation for HI is Complex
Accurate simulation must be available to ensure designs will work in the real world. Experiments must more from the fab to
the computer to control NRE cost. Many things are missing such as materials properties for new materials and ultra-thin layers.
ICEPT Short Course on Heterogeneous Integration
Modeling and SimulationMetrology must Improve as Feature Size Shrinks
ICEPT Short Course on Heterogeneous Integration
Chapter 16Emerging Research Devices
This Chapter is published and can be downloaded from the HIR website.You can access it with the link below.
eps.ieee.org/hir
ICEPT Short Course on Heterogeneous Integration
Emerging Research DevicesA 25-year horizon
The scope of this Chapter includes supporting other HIR Working Groups with new devices required to meet the difficult challenges they identify and assessing emerging research devices and technologies for this purpose. A list of Emerging Research Device types known today is included. However, the most important devices over the next 25 years, are likely to be types that we have not yet imagined.
ICEPT Short Course on Heterogeneous Integration
Emerging Research Devices
Nanoscale vacuum electronics Neuromorphic devices Quantum devices for information processing Spintronic devices Flexible electronics 3 dimensional stacked devices Nanowire electronics Carbon nanotube electronics Graphene electronics Other 2D material-based electronics
ICEPT Short Course on Heterogeneous Integration
Emerging Research Devices Continued
Plasmonic devices Power electronics Electronics for harsh environment – automotive and industrial Electronics for harsh environment – extreme temperature, radiation, vibration, etc.
New MEMS and Sensors both as components and integrated into sub-systems Phase change memory (both thin film and nanowire-based) Resistive random-access memory (both thin film and nanowire based) Ferroelectric memory NEMS based memory
Molecular memory
ICEPT Short Course on Heterogeneous Integration
Emerging Research Devices
Prototypes exist with source-drain distance of less than 50Ƞm
ICEPT Short Course on Heterogeneous Integration
Chapter 17Test Technology
This Chapter is published and can be downloaded from the HIR website.You can access it with the link below.
eps.ieee.org/hir
ICEPT Short Course on Heterogeneous Integration
Test TechnologyThe heterogeneous integration testing roadmap contains estimates of key trends influencing this industry over the next 15 years. This roadmap includes trends in semiconductor device technologies and their impact on test, as well as roadmaps for key test enablers (Device Handlers, Test Interfaces, and Test Methods). The resulting Cost of Test is also analyzed and discussed.
Device types include RF, Photonic, Logic, specialty devices, memory and analog/mixed signal devices.
Each device type has differences in test requirements based on the devices and the applications where they will be used.
ICEPT Short Course on Heterogeneous Integration
Test TechnologyFixtures must provide for both electrical and optical probes
ICEPT Short Course on Heterogeneous Integration
Test Technology
Wafer probe station for Photonic Integrated Circuit (PIC)
ICEPT Short Course on Heterogeneous Integration
Chapter 19Security
This Chapter is published and can be downloaded from the HIR website.You can access it with the link below.
eps.ieee.org/hir
ICEPT Short Course on Heterogeneous Integration
SecurityCybersecurity threats can manifest themselves either through software or hardware. The majority of threats occur through software attacks, providing access from many sources such as email attachments, fake web sites, unsecure wireless, social networking or infected USB drives. Software threats are generally not specific to the hardware and as such are outside the scope of the HI security roadmap.
Hardware threats are impacted by the design and integration of the hardware components of a chip and integration into a functional system at the package level, board level, and system level. Hardware attacks fall into 7 classes: interface leakage, supply-channel attacks, side channel attacks, chip counterfeiting, physical tampering with the system, fault injection attacks, and reverse engineering attacks.
ICEPT Short Course on Heterogeneous Integration
Security Controller ExampleInfrastructure IP Security with interfaces for each core
ICEPT Short Course on Heterogeneous Integration
Chapter 20Thermal
This Chapter is published and can be downloaded from the HIR website.You can access it with the link below.
eps.ieee.org/hir
ICEPT Short Course on Heterogeneous Integration
ThermalThermal problems and Challenges
2D chip with stacked memory on a silicon/glass interposer
3D stacked die with conduction interfaces
3D stacked die with embedded liquid cooling
Optics/photonics-based heterogeneous package
Harsh environment (military, aerospace, automobile)
Mobile application chipset (package-on-package, fan-out, bridge)
Voltage regulators in a heterogenous package
ICEPT Short Course on Heterogeneous Integration
Thermal ExampleCooling High Power 3D Chip
ICEPT Short Course on Heterogeneous Integration
Chapter 21SIP and Module Integration
This Chapter is published and can be downloaded from the HIR website.You can access it with the link below.
eps.ieee.org/hir
ICEPT Short Course on Heterogeneous Integration
SiP & Module Integration
Heterogenous integration through SiP (System-in-Package) leverages capabilities of advanced packaging to create systems close to SoC form factors with better yield, lower cost, higher flexibility, and faster time to market.
This chapter highlights market needs, technology paths, difficult challenges and potential solutions for high-density system integration with advanced packaging materials, tools and techniques. It addresses required developments for the next 10 to 15 years.
ICEPT Short Course on Heterogeneous Integration
SiP & Module IntegrationExample of SiP on Board and SiP in Board combined in a single package
SiP & Module IntegrationThe “tool Box” application areas
ICEPT Short Course on Heterogeneous Integration
Chapter 22Interconnects for 2D and 3D
Architectures
This Chapter is published and can be downloaded from the HIR website.You can access it with the link below.
eps.ieee.org/hir
ICEPT Short Course on Heterogeneous Integration
Interconnections for 2D and 3D Architectures
This chapter has two primary objectives:
Define and proliferate a new standardized nomenclature for package architectures covering and clearly demarcating both 2D and 3D constructions
Define and proliferate key metrics driving the evolution of the physical interconnects in these architectures.
The Scope of this chapter is restricted to electrical interconnects between one or more semiconductor devices.
ICEPT Short Course on Heterogeneous Integration
Interconnections for 2D and 3D ArchitecturesDifficult Challenges:
Increasing density, i.e. reduced line pitch. Increasing signal speeds will increase concerns about signal quality due to cross-talk caused by reduced line spacing. The challenges include solutions that minimize impact to signal integrity and provide physical links with improved power efficiency.
Greater need for novel assembly technologies for ultra-fine pitch enhanced-2D and 3D architectures using both solder and non-solder based approaches.
Key challenges for stacked-die architectures will continue to be fine pitch sort/test, thermal management, power delivery network, co-design processes, and equipment readiness for high volume.
ICEPT Short Course on Heterogeneous Integration
Interconnections for 2D and 3D Architectures
ICEPT Short Course on Heterogeneous Integration
Chapter 23Wafer-Level Packaging (WLP)
This Chapter is published and can be downloaded from the HIR website.You can access it with the link below.
eps.ieee.org/hir
ICEPT Short Course on Heterogeneous Integration
Wafer Level Packaging
The intent of this chapter is to provide a brief overview of Wafer Level Packaging (WLP), including Wafer Level Chip Scale Packaging (WLCSP) and Fan Out packaging, as a background for a roadmap for these technologies going forward. This chapter looks at WLP technology today and projects forward to future needs and challenges including those related to panel level processing.
ICEPT Short Course on Heterogeneous Integration
Wafer Level PackagingDifficult Challenges: There are reliability and chip package interaction (CPI) challenges as the size of
the WLCSPs increases. Adverse effects that can occur during subsequent processes after WLCSP
manufacture including shipping and handling, and final assembly. Singulation becomes more difficult as technology nodes shrink How can we deliver the panel level cost benefits for low volume parts Die Shift during reconstitution molding. Low temperature polymer for RDL isolation. Reconstituted wafer warpage during processing.
ICEPT Short Course on Heterogeneous Integration
Wafer level Packaging
ICEPT Short Course on Heterogeneous Integration
The Short Course Materials will be available for Registered Participants
For More Information about How to Participate Use The Links Below
bill_bottoms@3mts.comeps.ieee.org/hir
ICEPT Short Course on Heterogeneous IntegrationICEPT Short Course on Heterogeneous Integration
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