flot de conception des circuits intégrés
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Alain VachouxMicroelectronic Systems Laboratory
alain.vachoux@epfl.ch
EDA Based Design
Introduction
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A. Vachoux, 2005-2006 EDA Based Design Introduction - 2
Table of contents
Some definitions Full-custom design flow Semi-custom (standard cell based) design flow
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Electronic Design Automation (EDA)
Category of (software) tools for designing and producing electronic systemsincluding printed circuit boards (PCBs), integrated circuits (ICs), or systemson chips (SoCs)
Alternative terms:Computer-aided engineering (CAE), computer-aided design (CAD) Largest EDA companies:
Cadence Design Systems (market value: US$ 3.5 billion)
Synopsys (market value: US$ 2.5 billion) Mentor Graphics (market value: US$ 1.0 billion)
Magma Design Automation (market value: US$ 387 million)
To probe further: http://www.eda.org/ -- standard working groups
http://www.edacafe.com/ -- commercial site
http://www.dac.com/ -- main conference in US
http://www.date-conference.com/ -- main conference in Europe
http://www.deepchip.com/ -- AYNTKBATA about EDA
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A. Vachoux, 2005-2006 EDA Based Design Introduction - 4
Design process/flow (1/2)
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A. Vachoux, 2005-2006 EDA Based Design Introduction - 5
Design process/flow (2/2)
Requirements Whatthe system should do
Characteristics or features of the
desired (required) system
Specifications Result of the requirement
analysis
Items, materials, or services
Procedures for validating the
requirements
Architecture design Howthe system should work Hardware/software partitioning
Hardware partitioning
(RF, analog, digital parts)
IP blocks (design reuse)
Architecture design (cont'd) Performance evaluation
(operability, speed, consumption,
area, etc.)
Component design Detailed/physical design
Block implementation
Manufacture At foundry location (ASIC) or device
programming (FPGA)
Test Functional/structural testing of
chip samples
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A. Vachoux, 2005-2006 EDA Based Design Introduction - 6
Design methodology
Series of standards, rules and procedures to optimize the designprocess/flow on the basis of particular criteria such as:
User's needs (performances)
Market relevance (cost)
Available resources (time to market)
EDA tools Specification tools
e.g., Matlab/Simulink, VHDL,
diagram editors
Design tools
e.g., schematic/layout editors, logic
synthesizers, place&route tools
Verification toolse.g., simulators, formal checkers,
DRC, LVS
Test tools
e.g., ATPG tools, fault simulators,
scan insertion tools
Technological process Full/semi-custom design
Process description (design
rules, device models)
Cell libraries (logic gates,
custom blocks)
IP libraries (memories, etc.)
Programmable devices (FPGA)Pre-placed configurable blocks
Programmable interconnects
IP blocks (memories,
processor cores, etc.)
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A. Vachoux, 2005-2006 EDA Based Design Introduction - 7
Full-custom design process/flow
Design Specifications
Schematic Capture
Symbol creation
Simulation
Layout
DRC- Design Rule Check
Parasitics Extraction
LVS Layout versus Schematic Check
Post-Layout Simulation
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A. Vachoux, 2005-2006 EDA Based Design Introduction - 8
Full-custom design process/flow
Design Specifications
Schematic Capture
Symbol creation
Simulation
Layout
DRC- Design Rule Check
Parasitics Extraction
LVS Layout versus Schematic Check
Post-Layout Simulation
Technology: 0.8 um twin-well CMOS
Propagation delay of "sum" and "carry_out" signals < 1.2 ns (worst case)
Transition times of "sum" and "carry_out" signals
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A. Vachoux, 2005-2006 EDA Based Design Introduction - 9
Full-custom design process/flow
Design Specifications
Schematic Capture
Symbol creation
Simulation
Layout
DRC- Design Rule Check
Parasitics Extraction
LVS Layout versus Schematic Check
Post-Layout Simulation
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A. Vachoux, 2005-2006 EDA Based Design Introduction - 10
Full-custom design process/flow
Design Specifications
Schematic Capture
Symbol creation
Simulation
Layout
DRC- Design Rule Check
Parasitics Extraction
LVS Layout versus Schematic Check
Post-Layout Simulation
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A. Vachoux, 2005-2006 EDA Based Design Introduction - 11
Full-custom design process/flow
Design Specifications
Schematic Capture
Symbol creation
Simulation
Layout
DRC- Design Rule Check
Parasitics Extraction
LVS Layout versus Schematic Check
Post-Layout Simulation
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A. Vachoux, 2005-2006 EDA Based Design Introduction - 12
Full-custom design process/flow
Design Specifications
Schematic Capture
Symbol creation
Simulation
Layout
DRC- Design Rule Check
Parasitics Extraction
LVS Layout versus Schematic Check
Post-Layout Simulation
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A. Vachoux, 2005-2006 EDA Based Design Introduction - 13
Full-custom design process/flow
Design Specifications
Schematic Capture
Symbol creation
Simulation
Layout
DRC- Design Rule Check
Parasitics Extraction
LVS Layout versus Schematic Check
Post-Layout Simulation
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A. Vachoux, 2005-2006 EDA Based Design Introduction - 14
Full-custom design process/flow
Design Specifications
Schematic Capture
Symbol creation
Simulation
Layout
DRC- Design Rule Check
Parasitics Extraction
LVS Layout versus Schematic Check
Post-Layout Simulation
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A. Vachoux, 2005-2006 EDA Based Design Introduction - 15
Full-custom design process/flow
Design Specifications
Schematic Capture
Symbol creation
Simulation
Layout
DRC- Design Rule Check
Parasitics Extraction
LVS Layout versus Schematic Check
Post-Layout Simulation
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A. Vachoux, 2005-2006 EDA Based Design Introduction - 16
Full-custom design process/flow
Design Specifications
Schematic Capture
Symbol creation
Simulation
Layout
DRC- Design Rule Check
Parasitics Extraction
LVS Layout versus Schematic Check
Post-Layout Simulation
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A. Vachoux, 2005-2006 EDA Based Design Introduction - 17
Semi-custom design process/flow
Design Specifications
HDL RTL coding
RTL simulation
Logic Synthesis
Gate-Level Simulation
Standard Cell Place and Route
Timing Delay Extraction
Backannotated Gate-Level Simulation
System Integration
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A. Vachoux, 2005-2006 EDA Based Design Introduction - 18
Semi-custom design process/flow
Design Specifications
HDL RTL coding
RTL simulation
Logic Synthesis
Gate-Level Simulation
Standard Cell Place and Route
Timing Delay Extraction
Backannotated Gate-Level Simulation
System Integration
Technology: 0.8 um twin-well CMOS
Propagation delay of "sum" and "carry_out" signals < 1.2 ns (worst case)
Transition times of "sum" and "carry_out" signals
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A. Vachoux, 2005-2006 EDA Based Design Introduction - 19
Semi-custom design process/flow
Design Specifications
HDL RTL coding
RTL simulation
Logic Synthesis
Gate-Level Simulation
Standard Cell Place and Route
Timing Delay Extraction
Backannotated Gate-Level Simulation
System Integration
entity addsub is
generic (NBITS: natural := 4);
port (
clk, rst, add: in std_logic;
a, b: in unsigned(NBITS-1 downto 0);
z : out unsigned(NBITS-1 downto 0));
end entity addsub;
architecture dfl of addsub is
signal a_reg, b_reg, z_reg: unsigned(NBITS-1 downto 0);
begin
process (rst, clk)
begin
if rst = '1' then
a_reg '0');
b_reg '0');z '0');
elsif clk'event and clk = '1' then
a_reg
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A. Vachoux, 2005-2006 EDA Based Design Introduction - 20
Semi-custom design process/flow
Design Specifications
HDL RTL coding
RTL simulation
Logic Synthesis
Gate-Level Simulation
Standard Cell Place and Route
Timing Delay Extraction
Backannotated Gate-Level Simulation
System Integration
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A. Vachoux, 2005-2006 EDA Based Design Introduction - 21
Semi-custom design process/flow
Design Specifications
HDL RTL coding
RTL simulation
Logic Synthesis
Gate-Level Simulation
Standard Cell Place and Route
Timing Delay Extraction
Backannotated Gate-Level Simulation
System Integration
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A. Vachoux, 2005-2006 EDA Based Design Introduction - 22
Semi-custom design process/flow
Design Specifications
HDL RTL coding
RTL simulation
Logic Synthesis
Gate-Level Simulation
Standard Cell Place and Route
Timing Delay Extraction
Backannotated Gate-Level Simulation
System Integration
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A. Vachoux, 2005-2006 EDA Based Design Introduction - 23
Semi-custom design process/flow
Design Specifications
HDL RTL coding
RTL simulation
Logic Synthesis
Gate-Level Simulation
Standard Cell Place and Route
Timing Delay Extraction
Backannotated Gate-Level Simulation
System Integration
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A. Vachoux, 2005-2006 EDA Based Design Introduction - 24
Semi-custom design process/flow
Design Specifications
HDL RTL coding
RTL simulation
Logic Synthesis
Gate-Level Simulation
Standard Cell Place and Route
Timing Delay ExtractionBackannotated Gate-Level Simulation
System Integration
(TIMESCALE 1ns)
(CELL(DELAY
(ABSOLUTE
(INTERCONNECT clk z_regx7x/C (0.0045:0.0045:0.0045) (0.0045:0.0045:0.0045))
(INTERCONNECT clk z_regx6x/C (0.0044:0.0044:0.0044) (0.0044:0.0044:0.0044))
(INTERCONNECT clk z_regx5x/C (0.0044:0.0044:0.0044) (0.0044:0.0044:0.0044))
(INTERCONNECT clk z_regx4x/C (0.0044:0.0044:0.0044) (0.0044:0.0044:0.0044))(INTERCONNECT clk z_regx3x/C (0.0043:0.0043:0.0043) (0.0043:0.0043:0.0043))
(INTERCONNECT clk z_regx2x/C (0.0046:0.0046:0.0046) (0.0046:0.0046:0.0046))
...
(CELL
(CELLTYPE "INV3")
(INSTANCE U93)(DELAY
(ABSOLUTE
(IOPATH A Q (0.6556:0.6556:0.6556) (0.411:0.411:0.411))))
)
...
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A. Vachoux, 2005-2006 EDA Based Design Introduction - 25
Semi-custom design process/flow
Design Specifications
HDL RTL coding
RTL simulation
Logic Synthesis
Gate-Level Simulation
Standard Cell Place and Route
Timing Delay Extraction
Backannotated Gate-Level Simulation
System Integration
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A. Vachoux, 2005-2006 EDA Based Design Introduction - 26
Acronyms
AYNTKBATA: All You Need To Know But Afraid To AskASIC: Application-Specific Integrated CircuitASSP: Application-Specific Standard ProductATPG: Automatic Test Pattern GeneratorCAD: Computer-Aided DesignDRC: Design Rule CheckEDA: Electronic Design AutomationHDL: Hardware Description LanguageIP: Intellectual PropertyLVS: Layout Versus SchematicRTL: Register Transfer LevelSoC: System on ChipVHDL: Very high-speed integrated circuit HDL
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