experimental software receiver o f signals of satellite navigation systems

EXPERIMENTAL SOFTWARE RECEIVER

OF SIGNALS OF SATELLITE NAVIGATION SYSTEMS

František VEJRAŽKA, Pavel KOVÁŘ, Libor SEIDL, Petr KAČMAŘÍK

Czech Technical University in PragueDepartment of Radio Engineering

Technická 2, 166 27 Praha 6, Czech Republic

Phone: +420 2 2435 2246, fax +420 2 2435 5829

vejrazka@fel.cvut.cz

AGENDA

• Introduction

• Receiver architecture

• Receiver software architecture

• Validation project

• Validation results

• Future plans

• Conclusion

INTRODUCTION

• Task: Participation of the Czech Republic in GALILEO project

• It needs: Different algorithms dependent on implementation character

EXPERIMENTAL RECEIVERFOR SATELLITE NAVIGATION

INTRODUCTIONContribution describes:• Experimental receiver as a tool for research

in GNSS– processing of the signals of present and

future GNSS– GNSS signal processing algorithms

development and testing• Validation of the receiver

– architecture– hardware– FPGA development method– SW development flow– implementation GPS L1 CA code receiver

AGENDA

• Introduction

• Receiver architecture

• Receiver software architecture

• Validation project

• Validation results

• Future plans

• Conclusion

RECEIVER ARCHITECTURERequirements

• Processing of all known and planned SATNAV signals:– GPS L1, L2, L5– GLONASS– EGNOS, WAAS– GALILEO

• Flexible design and development of powerful algorithms of signal processing

• Easy implementation of them• Rapid and simple prototyping and testing

Software Defined Radio

RECEIVER ARCHITECTURE

LNA

Channel 1

Cannel 2LNA

A/D FPGAVirtex II

PCI Bridge

DSP Xilinx

DSP UnitRadio Frequency UnitGNSS antenna

Synthetiser

High PowerComputer

• Radio Frequency unit• DSP Unit• High Power Computer

RECEIVER ARCHITECTURE

LNA

Channel 1

Cannel 2LNA

A/D FPGAVirtex II

PCI Bridge

DSP Xilinx

DSP UnitRadio Frequency UnitGNSS antenna

Synthetiser

High PowerComputer

• Radio Frequency Unit• DSP Unit• High Power Computer

Parameters:• frequency band 1 – 2 GHz• bandwidth 2 - 35 MHz adjustable• frequency tuning step 100 kHz

RECEIVER ARCHITECTUREHardware Radio Frequency Unit realization

RECEIVER ARCHITECTUREHardware

Radio Frequency Unit realization in 19“ rack

RECEIVER ARCHITECTURE

LNA

Channel 1

Cannel 2LNA

A/D FPGAVirtex II

PCI Bridge

DSP Xilinx

DSP UnitRadio Frequency UnitGNSS antenna

Synthetiser

High PowerComputer

• Radio Frequency unit• DSP Unit• High Power Computer

Parameters:• two 14 bits A/D converters• sample frequency up to 65 MHz• sufficient computational power for 40 MHz bandwidth

RECEIVER ARCHITECTUREDSP UnitSoftware design flow

VHDL compilation

VHDL synthesis

Simulink model Auxiliary VHDL blocks

VHDL program

Testing, simulation

FPGA implementation

FPGA testing

RECEIVER ARCHITECTURE

LNA

Channel 1

Cannel 2LNA

A/D FPGAVirtex II

PCI Bridge

DSP Xilinx

DSP UnitRadio Frequency UnitGNSS antenna

Synthetiser

High PowerComputer

• Radio Frequency unit• DSP Unit• High Power Computer

Parameters• PC computer with WINDOWS 2000 OS• planed: Embedded RT Kernel • multithread software

AGENDA

• Introduction

• Receiver architecture

• Receiver software architecture

• Validation project

• Validation results

• Future plans

• Conclusion

RECEIVER ARCHITECTUREHigh Power Computer (HPC) UnitSoftware architecture

• modularity, portability– ANSI C/C++

– multithreading

– interproces communication through shared memory

• multiplatform solution• PC (i686)

– system Win32, Linux

• Embedded application (Virtex II-Pro - PPC-405)– Real-Time kernel (Micro-C)

RECEIVER ARCHITECTUREHigh Power Computer (HPC) UnitSoftware library structure

• Channel handling and control

• Raw measurement processing

- filtration

- verification (RAIM)

• Data demodulation and interpretation

• Satellite position determination

• Coordinate transformation

• Atmospheric correction

• User position estimation and verification

• System integrity monitoring

• System augmentation of differential measurement

• User interface

AGENDA

• Introduction

• Receiver architecture

• Receiver software architecture

• Validation project

• Validation results

• Future plans

• Conclusion

VALIDATION PROJECT

• Validation of the receiver– architecture– hardware– FPGA development method– SW development flow

• Implementation GPS L1 CA code receiver

Array of channels(Virtex II)

Searchand tracking

Raw measurement conversion

Data demodulationData interpretation

and archiving

Position determinationSystem integrity monitoring

Channelshandling

and control

Radiofreq. part

User interface

User interface

User interface

VALIDATION PROJECTImplementation GPS L1 C/A code receiver

VALIDATION PROJECTDSP UnitImplementation GPS L1 C/A code receiver Correlator structure

VALIDATION PROJECTDSP UnitImplementation GPS L1 C/A code receiver Correlator realization

VALIDATION PROJECTDSP UnitImplementation GPS L1 C/A code receiver Correlator realization

32 bits NCO and PRN generatorof GPS and EGNOS codes

VALIDATION PROJECTDSP UnitImplementation GPS L1 C/A code receiver Correlator realization

32 bits NCO and PRN generatorof GPS and EGNOS codes

32 bits NCOand complex (IQ) mixer

VALIDATION PROJECTDSP UnitImplementation GPS L1 C/A code receiver Correlator realization - state diagram of the correlator service routine

AGENDA

• Introduction

• Receiver architecture

• Receiver software architecture

• Validation project

• Validation results

• Future plans

• Conclusion

Code delay error

Early – Late envelopeestimation of the mean envelope level (dot)

In phase and Quadrature output of the correlator

Frequency error

Phase error

Code delay error

Early – Late envelopeestimation of the mean envelope level (dot)

In phase and Quadrature output of the correlator

Frequency error

Phase error

Code delay error

Early – Late envelopeestimation of the mean envelope level (dot)

In phase and Quadrature output of the correlator

Frequency error

Phase error

Code delay error

Early – Late envelopeestimation of the mean envelope level (dot)

In phase and Quadrature output of the correlator

Frequency error

Phase error

Code delay error

Early – Late envelopeestimation of the mean envelope level (dot)

In phase and Quadrature output of the correlator

Frequency error

Phase error

Code delay error

Early – Late envelopeestimation of the mean envelope level (dot)

In phase and Quadrature output of the correlator

Frequency error

Phase error

AGENDA

• Introduction

• Receiver architecture

• Receiver software architecture

• Validation project

• Validation results

• Future plans

• Conclusion

FUTURE PLANS

• Implementation of GPS L2 CA code

• Diversity reception of EGNOS

• Implementation of Galileo

Realized and planed tasks

GPS + EGNOS

GPS + GALILEO

Signal processing Positioning methods

GPS L1 C/A code

EGNOS

GPS L2 C/A code

GPS L1/L2 P-code

GLONASS

GALILEO

GPS code based positioning

DGPS

GPS + GLONASS

Problem:signal reception in hard conditions

• under leaves canopy• in hollowed tracks• in street canyons• inside buildings• etc.

Solution:Assisted GNSS (AGNSS)

FUTURE PLANS

• Implementation of GPS L2 CA code

• Diversity reception of EGNOS

• Implementation of Galileo

• AGPS

AGENDA

• Introduction

• Receiver architecture

• Receiver software architecture

• Validation project

• Validation results

• Future plans

• Conclusion

CONCLUSION

• Experimental receiver was validated– Architecture of the receiver was confirmed– Complete development process of the

application was verified– Performance of the FPGA was approved

• Experimental receiver is ready for implementation of the new GNSS signals and for signal processing

Thank you for your attention.Pavel Kovář

&František Vejražka

&Libor Seidl

Czech Technical UniversityPrague

http://radio.feld.cvut.cz/personal/vejrazka