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A linear 32.8 dBm 2.4 GHz LDMOS power amplifier in 65 nm CMOS
Ted Johansson, Olof Bengtsson, Sara Lo5i, Lars
Vestling, Hans Norström, Jörgen Olsson, and Chris=an Nyström
Outline
• Background: WLAN IC technology roadmap • PA device design in 65 nm CMOS • Testchip • Results: DC, RF small-‐signal, LP, PA, reliability • Summary, conclusion
WLAN IC technology roadmap
1st/2nd genera=on WLAN circuits consisted of several chips: -‐ WiFi BB in digital CMOS -‐ Separate Bluetooth chip -‐ WiFi RF in BiCMOS with SiGe BJT
PA
Today a single chip solu=on is wanted using advanced CMOS. But: -‐ SiGe is not available -‐ Power MOSFET is needed
for PA
Nanoradio AB
To obtain maximum power into a load: -‐ use high supply voltage
technology (foundry technology, with or without process add-‐ons) circuit solu=on that can handle higher voltage, e.g. cascodes select PA-‐class with low voltage swing (rela=ve to Vdd)
-‐ use power combinaJon (use current instaed of voltage) low load, and transforma=on to 50 Ω. differen=al amplifiers (larger devices possible to use with same matching) power combina=on using passive networks, e.g. inductor or transformers
Put all "bells and whistle" together to achieve a good PA!
Challenges of PA design in nm technologies
To obtain maximum power into a load: -‐ use high supply voltage
technology (foundry technology, with or without process add-‐ons) circuit solu=on that can handle higher voltage, e.g. cascodes select PA-‐class with low voltage swing (rela=ve to Vdd)
-‐ use power combinaJon (use current instaed of voltage) low load, and transforma=on to 50 Ω. differen=al amplifiers (larger devices possible to use with same matching) power combina=on using passive networks, e.g. inductor or transformers
Put all "bells and whistle" together to achieve a good PA!
Challenges of PA design in nm technologies
Design of CMOS WLAN-‐PA Specifications (similar to SiGe HBT/Si BJT from exisJng WLAN products): VDD=3.3 V
=> BVCBO or BVDSS >6-‐7 V, up to 10 V for ruggedness RON around 2 Ωmm ION > 500 mA/mm fT > 20 GHz fmax > 20GHz Digital CMOS in 65 nm has technology that is very hard to use for PAs:
Vdd=1-‐1.5 V Tox=1.2-‐1.8 nm Lg=30-‐50 nm
IO-‐devices with Lg=350-‐500 nm for 2.5 – 3.3 V opera=on, with thicker gate oxide exist
Challenges: -‐ Protect gate oxide from high electric fields -‐ reliability -‐ Design extended drain drih region for op=mum current drive and breakdown voltage
Different HV MOSFET architectures in bulk CMOS
Ref. Bianchi CICC'09
Different HV MOSFET architectures in bulk CMOS
Ref. Bianchi CICC'09
RF-‐LDMOS design • 65 nm foundry CMOS process (no process changes possible) • No extra mask layers (only drawing layers for mask genera=on) => RF-‐LDMOS (EDMOS) has been developed.
Test chip manufactured at foundry.
2.5 x 4 mm2
DC and RF small-‐signal results W/L = 200/0.35 (10 fingers*20 um, 1 unit cell)
• BVDSS > 10 V • RON ≈ 2 Ωmm • ION > 600 mA/mm • fT=25 GHz • fmax=30 GHz
• Specifica=on filled!
Load-‐pull measurements
G D
S
S
S
S
40
30 20
10
0
-10 -25 -15 -5 5 15
P OU
T (d
Bm
) PIN (dBm)
AB 30% A*
25 15
5
-5
-15
-25 -15 -5PIN (dBm5) 15 25
P OU
T (d
Bm
) AB 10% AB 30% A*
Vdd=3.3 V 2.45 GHz
Vdd=5 V 5.8 GHz
Very good performance at both frequency bands and at higher supply voltage. P-‐1dB>1W, 50% eff
GSG test transistors for load-‐pull, W=2.8 mm (14 unit cells).
• Target Pout,peak >30 dBm => WLAN modulated 20-‐24 dBm signal.
• Differen=al PA => 4x beper impedance levels.
• Total transistor width = 5.6 mm (W=2 x 2.8 mm, 2 x 14 unit cells).
• Reference design: conven=onal cascode with 2 x 3.3 V IO transistors.
PA measurements
Direct bonding on PCB
Soldered test board
PA results
Reliability DC stress performed at high electric field and typical quiescent current for class AB. IDQ drih is caused by electron injec=on in the gate oxide resul=ng in increase of threshold voltage.
-5
-4
-3
-2
-1
0
1
101 102 103 104 105 106 107 108 109
Drift in IDQ
∆ID
(%)
Time (sec)
10 years
Vg=1.5 V, Vd=5.4 V
Less than 2% driU at 10 years (extrapolated)
Summary • Developed LDMOS transistors meet performance requirement
• WLAN PA with power-‐MOSFET possible in 65nm CMOS
• Solu=ons scalable for PA down to 28 nm for SoC WLAN, pico-‐basesta=ons, and other RF-‐ICs.
Hans Norström (UU), Klas-‐Håkan Eklund (Comheat), Lars Vestling (Comheat/UU), Ted Johansson (LiU), Sara Lo5i (UU), Jörgen Olsson (UU) Christian Nyström (Nanoradio)
BACKUP
Linear class-‐AB design Vdrain <= 2 Vdd
Alterna=ve A: using conven=onal circuit solu=on that can tolerate 2Vdd at drain, a cascode:
PA core, incl. =edown and sub con two-‐transistor cascode, upper T using twell, capacitor to gnd (CB), gate to Vdd.
Linear class-‐AB design Vdrain <= 2 Vdd
Alterna=ve B: using device that can tolerate high Vdd at drain, such as an EDMOS device:
PA core, incl. =edown and sub con
Full cascode circuit in Cadence, including input/output diff matching. EDMOS similar schema=cs.
Test board layout
2-‐lagers Au-‐pläterat t=508 um er=4,2 4,0 x 2,9 mm2
Evalua=on
Evalua=on
WLAN PA • Transistors with 5.6 mm width mounted on PCB and characterized at
Nanoradio AB. Differen=al PA, Vdd=3 V, f=2412 MHz P-‐1dB = 32,5 dBm (1,8 W). Class AB, efficiency over 50 % for unmodulated signal.
Load-‐pull measurements GSG test transistors for load-‐pull, W=2.8 mm.
G
S
S
D
S
S
Very good performance at both frequency bands and at higher supply voltage. P-‐1dB>1W, 50% eff
WLAN modulated signal 802.11g, f=2412 MHz, 54 Mbps OFDM
Both EDMOS and Cascode reference pass frequency mask test up to the limits of the used signal source (peak Pout >27 dBm).
EDMOS Cascode 2xIO
0
1
2
3
4
5
6
7
8
9
10 15 20 25
EVM [%
]
Pout (peak) [dBm]
Cascode
EDMOS
EVM measurement (linearity) shows less linearity for the EDMOS compared to the Cascode reference. If this comes from device performance, or matching circuit condi=ons, is not fully clear.
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